u-boot-imx-20220922

-------------------
 
 Fixes for 2022.10
 
 CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13548
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Merge tag 'u-boot-imx-20220922' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220922
-------------------

Fixes for 2022.10

CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13548

arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi

@@ -129,6 +129,57 @@
 	phy-reset-post-delay = <1>;
 };
 
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		lan1: port@0 {
+			phy-handle = <&sw_phy0>;
+		};
+
+		lan2: port@1 {
+			phy-handle = <&sw_phy1>;
+		};
+
+		lan3: port@2 {
+			phy-handle = <&sw_phy2>;
+		};
+
+		lan4: port@3 {
+			phy-handle = <&sw_phy3>;
+		};
+	};
+
+	mdios {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mdio@0 {
+			reg = <0>;
+			compatible = "microchip,ksz-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sw_phy0: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+
+			sw_phy1: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+
+			sw_phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+
+			sw_phy3: ethernet-phy@3 {
+				reg = <0x3>;
+			};
+		};
+	};
+};
+
 &pinctrl_fec1 {
 	u-boot,dm-spl;
 };

arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi

@@ -162,6 +162,65 @@
 	u-boot,dm-spl;
 };
 
+&switch {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		lan1: port@0 {
+			phy-handle = <&sw_phy0>;
+		};
+
+		lan2: port@1 {
+			phy-handle = <&sw_phy1>;
+		};
+
+		lan3: port@2 {
+			phy-handle = <&sw_phy2>;
+		};
+
+		lan4: port@3 {
+			phy-handle = <&sw_phy3>;
+		};
+
+		lan5: port@4 {
+			phy-handle = <&sw_phy4>;
+		};
+	};
+
+	mdios {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mdio@0 {
+			reg = <0>;
+			compatible = "microchip,ksz-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			sw_phy0: ethernet-phy@0 {
+				reg = <0x0>;
+			};
+
+			sw_phy1: ethernet-phy@1 {
+				reg = <0x1>;
+			};
+
+			sw_phy2: ethernet-phy@2 {
+				reg = <0x2>;
+			};
+
+			sw_phy3: ethernet-phy@3 {
+				reg = <0x3>;
+			};
+
+			sw_phy4: ethernet-phy@4 {
+				reg = <0x4>;
+			};
+		};
+	};
+};
+
 &usdhc2 {
 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
 	assigned-clock-rates = <400000000>;

arch/arm/include/asm/arch-imx8m/imx-regs.h

@@ -27,6 +27,7 @@
 #define IOMUXC_GPR_BASE_ADDR	0x30340000
 #define OCOTP_BASE_ADDR		0x30350000
 #define ANATOP_BASE_ADDR	0x30360000
+#define SNVS_BASE_ADDR		0x30370000
 #define CCM_BASE_ADDR		0x30380000
 #define SRC_BASE_ADDR		0x30390000
 #define GPC_BASE_ADDR		0x303A0000
@@ -113,6 +114,10 @@
 #define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
 #define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
 
+#define SNVS_LPSR			0x4c
+#define SNVS_LPLVDR			0x64
+#define SNVS_LPPGDR_INIT		0x41736166
+
 struct iomuxc_gpr_base_regs {
 	u32 gpr[47];
 };

arch/arm/mach-imx/imx8m/soc.c

@@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event)
 }
 EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
 
+static void imx8m_setup_snvs(void)
+{
+	/* Enable SNVS clock */
+	clock_enable(CCGR_SNVS, 1);
+	/* Initialize glitch detect */
+	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
+	/* Clear interrupt status */
+	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
+}
+
 int arch_cpu_init(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -594,6 +604,8 @@ int arch_cpu_init(void)
 			writel(0x200, &ocotp->ctrl_clr);
 	}
 
+	imx8m_setup_snvs();
+
 	return 0;
 }
 

board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c

@@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size)
 	return 0;
 }
 
-/* IMX8M SNVS registers needed for the bootcount functionality */
-#define SNVS_BASE_ADDR			0x30370000
-#define SNVS_LPSR			0x4c
-#define SNVS_LPLVDR			0x64
-#define SNVS_LPPGDR_INIT		0x41736166
-
-static void setup_snvs(void)
-{
-	/* Enable SNVS clock */
-	clock_enable(CCGR_SNVS, 1);
-	/* Initialize glitch detect */
-	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
-	/* Clear interrupt status */
-	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
-}
-
 static void setup_mac_address(void)
 {
 	unsigned char enetaddr[6];
@@ -99,7 +83,6 @@ static void setup_boot_device(void)
 
 int board_init(void)
 {
-	setup_snvs();
 	return 0;
 }
 

board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c

@@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
 	return 0;
 }
 
-/* IMX8M SNVS registers needed for the bootcount functionality */
-#define SNVS_BASE_ADDR			0x30370000
-#define SNVS_LPSR			0x4c
-#define SNVS_LPLVDR			0x64
-#define SNVS_LPPGDR_INIT		0x41736166
-
-static void setup_snvs(void)
-{
-	/* Enable SNVS clock */
-	clock_enable(CCGR_SNVS, 1);
-	/* Initialize glitch detect */
-	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
-	/* Clear interrupt status */
-	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
-}
-
 static void setup_eqos(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
@@ -145,7 +129,6 @@ int board_init(void)
 {
 	setup_eqos();
 	setup_fec();
-	setup_snvs();
 	return 0;
 }
 

board/menlo/mx8menlo/mx8menlo.c

@@ -12,24 +12,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <spl.h>
 
-#define SNVS_BASE_ADDR		0x30370000
-#define SNVS_LPSR		0x4c
-#define SNVS_LPLVDR		0x64
-#define SNVS_LPPGDR_INIT	0x41736166
-
-static void setup_snvs(void)
-{
-	/* Enable SNVS clock */
-	clock_enable(CCGR_SNVS, 1);
-	/* Initialize glitch detect */
-	writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
-	/* Clear interrupt status */
-	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
-}
-
 void board_early_init(void)
 {
 	init_uart_clk(1);
-
-	setup_snvs();
 }

configs/kontron-sl-mx8mm_defconfig

@@ -39,7 +39,6 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-# CONFIG_SPL_FIT_IMAGE_TINY is not set
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_POWER=y

doc/imx/habv4/csf_examples/mx8m/csf.sh

@@ -40,7 +40,7 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
 # fitImage tree
 fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
 fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
-fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) )
+fit_block_size=$(printf "0x%x" $(( ( ($(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
 sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp
 
 # U-Boot