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drivers/ddr/fsl: Fix DDR4 RDIMM support

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For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2018-01-29 09:44:33 -08:00
parent a9b1c2164a
commit 426230a65f
4 changed files with 41 additions and 22 deletions
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1
include/fsl_ddr_sdram.h
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@ -408,6 +408,7 @@ typedef struct memctl_options_s {
unsigned int rcw_override;
unsigned int rcw_1;
unsigned int rcw_2;
unsigned int rcw_3;
/* control register 1 */
unsigned int ddr_cdr1;
unsigned int ddr_cdr2;