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x86: coral: Add information about building / running
Add detailed information on how to build the coral image, since it needs binary blobs. Provide a way to avoid the memory-training delay. Also show the console output from a sample run. Signed-off-by: Simon Glass <sjg@chromium.org>
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Simon Glass
parent
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1 changed files with 217 additions and 17 deletions
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@ -16,6 +16,169 @@ Note that booting U-Boot on APL is already supported by coreboot and
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Slim Bootloader. This documentation refers to a 'bare metal' port.
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Slim Bootloader. This documentation refers to a 'bare metal' port.
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Building
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--------
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First, you need the following binary blobs:
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* descriptor.bin - Intel flash descriptor
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* fitimage.bin - Base flash image structure
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* fsp_m.bin - FSP-M, for setting up SDRAM
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* fsp_s.bin - FSP-S, for setting up Silicon
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* vbt.bin - for setting up display
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These binaries do not seem to be available publicly. If you have a ROM image,
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such as santa.bin then you can do this::
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cbfstool santa.bin extract -n fspm.bin -f fsp-m.bin
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cbfstool santa.bin extract -n fsps.bin -f fsp-s.bin
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cbfstool santa.bin extract -n vbt-santa.bin -f vbt.bin
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mkdir tmp
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cd tmp
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dump_fmap -x ../santa.bin
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mv SI_DESC ../descriptor.bin
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mv IFWI ../fitimage.bin
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Put all of these files in `board/google/chromebook_coral` so they can be found
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by the build.
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To build::
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make O=/tmp/b/chromebook_coral chromebook_coral_defconfig
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make O=/tmp/b/chromebook_coral -s -j30 all
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That should produce `/tmp/b/chrombook_coral/u-boot.rom` which you can use with
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a Dediprog em100::
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em100 -s -c w25q128fw -d /tmp/b/chromebook_coral/u-boot.rom -r
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or you can use flashrom to write it to the board. If you do that, make sure you
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have a way to restore the old ROM without booting the board. Otherwise you may
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brick it. Having said that, you may find these instructions useful if you want
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to unbrick your device:
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https://chromium.googlesource.com/chromiumos/platform/ec/+/cr50_stab/docs/case_closed_debugging.md
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You can buy Suzy-Q from Sparkfun:
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https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/main/docs/ccd.md#suzyq-suzyqable
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Note that it will hang at the SPL prompt for 21 seconds. When booting into
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Chrome OS it will always select developer mode, so will wipe anything you have
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on the device if you let it proceed. You have two seconds in U-Boot to stop the
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auto-boot prompt and several seconds at the 'developer wipe' screen to stop it
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wiping the disk.
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Here is the console output::
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U-Boot TPL 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700)
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Trying to boot from Mapped SPI
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U-Boot SPL 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700)
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Trying to boot from Mapped SPI
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U-Boot 2021.04-rc1-00128-g344eefcdfec-dirty (Feb 11 2021 - 20:13:08 -0700)
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CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz
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DRAM: 3.9 GiB
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MMC: sdmmc@1b,0: 1, emmc@1c,0: 2
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Video: 1024x768x32 @ b0000000
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Model: Google Coral
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Net: No ethernet found.
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SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
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Hit any key to stop autoboot: 0
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cmdline=console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=${uuid}/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=${uuid} add_efi_memmap boot=local noresume noswap i915.modeset=1 Kernel command line: "console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off "
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Setup located at 00090000:
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ACPI RSDP addr : 7991f000
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E820: 14 entries
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Addr Size Type
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d0000000 1000000 <NULL>
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0 a0000 RAM
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a0000 60000 Reserved
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7b000000 800000 Reserved
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7b800000 4800000 Reserved
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7ac00000 400000 Reserved
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100000 ff00000 RAM
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10000000 2151000 Reserved
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12151000 68aaf000 RAM
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100000000 80000000 RAM
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e0000000 10000000 Reserved
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7991bfd0 12e4030 Reserved
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d0000000 10000000 Reserved
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fed10000 8000 Reserved
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Setup sectors : 1e
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Root flags : 1
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Sys size : 63420
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RAM size : 0
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Video mode : ffff
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Root dev : 0
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Boot flag : 0
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Jump : 66eb
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Header : 53726448
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Kernel V2
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Version : 20d
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Real mode switch : 0
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Start sys : 1000
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Kernel version : 38cc
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@00003acc:
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Type of loader : 80
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U-Boot, version 0
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Load flags : 81
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: loaded-high can-use-heap
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Setup move size : 8000
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Code32 start : 100000
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Ramdisk image : 0
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Ramdisk size : 0
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Bootsect kludge : 0
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Heap end ptr : 8e00
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Ext loader ver : 0
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Ext loader type : 0
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Command line ptr : 99000
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console= loglevel=7 init=/sbin/init cros_secure oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw dm_verity.error_behavior=3 dm_verity.max_bios=-1 dm_verity.dev_wait=0 dm="1 vroot none rw 1,0 3788800 verity payload=ROOT_DEV hashtree=HASH_DEV hashstart=3788800 alg=sha1 root_hexdigest=55052b629d3ac889f25a9583ea12cdcd3ea15ff8 salt=a2d4d9e574069f4fed5e3961b99054b7a4905414b60a25d89974a7334021165c" noinitrd vt.global_cursor_default=0 kern_guid=35c775e7-3735-d745-93e5-d9e0238f7ed0 add_efi_memmap boot=local noresume noswap i915.modeset=1 tpm_tis.force=1 tpm_tis.interrupts=0 nmi_watchdog=panic,lapic disablevmx=off
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Initrd addr max : 7fffffff
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Kernel alignment : 200000
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Relocatable kernel : 1
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Min alignment : 15
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: 200000
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Xload flags : 3
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: 64-bit-entry can-load-above-4gb
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Cmdline size : 7ff
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Hardware subarch : 0
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HW subarch data : 0
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Payload offset : 26e
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Payload length : 612045
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Setup data : 0
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Pref address : 1000000
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Init size : 1383000
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Handover offset : 0
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Starting kernel ...
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Timer summary in microseconds (17 records):
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Mark Elapsed Stage
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0 0 reset
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155,279 155,279 TPL
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237,088 81,809 end phase
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237,533 445 SPL
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816,456 578,923 end phase
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817,357 901 board_init_f
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1,061,751 244,394 board_init_r
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1,402,435 340,684 id=64
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1,430,071 27,636 main_loop
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5,532,057 4,101,986 start_kernel
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Accumulated time:
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685 dm_r
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2,817 fast_spi
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33,095 dm_spl
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52,468 dm_f
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208,242 fsp-m
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242,221 fsp-s
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332,710 mmap_spi
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Boot flow - TPL
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Boot flow - TPL
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---------------
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---------------
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@ -181,7 +344,7 @@ Partial memory map
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ff000000 Bottom of ROM
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ff000000 Bottom of ROM
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fefc0000 Top of CAR region
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fefc0000 Top of CAR region
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fef96000 Stack for FSP-M
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fef96000 Stack for FSP-M
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fef40000 59000 FSP-M
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fef40000 59000 FSP-M (also VPL loads here)
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fef11000 SPL loaded here
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fef11000 SPL loaded here
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fef10000 CONFIG_BLOBLIST_ADDR
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fef10000 CONFIG_BLOBLIST_ADDR
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fef10000 Stack top in TPL, SPL and U-Boot before relocation
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fef10000 Stack top in TPL, SPL and U-Boot before relocation
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@ -195,35 +358,72 @@ Partial memory map
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1110000 CONFIG_SYS_TEXT_BASE
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1110000 CONFIG_SYS_TEXT_BASE
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Speeding up SPL for development
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-------------------------------
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The 21-second wait for memory training is annoying during development, since
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every new image incurs this cost when booting. There is no cache to fall back on
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since that area of the image is empty on start-up.
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You can add suitable cache contents to the image to fix this, for development
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purposes only, like this::
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# Read the image back after booting through SPL
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em100 -s -c w25q128fw -u image.bin
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# Extract the two cache regions
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binman extract -i image.bin extra *cache
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# Move them into the source directory
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mv *cache board/google/chromebook_coral
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Then add something like this to the devicetree::
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#if IS_ENABLED(CONFIG_HAVE_MRC) || IS_ENABLED(CONFIG_FSP_VERSION2)
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/* Provide initial contents of the MRC data for faster development */
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rw-mrc-cache {
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type = "blob";
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/* Mirror the offset in spi-flash@0 */
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offset = <0xff8e0000>;
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size = <0x10000>;
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filename = "board/google/chromebook_coral/rw-mrc-cache";
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};
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rw-var-mrc-cache {
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type = "blob";
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size = <0x1000>;
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filename = "board/google/chromebook_coral/rw-var-mrc-cache";
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};
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#endif
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This tells binman to put the cache contents in the same place as the
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`rw-mrc-cache` and `rw-var-mrc-cache` regions defined by the SPI-flash driver.
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Supported peripherals
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Supported peripherals
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---------------------
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---------------------
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- UART
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The following have U-Boot drivers:
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- SPI flash
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- Video
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- UART
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- MMC (dev 0) and micro-SD (dev 1)
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- SPI flash
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- Chrome OS EC
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- Video
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- Keyboard
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- MMC (dev 0) and micro-SD (dev 1)
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- USB
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- Chrome OS EC
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- Cr50 (security chip)
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- Keyboard
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- USB
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To do
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To do
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-----
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-----
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- Finish peripherals
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- Finish peripherals
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- left-side USB
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- USB-C
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- Cr50 (security chip: a basic driver is running but not included here)
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- Sound (Intel I2S support exists, but need da7219 driver)
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- Sound (Intel I2S support exists, but need da7219 driver)
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- Various minor features supported by LPC, etc.
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- Booting Chrome OS, e.g. with verified boot
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- Integrate with Chrome OS vboot
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- Improvements to booting from coreboot (i.e. as a coreboot target)
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- Use FSP-T binary instead of our own CAR implementation
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- Use FSP-T binary instead of our own CAR implementation
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- Use the official FSP package instead of the coreboot one
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- Use the official FSP package instead of the coreboot one
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- Enable all CPU cores
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- Suspend / resume
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- Suspend / resume
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- ACPI
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- Fix MMC which seems to try to read even though the card is empty
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- Fix USB3 crash "WARN halted endpoint, queueing URB anyway."
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Credits
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Credits
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