From dcf1c627cf436191919c5a3b153d1033245b54b7 Mon Sep 17 00:00:00 2001 From: Michael Ferolito Date: Mon, 27 Jan 2025 21:09:45 -0600 Subject: [PATCH 01/68] usb: gadget: g_dnl: Fix NULLPTR dereference when serial# is unset The current behaviour of this function will dereference a null pointer if the serial# environment variable is unset. This was discovered on a board where U-Boot did not have access to the first 256MB of ram, resulting in a board crash. In the event that U-Boot has full access to memory, it will still read from address 0, which is probably not optimal. This simple check is enough to fix it Signed-off-by: Michael Ferolito Cc: Marek Vasut Cc: Heiko Schocher Cc: Kyungmin Park Reviewed-by: Heiko Schocher Reviewed-by: Mattijs Korpershoek Reviewed-by: Marek Vasut Link: https://lore.kernel.org/r/20250128030945.1219589-1-michaelsunn101@gmail.com Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/g_dnl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 631969b3405..f2540eb6ded 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -207,7 +207,8 @@ void g_dnl_clear_detach(void) static int on_serialno(const char *name, const char *value, enum env_op op, int flags) { - g_dnl_set_serialnumber((char *)value); + if (value) + g_dnl_set_serialnumber((char *)value); return 0; } U_BOOT_ENV_CALLBACK(serialno, on_serialno); From aa817a2f1fb66067fc3c6dc7d9d1a84bbaa99df9 Mon Sep 17 00:00:00 2001 From: Sam Day Date: Thu, 23 Jan 2025 14:35:01 +0000 Subject: [PATCH 02/68] boot: android: handle boot images with missing DTB 607b07554e2 removed the check on the return status of the android_image_get_dtb_img_addr call from android_image_get_dtb_by_index, which results in null pointer accesses shortly after when trying to check the header of a nonexistent DTB. Fixes: 607b07554e2 ("android: boot: move to andr_image_data structure") Signed-off-by: Sam Day Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20250123-android-handle-no-dtb-v1-1-1cb7373247da@samcday.com Signed-off-by: Mattijs Korpershoek --- boot/image-android.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/boot/image-android.c b/boot/image-android.c index fa4e14ca469..1746b018900 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -696,7 +696,10 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, ulong dtb_addr; /* address of DTB blob with specified index */ u32 i; /* index iterator */ - android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr); + if (!android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, + &dtb_img_addr)) + return false; + /* Check if DTB area of boot image is in DTBO format */ if (android_dt_check_header(dtb_img_addr)) { return android_dt_get_fdt_by_index(dtb_img_addr, index, addr, From 4b6a3e860878de5198f5561a0d8c602a9c296f0a Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 2 Dec 2024 08:46:44 +0100 Subject: [PATCH 03/68] usb: gadget: f_mass_storage: Add schedule() in sleep_thread() In case "ums" command is used on platforms which don't implement g_dnl_board_usb_cable_connected() and USB cable is not connected, we stay inside sleep_thread() forever and watchdog is triggered. Add schedule() call to avoid this issue. Signed-off-by: Patrice Chotard Reviewed-by: Marek Vasut Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20241202074644.5380-1-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/f_mass_storage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index ffe1ae6eb73..d3fc4acb401 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -682,6 +682,7 @@ static int sleep_thread(struct fsg_common *common) k = 0; } + schedule(); dm_usb_gadget_handle_interrupts(udcdev); } common->thread_wakeup_needed = 0; From 3810cd52cbf42727ebe22cf2a7929045d5ab01fd Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:39 +0100 Subject: [PATCH 04/68] ARM: dts: sti: Add fixed clock for ehci and ohci nodes in stih410-b2260.dtsi On STi platforms, all clocks are enabled by BOOTROM, so CONFIG_CLK is not set as no clock driver for STI exists. As ehci-generic and ohci-generic drivers are used on platforms where CONFIG_CLK is set, clk_get_bulk() returns-ENOSYS in case of stih410-b2260. To avoid this error, add fixed clocks for ehci and ohci nodes for stih410-b2260 to fix the following errors: Bus usb@9a03c00: ohci_generic usb@9a03c00: Failed to get clocks (ret=-19) Port not available. Bus usb@9a03e00: ehci_generic usb@9a03e00: Failed to get clocks (ret=-19) Port not available. Bus usb@9a83c00: ohci_generic usb@9a83c00: Failed to get clocks (ret=-19) Port not available. Bus usb@9a83e00: ehci_generic usb@9a83e00: Failed to get clocks (ret=-19) Port not available. scanning bus dwc3@9900000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Patrick Delaunay Link: https://lore.kernel.org/r/20250130163547.512990-2-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- arch/arm/dts/stih410-b2260-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi index 3b080ac7a1b..e9d7ec92281 100644 --- a/arch/arm/dts/stih410-b2260-u-boot.dtsi +++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi @@ -14,20 +14,30 @@ }; }; + clk_usb: clk-usb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + ohci0: usb@9a03c00 { compatible = "generic-ohci"; + clocks = <&clk_usb>; }; ehci0: usb@9a03e00 { compatible = "generic-ehci"; + clocks = <&clk_usb>; }; ohci1: usb@9a83c00 { compatible = "generic-ohci"; + clocks = <&clk_usb>; }; ehci1: usb@9a83e00 { compatible = "generic-ehci"; + clocks = <&clk_usb>; }; }; }; From 0f688eb0d69e2f8f65532908d8575113b4bd3427 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:40 +0100 Subject: [PATCH 05/68] configs: stih410-b2260: Enable DM_REGULATOR flag Since commit 6aa8bde8786d ("usb: host: ehci-generic: Remove DM_REGULATOR flag") device_get_supply_regulator() returns -ENOSYS which is not handle by ehci_enable_vbus_supply() and thus, ehci_usb_probe() return an error. By enabling DM_REGULATOR flag, device_get_supply_regulator() return -ENOENT which is handle and ehci_usb_probe() return 0. This fixed the following issue: stih410-b2260 =>usb start starting USB... Bus dwc3@9900000: Register 2000240 NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb@9a03c00: USB OHCI 1.0 Bus usb@9a03e00: probe failed, error -38 Bus usb@9a83c00: USB OHCI 1.0 Bus usb@9a83e00: probe failed, error -38 scanning bus dwc3@9900000 for devices... 1 USB Device(s) found scanning bus usb@9a03c00 for devices... data abort pc : [<7df929b4>] lr : [<7df92918>] reloc pc : [<7d6409b4>] lr : [<7d640918>] sp : 7c73b848 ip : 9cf13c5c fp : 7c879d08 r10: 7c85d040 r9 : 7c74ded0 r8 : 09a03c00 r7 : 00000002 r6 : 7c85d080 r5 : 7c86a040 r4 : 00000000 r3 : 00000000 r2 : 00000000 r1 : 7c85d080 r0 : 7c85d040 Flags: nzCv IRQs off FIQs off Mode SVC_32 Code: 05853ae4 0affffe2 e59a2010 e59a300c (e5832010) Resetting CPU ... Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Patrick Delaunay Link: https://lore.kernel.org/r/20250130163547.512990-3-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 815f7557d69..e312ca492d2 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -48,6 +48,7 @@ CONFIG_MMC_SDHCI_STI=y CONFIG_PHY=y CONFIG_STI_USB_PHY=y CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y CONFIG_STI_RESET=y CONFIG_STI_ASC_SERIAL=y CONFIG_SYSRESET=y From 15cd35cb3f1a128f1f4da8a3e5b8d93316125330 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:41 +0100 Subject: [PATCH 06/68] usb: dwc3: Remove dwc3 glue driver support for STi STi will migrate to dwc3-generic driver, dwc3-sti-glue driver can be removed. Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20250130163547.512990-4-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- MAINTAINERS | 2 - board/st/stih410-b2260/board.c | 1 - drivers/usb/host/Kconfig | 9 -- drivers/usb/host/Makefile | 1 - drivers/usb/host/dwc3-sti-glue.c | 253 ------------------------------- include/dwc3-sti-glue.h | 41 ----- 6 files changed, 307 deletions(-) delete mode 100644 drivers/usb/host/dwc3-sti-glue.c delete mode 100644 include/dwc3-sti-glue.h diff --git a/MAINTAINERS b/MAINTAINERS index 10f7f1fd180..8834737ebf9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -671,8 +671,6 @@ F: drivers/reset/sti-reset.c F: drivers/serial/serial_sti_asc.c F: drivers/sysreset/sysreset_sti.c F: drivers/timer/arm_global_timer.c -F: drivers/usb/host/dwc3-sti-glue.c -F: include/dwc3-sti-glue.h F: include/dt-bindings/clock/stih407-clks.h F: include/dt-bindings/clock/stih410-clks.h F: include/dt-bindings/reset/stih407-resets.h diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index a912712c9dd..3a495eb5089 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index a656265890e..3dc79770eeb 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -110,15 +110,6 @@ config USB_XHCI_RCAR Choose this option to add support for USB 3.0 driver on Renesas R-Car Gen3 SoCs. -config USB_XHCI_STI - bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" - depends on ARCH_STI - default y - help - Enables support for the on-chip xHCI controller on STMicroelectronics - STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic - to configure the controller. - config USB_XHCI_DRA7XX_INDEX int "DRA7XX xHCI USB index" range 0 1 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 301bb9fdee1..902d68d0378 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,7 +54,6 @@ obj-$(CONFIG_USB_XHCI_GENERIC) += xhci-generic.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o -obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o # designware diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c deleted file mode 100644 index 3e6834e38e3..00000000000 --- a/drivers/usb/host/dwc3-sti-glue.c +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * STiH407 family DWC3 specific Glue layer - * - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure - * @syscfg_base: addr for the glue syscfg - * @glue_base: addr for the glue registers - * @syscfg_offset: usb syscfg control offset - * @powerdown_ctl: rest controller for powerdown signal - * @softreset_ctl: reset controller for softreset signal - * @mode: drd static host/device config - */ -struct sti_dwc3_glue_plat { - phys_addr_t syscfg_base; - phys_addr_t glue_base; - phys_addr_t syscfg_offset; - struct reset_ctl powerdown_ctl; - struct reset_ctl softreset_ctl; - enum usb_dr_mode mode; -}; - -static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat) -{ - unsigned long val; - - val = readl(plat->syscfg_base + plat->syscfg_offset); - - val &= USB3_CONTROL_MASK; - - switch (plat->mode) { - case USB_DR_MODE_PERIPHERAL: - val &= ~(USB3_DELAY_VBUSVALID - | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) - | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 - | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); - - val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; - break; - - case USB_DR_MODE_HOST: - val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID - | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) - | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 - | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); - - val |= USB3_DELAY_VBUSVALID; - break; - - default: - pr_err("Unsupported mode of operation %d\n", plat->mode); - return -EINVAL; - } - writel(val, plat->syscfg_base + plat->syscfg_offset); - - return 0; -} - -static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat) -{ - unsigned long reg; - - reg = readl(plat->glue_base + CLKRST_CTRL); - - reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; - reg &= ~SW_PIPEW_RESET_N; - - writel(reg, plat->glue_base + CLKRST_CTRL); - - /* configure mux for vbus, powerpresent and bvalid signals */ - reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1); - - reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | - SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | - SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); - - writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1); - - setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); -} - -static int sti_dwc3_glue_of_to_plat(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - struct udevice *syscon; - struct regmap *regmap; - int ret; - u32 reg[4]; - - ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg, - ARRAY_SIZE(reg)); - if (ret) { - pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret); - return ret; - } - - plat->glue_base = reg[0]; - plat->syscfg_offset = reg[2]; - - /* get corresponding syscon phandle */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg", - &syscon); - if (ret) { - pr_err("unable to find syscon device (%d)\n", ret); - return ret; - } - - /* get syscfg-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - pr_err("unable to find regmap\n"); - return -ENODEV; - } - plat->syscfg_base = regmap->ranges[0].start; - - /* get powerdown reset */ - ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl); - if (ret) { - pr_err("can't get powerdown reset for %s (%d)", dev->name, ret); - return ret; - } - - /* get softreset reset */ - ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl); - if (ret) - pr_err("can't get soft reset for %s (%d)", dev->name, ret); - - return ret; -}; - -static int sti_dwc3_glue_bind(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - ofnode node, dwc3_node; - - /* Find snps,dwc3 node from subnode */ - ofnode_for_each_subnode(node, dev_ofnode(dev)) { - if (ofnode_device_is_compatible(node, "snps,dwc3")) - dwc3_node = node; - } - - if (!ofnode_valid(dwc3_node)) { - pr_err("Can't find dwc3 subnode for %s\n", dev->name); - return -ENODEV; - } - - /* retrieve the DWC3 dual role mode */ - plat->mode = usb_get_dr_mode(dwc3_node); - if (plat->mode == USB_DR_MODE_UNKNOWN) - /* by default set dual role mode to HOST */ - plat->mode = USB_DR_MODE_HOST; - - return dm_scan_fdt_dev(dev); -} - -static int sti_dwc3_glue_probe(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - int ret; - - /* deassert both powerdown and softreset */ - ret = reset_deassert(&plat->powerdown_ctl); - if (ret < 0) { - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - return ret; - } - - ret = reset_deassert(&plat->softreset_ctl); - if (ret < 0) { - pr_err("DWC3 soft reset deassert failed: %d", ret); - goto softreset_err; - } - - ret = sti_dwc3_glue_drd_init(plat); - if (ret) - goto init_err; - - sti_dwc3_glue_init(plat); - - return 0; - -init_err: - ret = reset_assert(&plat->softreset_ctl); - if (ret < 0) { - pr_err("DWC3 soft reset deassert failed: %d", ret); - return ret; - } - -softreset_err: - ret = reset_assert(&plat->powerdown_ctl); - if (ret < 0) - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - - return ret; -} - -static int sti_dwc3_glue_remove(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - int ret; - - /* assert both powerdown and softreset */ - ret = reset_assert(&plat->powerdown_ctl); - if (ret < 0) { - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - return ret; - } - - ret = reset_assert(&plat->softreset_ctl); - if (ret < 0) - pr_err("DWC3 soft reset deassert failed: %d", ret); - - return ret; -} - -static const struct udevice_id sti_dwc3_glue_ids[] = { - { .compatible = "st,stih407-dwc3" }, - { } -}; - -U_BOOT_DRIVER(dwc3_sti_glue) = { - .name = "dwc3_sti_glue", - .id = UCLASS_NOP, - .of_match = sti_dwc3_glue_ids, - .of_to_plat = sti_dwc3_glue_of_to_plat, - .probe = sti_dwc3_glue_probe, - .remove = sti_dwc3_glue_remove, - .bind = sti_dwc3_glue_bind, - .plat_auto = sizeof(struct sti_dwc3_glue_plat), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h deleted file mode 100644 index 546ffbaf7b4..00000000000 --- a/include/dwc3-sti-glue.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. - */ - -#ifndef __DWC3_STI_UBOOT_H_ -#define __DWC3_STI_UBOOT_H_ - -/* glue registers */ -#include -#define CLKRST_CTRL 0x00 -#define AUX_CLK_EN BIT(0) -#define SW_PIPEW_RESET_N BIT(4) -#define EXT_CFG_RESET_N BIT(8) - -#define XHCI_REVISION BIT(12) - -#define USB2_VBUS_MNGMNT_SEL1 0x2C -#define USB2_VBUS_UTMIOTG 0x1 - -#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) -#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) -#define SEL_OVERRIDE_BVALID(n) ((n) << 8) - -/* Static DRD configuration */ -#define USB3_CONTROL_MASK 0xf77 - -#define USB3_DEVICE_NOT_HOST BIT(0) -#define USB3_FORCE_VBUSVALID BIT(1) -#define USB3_DELAY_VBUSVALID BIT(2) -#define USB3_SEL_FORCE_OPMODE BIT(4) -#define USB3_FORCE_OPMODE(n) ((n) << 5) -#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) -#define USB3_FORCE_DPPULLDOWN2 BIT(9) -#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) -#define USB3_FORCE_DMPULLDOWN2 BIT(11) - -int sti_dwc3_init(enum usb_dr_mode mode); - -#endif /* __DWC3_STI_UBOOT_H_ */ From 9de4b7e0a4c93128f28b19ad8a3a82421275418f Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:42 +0100 Subject: [PATCH 07/68] usb: dwc3-generic: Reorder include Reorder include following rules available here : https://docs.u-boot.org/en/latest/develop/codingstyle.html#include-files Remove useless include files. Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Mattijs Korpershoek Reviewed-by: Patrick Delaunay Link: https://lore.kernel.org/r/20250130163547.512990-5-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- drivers/usb/dwc3/dwc3-generic.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 55e62b35c61..21452ad1569 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -7,29 +7,17 @@ * Based on dwc3-omap.c. */ -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" -#include "gadget.h" #include -#include -#include #include - +#include +#include +#include +#include +#include +#include "core.h" #include "dwc3-generic.h" +#include "gadget.h" struct dwc3_generic_plat { fdt_addr_t base; From 23542078ec9a49cfb35cc00a6715106afbf65627 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:43 +0100 Subject: [PATCH 08/68] usb: dwc3-generic: Add STih407 support Add STi glue logic to manage the DWC3 HC on STiH407 SoC family. It configures the internal glue logic and syscfg registers. Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20250130163547.512990-6-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- MAINTAINERS | 1 + drivers/usb/dwc3/Kconfig | 8 ++ drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-generic-sti.c | 134 ++++++++++++++++++++++++++++ 4 files changed, 144 insertions(+) create mode 100644 drivers/usb/dwc3/dwc3-generic-sti.c diff --git a/MAINTAINERS b/MAINTAINERS index 8834737ebf9..c1851280e6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -671,6 +671,7 @@ F: drivers/reset/sti-reset.c F: drivers/serial/serial_sti_asc.c F: drivers/sysreset/sysreset_sti.c F: drivers/timer/arm_global_timer.c +F: drivers/usb/host/dwc3-sti.c F: include/dt-bindings/clock/stih407-clks.h F: include/dt-bindings/clock/stih410-clks.h F: include/dt-bindings/reset/stih407-resets.h diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 0100723a68b..682a6910655 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -87,6 +87,14 @@ config USB_DWC3_LAYERSCAPE Host and Peripheral operation modes are supported. OTG is not supported. +config USB_DWC3_STI + bool "STi USB wrapper" + depends on DM_USB && USB_DWC3_GENERIC && SYSCON + help + Enables support for the on-chip xHCI controller on STMicroelectronics + STiH407 family SoCs. This is a driver for the dwc3 to provide the + glue logic to configure the controller. + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index a085c9d4628..985206eafe4 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o +obj-$(CONFIG_USB_DWC3_STI) += dwc3-generic-sti.o diff --git a/drivers/usb/dwc3/dwc3-generic-sti.c b/drivers/usb/dwc3/dwc3-generic-sti.c new file mode 100644 index 00000000000..b34f5ceceac --- /dev/null +++ b/drivers/usb/dwc3/dwc3-generic-sti.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * STi specific glue layer for DWC3 + * + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include +#include +#include +#include +#include +#include +#include +#include +#include "dwc3-generic.h" + +/* glue registers */ +#define CLKRST_CTRL 0x00 +#define AUX_CLK_EN BIT(0) +#define SW_PIPEW_RESET_N BIT(4) +#define EXT_CFG_RESET_N BIT(8) + +#define XHCI_REVISION BIT(12) + +#define USB2_VBUS_MNGMNT_SEL1 0x2C +#define USB2_VBUS_UTMIOTG 0x1 + +#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) +#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) +#define SEL_OVERRIDE_BVALID(n) ((n) << 8) + +/* Static DRD configuration */ +#define USB3_CONTROL_MASK 0xf77 + +#define USB3_DEVICE_NOT_HOST BIT(0) +#define USB3_FORCE_VBUSVALID BIT(1) +#define USB3_DELAY_VBUSVALID BIT(2) +#define USB3_SEL_FORCE_OPMODE BIT(4) +#define USB3_FORCE_OPMODE(n) ((n) << 5) +#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) +#define USB3_FORCE_DPPULLDOWN2 BIT(9) +#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) +#define USB3_FORCE_DMPULLDOWN2 BIT(11) + +static void dwc3_stih407_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ + struct dwc3_glue_data *glue = dev_get_plat(dev); + struct regmap *regmap; + ulong syscfg_base; + ulong syscfg_offset; + ulong glue_base; + int ret; + + /* deassert both powerdown and softreset */ + ret = reset_deassert_bulk(&glue->resets); + if (ret) { + dev_err(dev, "reset_deassert_bulk error: %d\n", ret); + return; + } + + regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg"); + if (IS_ERR(regmap)) { + dev_err(dev, "unable to get st,syscfg, dev %s\n", dev->name); + return; + } + + syscfg_base = regmap->ranges[0].start; + glue_base = dev_read_addr_index(dev, 0); + syscfg_offset = dev_read_addr_index(dev, 1); + + clrbits_le32(syscfg_base + syscfg_offset, USB3_CONTROL_MASK); + + /* glue drd init */ + switch (mode) { + case USB_DR_MODE_PERIPHERAL: + clrbits_le32(syscfg_base + syscfg_offset, + USB3_DELAY_VBUSVALID | USB3_SEL_FORCE_OPMODE | + USB3_FORCE_OPMODE(0x3) | USB3_SEL_FORCE_DPPULLDOWN2 | + USB3_FORCE_DPPULLDOWN2 | USB3_SEL_FORCE_DMPULLDOWN2 | + USB3_FORCE_DMPULLDOWN2); + + setbits_le32(syscfg_base + syscfg_offset, + USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID); + break; + + case USB_DR_MODE_HOST: + clrbits_le32(syscfg_base + syscfg_offset, + USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID | + USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | + USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | + USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); + + setbits_le32(syscfg_base + syscfg_offset, USB3_DELAY_VBUSVALID); + break; + + default: + dev_err(dev, "Unsupported mode of operation %d\n", mode); + return; + } + + /* glue init */ + setbits_le32(glue_base + CLKRST_CTRL, AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION); + clrbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); + + /* configure mux for vbus, powerpresent and bvalid signals */ + setbits_le32(glue_base + USB2_VBUS_MNGMNT_SEL1, + SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | + SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | + SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG)); + setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); +}; + +struct dwc3_glue_ops stih407_ops = { + .glue_configure = dwc3_stih407_glue_configure, +}; + +static const struct udevice_id dwc3_sti_match[] = { + { .compatible = "st,stih407-dwc3", .data = (ulong)&stih407_ops}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwc3_sti_wrapper) = { + .name = "dwc3-sti", + .id = UCLASS_NOP, + .of_match = dwc3_sti_match, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .plat_auto = sizeof(struct dwc3_glue_data), +}; From 08fec26a67643fac05e2a076d19c54bca6f6e427 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:44 +0100 Subject: [PATCH 09/68] configs: stih410-b2260: Enable USB_DWC3_GENERIC and USB_DWC3_STI flags Enable USB_DWC3_GENERIC and USB_DWC3_STI flags. Signed-off-by: Patrice Chotard Cc: Marek Vasut Link: https://lore.kernel.org/r/20250130163547.512990-7-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- configs/stih410-b2260_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index e312ca492d2..4fcbf75548b 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -61,6 +61,8 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_DWC3_STI=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y From d0ff527f6237a78fb289b02e5dab63a23478565b Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:45 +0100 Subject: [PATCH 10/68] configs: stih410-b2260: Enable DM_USB_GADGET flag Enable DM_USB_GADGET flag. Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Patrick Delaunay Link: https://lore.kernel.org/r/20250130163547.512990-8-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 4fcbf75548b..5641fd1d8d7 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -54,6 +54,7 @@ CONFIG_STI_ASC_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y From 0b96214cb32ebc54e92442a96eb9dc1e1f7e9175 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:46 +0100 Subject: [PATCH 11/68] board: stih410-b2260: Remove board_usb_init/cleanup() Since DM_USB_GADGET is enable for this board, board_usb_init() and board_usb_cleanup() can be removed. Signed-off-by: Patrice Chotard Reviewed-by: Mattijs Korpershoek Reviewed-by: Patrick Delaunay Link: https://lore.kernel.org/r/20250130163547.512990-9-patrice.chotard@foss.st.com Signed-off-by: Mattijs Korpershoek --- board/st/stih410-b2260/board.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index 3a495eb5089..8ad593cccdd 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -7,10 +7,6 @@ #include #include #include -#include -#include -#include -#include DECLARE_GLOBAL_DATA_PTR; @@ -42,31 +38,6 @@ int board_init(void) } #ifdef CONFIG_USB_DWC3 -static struct dwc3_device dwc3_device_data = { - .maximum_speed = USB_SPEED_HIGH, - .dr_mode = USB_DR_MODE_PERIPHERAL, - .index = 0, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const void *blob = gd->fdt_blob; - - /* find the snps,dwc3 node */ - node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); - - dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg"); - - return dwc3_uboot_init(&dwc3_device_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - dwc3_uboot_exit(index); - return 0; -} - int g_dnl_board_usb_cable_connected(void) { return 1; From 4096d28ec80f982454ef0dc7d42a4d4eaead5d56 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 30 Jan 2025 17:35:47 +0100 Subject: [PATCH 12/68] configs: stih410-b2260: Enable CMD_USB_MASS_STORAGE flag Enable CMD_USB_MASS_STORAGE flag. Signed-off-by: Patrice Chotard Cc: Marek Vasut Reviewed-by: Patrick Delaunay Link: https://lore.kernel.org/r/20250130163547.512990-10-patrice.chotard@foss.st.com [mkorpershoek: fixed up commit footer] Signed-off-by: Mattijs Korpershoek --- configs/stih410-b2260_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 5641fd1d8d7..1e5190dc828 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y From 3da1864b1f2fc3cf2b4eaa1849bcafa669ff674c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 11 Feb 2025 09:11:21 -0600 Subject: [PATCH 13/68] configs: Resync with savedefconfig Resync all defconfig files using qconfig.py Signed-off-by: Tom Rini --- configs/am62ax_evm_r5_defconfig | 1 - configs/am62px_evm_r5_defconfig | 1 - configs/arbel_evb_defconfig | 1 - configs/bitmain_antminer_s9_defconfig | 2 +- configs/ibex-ast2700_defconfig | 1 - configs/mt7987_rfb_defconfig | 1 - configs/qemu_arm64_defconfig | 2 +- configs/syzygy_hub_defconfig | 2 +- configs/xilinx_zynq_virt_defconfig | 2 +- configs/xilinx_zynqmp_kria_defconfig | 2 +- configs/xilinx_zynqmp_virt_defconfig | 2 +- 11 files changed, 6 insertions(+), 11 deletions(-) diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 58cad17b5d5..3953430c014 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -83,7 +83,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_SPL_MISC=y CONFIG_ESM_K3=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 54ea4bfb620..f39356351f4 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -88,7 +88,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_SPL_MISC=y CONFIG_ESM_K3=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 2b0b8b2d3b7..67627f5d26d 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -81,7 +81,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_GIGE=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index afff2d54f2c..edb49de207c 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -44,10 +44,10 @@ CONFIG_SYS_PROMPT="antminer> " CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index e4b9a9a5abb..6cb2a21ed2d 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -27,7 +27,6 @@ CONFIG_TARGET_ASPEED_AST2700_IBEX=y # CONFIG_SPL_SMP is not set CONFIG_XIP=y CONFIG_SPL_XIP=y -# CONFIG_AVAILABLE_HARTS is not set CONFIG_STACK_SIZE_SHIFT=11 CONFIG_ENV_VARS_UBOOT_CONFIG=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig index 00e3cea5264..c6a88e7e9d3 100644 --- a/configs/mt7987_rfb_defconfig +++ b/configs/mt7987_rfb_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_LOAD_ADDR=0x48000000 CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_DEBUG_UART=y -# CONFIG_EFI_LOADER is not set CONFIG_FIT=y # CONFIG_AUTOBOOT is not set CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb" diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 763fc14468a..03028c76acc 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -74,5 +74,5 @@ CONFIG_USB_EHCI_PCI=y CONFIG_SEMIHOSTING=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y -CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y CONFIG_TPM_PCR_ALLOCATE=y +CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index e7e15c64ba2..27ff3915050 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -36,10 +36,10 @@ CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000 CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index fdf8bb36129..9196a95e88a 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -61,10 +61,10 @@ CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index ad46c091c4a..1a6bd67afb8 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -70,8 +70,8 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 036268c79f7..e5e56babf4c 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -68,8 +68,8 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y From c125ef543c128a3351a564ce584e15e646cdb1df Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 9 Dec 2024 12:45:18 +0200 Subject: [PATCH 14/68] Revert "drivers: gpio-uclass: support PMIC GPIO children" Requesting of PMIC's GPIO child should be done by binding GPIO driver to PMIC's node is GPIO driver does not have its own node. This reverts commit c03cd98d1a163666b4addcdd9a34fc0c77dfd0a5. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Jaehoon Chung --- drivers/gpio/gpio-uclass.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index da929c33447..3d9f8b32b8d 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1145,29 +1145,9 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { -#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO) - struct udevice *pmic; - ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node, - &pmic); - if (ret) { - log_debug("%s: PMIC device get failed, err %d\n", - __func__, ret); - goto err; - } - - device_foreach_child(desc->dev, pmic) { - if (device_get_uclass_id(desc->dev) == UCLASS_GPIO) - break; - } - - /* if loop exits without GPIO device return error */ - if (device_get_uclass_id(desc->dev) != UCLASS_GPIO) - goto err; -#else debug("%s: uclass_get_device_by_ofnode failed\n", __func__); goto err; -#endif } } ret = gpio_find_and_xlate(desc, args); From 1ca8ec80f29a5a45dcb702a1164f9b42a077914f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 9 Dec 2024 12:51:33 +0200 Subject: [PATCH 15/68] pmic: max77663: bind children to parent node Bind GPIO and SYSRESET children to parent node since they do not have their own nodes in the device tree. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Jaehoon Chung --- drivers/power/pmic/max77663.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index cf08b6a7e1d..c2a7cbf7e40 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -47,8 +47,9 @@ static int max77663_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { - ret = device_bind_driver(dev, MAX77663_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; @@ -56,8 +57,8 @@ static int max77663_bind(struct udevice *dev) } if (IS_ENABLED(CONFIG_MAX77663_GPIO)) { - ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER, - "gpio", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_GPIO_DRIVER, + "gpio", dev_ofnode(dev), NULL); if (ret) { log_err("cannot bind GPIOs (ret = %d)\n", ret); return ret; From aab837d7fc776ef956d07f97ad15cb4256a146af Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 9 Dec 2024 12:58:19 +0200 Subject: [PATCH 16/68] pmic: palmas: bind sysreset to parent node Bind SYSRESET child to parent node since it does not have its own node in the device tree. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Jaehoon Chung --- drivers/power/pmic/palmas.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index f676bf64169..37d4190fabe 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -49,8 +49,9 @@ static int palmas_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { - ret = device_bind_driver(dev, PALMAS_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; From efb7964cc1613bed0550510116f11fe757c025f8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 6 Dec 2024 17:50:58 +0200 Subject: [PATCH 17/68] pinctrl: tegra20: adjust pin type detection Pin detection on t20 depends on node name. With recent changes in node naming, let's remove '_' to be safe about both '_' or '-' use. Signed-off-by: Svyatoslav Ryhel --- drivers/pinctrl/tegra/pinctrl-tegra20.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index d5171b8be23..d59b3ec7b5d 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -97,9 +97,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config) * then actual pins setup (with node name prefix * conf_*) and then drive setup. */ - if (!strncmp(child->name, "conf_", 5)) + if (!strncmp(child->name, "conf", 4)) tegra_pinctrl_set_pin(child); - else if (!strncmp(child->name, "drive_", 6)) + else if (!strncmp(child->name, "drive", 5)) debug("%s: drive configuration is not supported\n", __func__); else tegra_pinctrl_set_func(child); From b93e25dc73acdc07c16074923aeeb305db21157a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 29 Nov 2024 19:30:54 +0200 Subject: [PATCH 18/68] board: asus: convert SPL to XPL Not sure why these files were omitted, but SPL should be converted to XPL. Signed-off-by: Svyatoslav Ryhel --- board/asus/grouper/Makefile | 2 +- board/asus/transformer-t30/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile index 8a8e6530c86..b83b7fced48 100644 --- a/board/asus/grouper/Makefile +++ b/board/asus/grouper/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel -obj-$(CONFIG_SPL_BUILD) += grouper-spl.o +obj-$(CONFIG_XPL_BUILD) += grouper-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += grouper.o diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile index 22b6160f757..b8617f820cd 100644 --- a/board/asus/transformer-t30/Makefile +++ b/board/asus/transformer-t30/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel -obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o +obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += transformer-t30.o From e4f5741c6dc3ba5d867336244c53eb092b273f60 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 15 Nov 2024 21:13:15 +0200 Subject: [PATCH 19/68] ARM: tegra124: clock: implement PLLD2 support PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra124/clock-tables.h | 2 +- arch/arm/mach-tegra/tegra124/clock.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index 9f531253153..055948ec07a 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* Special for Tegra124 */ /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL2, CLOCK_ID_CGENERAL3, CLOCK_ID_MEMORY2, diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 4ac0c10c597..0ea212f80e2 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -598,6 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -852,6 +854,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA124_CLK_PLL_D: case TEGRA124_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA124_CLK_PLL_D2: + case TEGRA124_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA124_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA124_CLK_PLL_E: @@ -1194,6 +1199,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; case CLOCK_ID_DP: return &clkrst->plldp; default: From c3d8c206dc62a79eda44b1492decfbace151d17e Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 29 Nov 2024 08:14:21 +0200 Subject: [PATCH 20/68] ARM: tegra210: clock: implement PLLD2 support PLLD2 is a simple clock (controlled by 2 registers) and appears starting from T30. Primary use of PLLD2 is as main HDMI clock parent. Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra210/clock-tables.h | 2 +- arch/arm/mach-tegra/tegra210/clock.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index c6d7487e629..5c4d7fc84c4 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL_0, CLOCK_ID_CGENERAL_1, CLOCK_ID_CGENERAL2, diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 57ff0b2a19a..04708f97144 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -668,6 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -939,6 +941,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA210_CLK_PLL_D: case TEGRA210_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA210_CLK_PLL_D2: + case TEGRA210_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA210_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA210_CLK_PLL_E: @@ -1276,6 +1281,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; default: return NULL; } From f47a02825aa967cf1f62248d50c012a3821d7ebc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 24 Nov 2024 14:27:17 +0200 Subject: [PATCH 21/68] ARM: tegra30: dts: complete DSI nodes Sync DSI nodes with Linux tree. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra30.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 1177e2ab1f4..d5de1ecaf05 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -218,10 +218,29 @@ dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; From dedc0468b2eec4d4b8918742eda7203fb1871178 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 18 Nov 2024 08:32:13 +0200 Subject: [PATCH 22/68] ARM: tegra124: dts: add missing DSI nodes Bind missing DSI and MIPI calibration devices. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra124.dtsi | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index ffec9cae09d..cac9b112302 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -136,6 +136,38 @@ status = "disabled"; }; + dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x54540000 0x00040000>; @@ -737,6 +769,13 @@ #thermal-sensor-cells = <1>; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0x70110000 0x100>, /* DFLL control */ From 9f6b9f57fefa391018083c42bc3de9f33ea3bd90 Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Thu, 30 Jan 2025 09:22:20 +0100 Subject: [PATCH 23/68] net: lwip: move eth_init() out of new_netif() Move the initialization of the ethernet devices out of the new_netif() function. Indeed, new_netif() accepts a struct device argument, which is expected to be valid and active. The activation and selection of this device are achieved by eth_init() (on first time the network stack is used) and eth_set_current(). This is what takes care of the ethrotate and ethact environment variables. Therefore, move these calls to a new function: net_lwip_set_current(), and use it whenever a net-lwip command is run. This patch hopefully fixes the incorrect net-lwip behavior observed on boards with multiple ethernet interfaces [1]. Tested on an i.MX8MPlus EVK equipped wih two ethernet ports. The dhcp command succeeds whether the cable is plugged into the first or second port. [1] https://lists.denx.de/pipermail/u-boot/2025-January/576326.html Reported-by: E Shattow Tested-by: E Shattow Signed-off-by: Jerome Forissier --- include/net-lwip.h | 1 + net/lwip/dhcp.c | 2 +- net/lwip/dns.c | 2 +- net/lwip/net-lwip.c | 23 ++++++++++++++--------- net/lwip/ping.c | 2 +- net/lwip/tftp.c | 2 +- net/lwip/wget.c | 2 +- 7 files changed, 20 insertions(+), 14 deletions(-) diff --git a/include/net-lwip.h b/include/net-lwip.h index 4d7f9387d1d..64e5c720560 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -10,6 +10,7 @@ enum proto_t { TFTPGET }; +void net_lwip_set_current(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index e7d9147455c..3b7e4700c6e 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -115,7 +115,7 @@ int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int ret; struct udevice *dev; - eth_set_current(); + net_lwip_set_current(); dev = eth_get_dev(); if (!dev) { diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 1de63c9998b..149bdb784dc 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -121,7 +121,7 @@ int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc == 3) var = argv[2]; - eth_set_current(); + net_lwip_set_current(); return dns_loop(eth_get_dev(), name, var); } diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index b863047f598..cab1dd7d483 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -127,6 +127,20 @@ static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip, return 0; } +/* Initialize the lwIP stack and the ethernet devices and set current device */ +void net_lwip_set_current(void) +{ + static bool init_done; + + if (!init_done) { + eth_init_rings(); + eth_init(); + lwip_init(); + init_done = true; + } + eth_set_current(); +} + static struct netif *new_netif(struct udevice *udev, bool with_ip) { unsigned char enetaddr[ARP_HLEN]; @@ -134,19 +148,10 @@ static struct netif *new_netif(struct udevice *udev, bool with_ip) ip4_addr_t ip, mask, gw; struct netif *netif; int ret = 0; - static bool first_call = true; if (!udev) return NULL; - if (first_call) { - eth_init_rings(); - /* Pick a valid active device, if any */ - eth_init(); - lwip_init(); - first_call = false; - } - if (eth_start_udev(udev) < 0) { log_err("Could not start %s\n", udev->name); return NULL; diff --git a/net/lwip/ping.c b/net/lwip/ping.c index aa617530749..200a702bbb5 100644 --- a/net/lwip/ping.c +++ b/net/lwip/ping.c @@ -168,7 +168,7 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (!ipaddr_aton(argv[1], &addr)) return CMD_RET_USAGE; - eth_set_current(); + net_lwip_set_current(); if (ping_loop(eth_get_dev(), &addr) < 0) return CMD_RET_FAILURE; diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c index fc4aff5f2ba..123d66b5dba 100644 --- a/net/lwip/tftp.c +++ b/net/lwip/tftp.c @@ -280,7 +280,7 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) goto out; } - eth_set_current(); + net_lwip_set_current(); if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0) ret = CMD_RET_FAILURE; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index b76f6c0f1d9..9aec75f9bed 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -354,7 +354,7 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) int wget_do_request(ulong dst_addr, char *uri) { - eth_set_current(); + net_lwip_set_current(); if (!wget_info) wget_info = &default_wget_info; From 10917df17f247d3b0a7f5ca992b97bd2728ef09e Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 3 Feb 2025 10:11:59 +0100 Subject: [PATCH 24/68] net: lwip: tftp: fix find_option() Find_option() is used to retrieve the block size value in an option acknowledgment in response to a request containing a block size option according to RFC2348. The format of an OACK response is described in RFC2347 as +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ | opc | opt1 | 0 | value1 | 0 | optN | 0 | valueN | 0 | +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ The current implementation of find_option() only works if * blksize is the first option * lwip_strnstr() ignores the length parameter, i.e. is implemented via strstr() The OACK messages starts with 0x00 0x06. If 'blksize' is the first option, strstr() reports a match when the first parameter points to 0x06. Adding the string length of 'blksize' plus 2 to the location of the 0x06 byte points to the value. Find_option() would report a match for option 'blksize' if the response contained an option called 'foo_blksize_bar'. In this case find_option() would return 'bar' as the value string. If 'blksize' were the second option, find_option() would return a pointer to the second character of the value string. Furthermore find_option() does not detect if the value string is NUL terminated. This may lead to a buffer overrun. Provide an implementation that correctly steps from option to option. Fixes: 27d7ccda94fa ("net: lwip: tftp: add support of blksize option to client") Signed-off-by: Heinrich Schuchardt Reviewed-by: Jerome Forissier Tested-by: Jerome Forissier (qemu_arm64_lwip) Signed-off-by: Jerome Forissier --- lib/lwip/lwip/src/apps/tftp/tftp.c | 52 +++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 8 deletions(-) diff --git a/lib/lwip/lwip/src/apps/tftp/tftp.c b/lib/lwip/lwip/src/apps/tftp/tftp.c index 56aeabc4d73..63b1e0e0e20 100644 --- a/lib/lwip/lwip/src/apps/tftp/tftp.c +++ b/lib/lwip/lwip/src/apps/tftp/tftp.c @@ -264,19 +264,55 @@ static u16_t payload_size(void) return TFTP_DEFAULT_BLOCK_SIZE; } +/** + * find_option() - check if OACK message contains option + * + * @p: message buffer + * @option: option key + * Return: option value + */ static const char * find_option(struct pbuf *p, const char *option) { - int i; - u16_t optlen = strlen(option); - const char *b = p->payload; + const char *pos = p->payload; + int rem = p->len; - for (i = 0; i + optlen + 1 < p->len; i++) { - if (lwip_strnstr(b + i, option, optlen)) - return b + i + optlen + 2; - } + /* + * According to RFC 2347 the OACK packet has the following format: + * + * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ + * | opc | opt1 | 0 | value1 | 0 | optN | 0 | valueN | 0 | + * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ + */ - return NULL; + /* Skip opc */ + pos += 2; + rem -= 2; + if (rem <= 0) + return NULL; + + for (;;) { + int len; + int diff; + + len = strnlen(pos, rem) + 1; + if (rem < len) + break; + diff = strcmp(pos, option); + /* Skip option */ + pos += len; + rem -= len; + len = strnlen(pos, rem) + 1; + if (rem < len) + break; + if (!diff) + return pos; + /* Skip value */ + pos += len; + rem -= len; + } + + return NULL; } static void From 7c7361b98d6eadcbcde556763b6d40a686f4bd3d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 3 Feb 2025 10:12:00 +0100 Subject: [PATCH 25/68] lib: implement strnstr() Implement library function strnstr(). Implement strstr() using strnstr(). Sort the includes. Signed-off-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas [jf: replace by , folded from next patch] Signed-off-by: Jerome Forissier --- include/linux/string.h | 3 ++ lib/string.c | 65 +++++++++++++++++++++++++++--------------- 2 files changed, 45 insertions(+), 23 deletions(-) diff --git a/include/linux/string.h b/include/linux/string.h index 27b2beb9ddb..d943fcce690 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -72,6 +72,9 @@ extern char * strrchr(const char *,int); #ifndef __HAVE_ARCH_STRSTR extern char * strstr(const char *,const char *); #endif +#ifndef __HAVE_ARCH_STRNSTR +extern char *strnstr(const char *, const char *, size_t); +#endif #ifndef __HAVE_ARCH_STRLEN extern __kernel_size_t strlen(const char *); #endif diff --git a/lib/string.c b/lib/string.c index 0e0900de8bf..d56f88d4a84 100644 --- a/lib/string.c +++ b/lib/string.c @@ -15,13 +15,14 @@ * reentrant and should be faster). Use only strsep() in new code, please. */ -#include -#include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include +#include +#include /** * strncasecmp - Case insensitive, length-limited string comparison @@ -679,27 +680,45 @@ char *memdup(const void *src, size_t len) return p; } +#ifndef __HAVE_ARCH_STRNSTR +/** + * strnstr() - find the first substring occurrence in a NUL terminated string + * + * @s1: string to be searched + * @s2: string to search for + * @len: maximum number of characters in s2 to consider + * + * Return: pointer to the first occurrence or NULL + */ +char *strnstr(const char *s1, const char *s2, size_t len) +{ + size_t l1, l2; + + l1 = strnlen(s1, len); + l2 = strlen(s2); + + for (; l1 >= l2; --l1, ++s1) { + if (!memcmp(s1, s2, l2)) + return (char *) s1; + } + + return NULL; +} +#endif + #ifndef __HAVE_ARCH_STRSTR /** - * strstr - Find the first substring in a %NUL terminated string - * @s1: The string to be searched - * @s2: The string to search for + * strstr() - find the first substring occurrence in a NUL terminated string + * + * @s1: string to be searched + * @s2: string to search for + * @len: maximum number of characters in s2 to consider + * + * Return: pointer to the first occurrence or NULL */ -char * strstr(const char * s1,const char * s2) +char *strstr(const char *s1, const char *s2) { - int l1, l2; - - l2 = strlen(s2); - if (!l2) - return (char *) s1; - l1 = strlen(s1); - while (l1 >= l2) { - l1--; - if (!memcmp(s1,s2,l2)) - return (char *) s1; - s1++; - } - return NULL; + return strnstr(s1, s2, SIZE_MAX); } #endif From 4fee75276d3b140bf534f045327901656067bf80 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 3 Feb 2025 10:12:01 +0100 Subject: [PATCH 26/68] test: unit tests for strstr() and strnstr() Add unit tests for the library functions. Signed-off-by: Heinrich Schuchardt Acked-by: Ilias Apalodimas [jf: drop unwanted change to lib/string.c] Signed-off-by: Jerome Forissier --- test/lib/string.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/test/lib/string.c b/test/lib/string.c index 8d22f3fd68f..31391a387b9 100644 --- a/test/lib/string.c +++ b/test/lib/string.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -221,3 +222,42 @@ static int lib_memdup(struct unit_test_state *uts) return 0; } LIB_TEST(lib_memdup, 0); + +/** lib_strnstr() - unit test for strnstr() */ +static int lib_strnstr(struct unit_test_state *uts) +{ + const char *s1 = "Itsy Bitsy Teenie Weenie"; + const char *s2 = "eenie"; + const char *s3 = "eery"; + + ut_asserteq_ptr(&s1[12], strnstr(s1, s2, SIZE_MAX)); + ut_asserteq_ptr(&s1[12], strnstr(s1, s2, 17)); + ut_assertnull(strnstr(s1, s2, 16)); + ut_assertnull(strnstr(s1, s2, 0)); + ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], SIZE_MAX)); + ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], 14)); + ut_assertnull(strnstr(&s1[3], &s2[1], 13)); + ut_assertnull(strnstr(&s1[3], &s2[1], 0)); + ut_assertnull(strnstr(s1, s3, SIZE_MAX)); + ut_assertnull(strnstr(s1, s3, 0)); + + return 0; +} +LIB_TEST(lib_strnstr, 0); + +/** lib_strstr() - unit test for strstr() */ +static int lib_strstr(struct unit_test_state *uts) +{ + const char *s1 = "Itsy Bitsy Teenie Weenie"; + const char *s2 = "eenie"; + const char *s3 = "easy"; + + ut_asserteq_ptr(&s1[12], strstr(s1, s2)); + ut_asserteq_ptr(&s1[13], strstr(&s1[3], &s2[1])); + ut_assertnull(strstr(s1, s3)); + ut_asserteq_ptr(&s1[2], strstr(s1, &s3[2])); + ut_asserteq_ptr(&s1[8], strstr(&s1[5], &s3[2])); + + return 0; +} +LIB_TEST(lib_strstr, 0); From 331d75544fc843f93275eb3767753e4a0a712a39 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 3 Feb 2025 10:12:02 +0100 Subject: [PATCH 27/68] net: use strnstr() for lwip_strnstr() Using strstr() instead of strnstr() creates a security concern. Fixes: 1c41a7afaa15 ("net: lwip: build lwIP") Signed-off-by: Heinrich Schuchardt Reviewed-by: Jerome Forissier Reviewed-by: Ilias Apalodimas Signed-off-by: Jerome Forissier --- lib/lwip/u-boot/arch/cc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h index de138846358..6104c296f6f 100644 --- a/lib/lwip/u-boot/arch/cc.h +++ b/lib/lwip/u-boot/arch/cc.h @@ -34,7 +34,7 @@ x, __LINE__, __FILE__); } while (0) #define atoi(str) (int)dectoul(str, NULL) -#define lwip_strnstr(a, b, c) strstr(a, b) +#define lwip_strnstr(a, b, c) strnstr(a, b, c) #define LWIP_ERR_T int #define LWIP_CONST_CAST(target_type, val) ((target_type)((uintptr_t)val)) From a091d173e32b98fe372b5b02d4e25c81f1bc9dc1 Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Tue, 4 Feb 2025 17:00:49 +0100 Subject: [PATCH 28/68] net: Kconfig: depend on DM_RNG for WGET_HTTPS net/lwip/wget.c/mbedtls_hardware_poll() is calling dm_rng_read() but dependency is not recorded anywhere that's why depend on DM_RNG when WGET_HTTPS is used. Suggested-by: Michal Simek Co-developed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas Signed-off-by: Jerome Forissier Tested-by: Michal Simek --- cmd/Kconfig | 1 + net/lwip/wget.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 1f9b26928c4..a04fcaa0e08 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2161,6 +2161,7 @@ config WGET_HTTPS depends on CMD_WGET depends on PROT_TCP_LWIP depends on MBEDTLS_LIB + depends on DM_RNG select SHA256 select RSA select ASYMMETRIC_KEY_TYPE diff --git a/net/lwip/wget.c b/net/lwip/wget.c index 9aec75f9bed..14f27d42998 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -433,10 +433,15 @@ bool wget_validate_uri(char *uri) if (!strncmp(uri, "http://", strlen("http://"))) { prefix_len = strlen("http://"); - } else if (!strncmp(uri, "https://", strlen("https://"))) { - prefix_len = strlen("https://"); + } else if (CONFIG_IS_ENABLED(WGET_HTTPS)) { + if (!strncmp(uri, "https://", strlen("https://"))) { + prefix_len = strlen("https://"); + } else { + log_err("only http(s):// is supported\n"); + return false; + } } else { - log_err("only http(s):// is supported\n"); + log_err("only http:// is supported\n"); return false; } From 279289e0cfb67265190ab85420264ad78bba099c Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 20 Nov 2024 09:26:38 +0200 Subject: [PATCH 29/68] ARM: tegra124: dts: mark HOST1X and DC with pre-relocation flag Same as on previous SoC generations this is required for proper video output work. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 +-------- arch/arm/dts/tegra124-u-boot.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index 376dcdf68fb..8a629bfe703 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -4,16 +4,9 @@ * Written by Simon Glass */ -#include "tegra-u-boot.dtsi" +#include "tegra124-u-boot.dtsi" / { - host1x@50000000 { - bootph-all; - dc@54200000 { - bootph-all; - }; - }; - spi@7000d400 { spi-deactivate-delay = <500>; spi-max-frequency = <3000000>; diff --git a/arch/arm/dts/tegra124-u-boot.dtsi b/arch/arm/dts/tegra124-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra124-u-boot.dtsi +++ b/arch/arm/dts/tegra124-u-boot.dtsi @@ -1,3 +1,16 @@ #include #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; From 9095fb12110e24cfb383f49f2d491686324c53a2 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 3 Dec 2024 12:50:45 +0200 Subject: [PATCH 30/68] doc: board: tegra: update device information Adjust and update existing manuals to reflect the most recent updates. Signed-off-by: Svyatoslav Ryhel --- doc/board/asus/grouper.rst | 12 ++++++------ doc/board/asus/transformer_t20.rst | 6 +++--- doc/board/asus/transformer_t30.rst | 13 +++++++------ doc/board/htc/endeavoru.rst | 9 ++++----- doc/board/lg/x3_t30.rst | 20 ++++++++++---------- doc/board/microsoft/surface-rt.rst | 4 ++-- doc/board/wexler/qc750.rst | 9 ++++----- 7 files changed, 36 insertions(+), 37 deletions(-) diff --git a/doc/board/asus/grouper.rst b/doc/board/asus/grouper.rst index d56a9ca3921..14469582907 100644 --- a/doc/board/asus/grouper.rst +++ b/doc/board/asus/grouper.rst @@ -25,7 +25,7 @@ along with cellular one. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make grouper_defconfig # For all grouper versions and tilapia $ make @@ -79,18 +79,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have cellular version, +use ``tilapia.bct``. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst index d4bc12d1619..4f4f893c3a8 100644 --- a/doc/board/asus/transformer_t20.rst +++ b/doc/board/asus/transformer_t20.rst @@ -25,7 +25,7 @@ defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t20_defconfig tf101.config # For TF101 $ make @@ -84,8 +84,8 @@ encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break + $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst index bebc4b9fad3..012a38251aa 100644 --- a/doc/board/asus/transformer_t30.rst +++ b/doc/board/asus/transformer_t30.rst @@ -22,6 +22,7 @@ Build U-Boot U-Boot features ability to detect transformer device model on which it is loaded. The list of supported devices include: + - ASUS Transformer Prime TF201 - ASUS Transformer Pad (3G/LTE) TF300T/TG/TL - ASUS Transformer Infinity TF700T @@ -30,7 +31,7 @@ loaded. The list of supported devices include: .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t30_defconfig $ make @@ -84,18 +85,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that you should adjust bct file +name according to your device. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst index e0edefe28ae..53df2d09a6f 100644 --- a/doc/board/htc/endeavoru.rst +++ b/doc/board/htc/endeavoru.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make endeavoru_defconfig $ make @@ -72,16 +72,15 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst index 618b00d34e3..9ff75034b72 100644 --- a/doc/board/lg/x3_t30.rst +++ b/doc/board/lg/x3_t30.rst @@ -24,7 +24,7 @@ board defconfig. Valid fragments are ``p880.config`` and ``p895.config``. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make x3_t30_defconfig p895.config # For LG Optimus Vu $ make @@ -75,18 +75,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have Optimus 4x HD, +use ``p880.bct``. Flashing with a pre-loaded U-Boot ********************************* @@ -122,7 +122,7 @@ the user to use/partition it in any way the user desires. Self Upgrading -------------- -Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using -ability of u-boot to mount it). Enter bootmenu, choose update bootloader option -with Power button and U-Boot should update itself. Once the process is -completed, U-Boot will ask to press any button to reboot. +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC or MicroSD +card if it is supported (using ability of u-boot to mount it). Enter bootmenu, +choose update bootloader option with Power button and U-Boot should update itself. +Once the process is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/microsoft/surface-rt.rst b/doc/board/microsoft/surface-rt.rst index b5645e79340..2b29cce40a9 100644 --- a/doc/board/microsoft/surface-rt.rst +++ b/doc/board/microsoft/surface-rt.rst @@ -14,7 +14,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make surface-rt_defconfig $ make @@ -38,4 +38,4 @@ directory with To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on eMMC. Additionally, if the Volume Down button is pressed while loading, the device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC -as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console. +as mass storage, fastboot, reboot, reboot RCM, poweroff and enter U-Boot console. diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst index b61e40176b0..169629c7e47 100644 --- a/doc/board/wexler/qc750.rst +++ b/doc/board/wexler/qc750.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make qc750_defconfig $ make @@ -71,16 +71,15 @@ pre-loading just built U-Boot into RAM. Flashing with the NV3P protocol ******************************* -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is +used to handle such state. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --bct qc750.bct --bl bootloader.bin + $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000 $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. From df48a95588f7dfb36c39e24a5c4777d2357d4f1d Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 28 Dec 2024 15:21:03 +0200 Subject: [PATCH 31/68] board: transformer-t30: fix model detection PCBID1 seems to be high not only on TF600T, but on TF700T as well, that caused boot failure for TF700T. Switching PCBID1 to PCBID7 should fix this issue. Co-developed-by: Ion Agorria Signed-off-by: Ion Agorria Signed-off-by: Svyatoslav Ryhel --- board/asus/transformer-t30/board-info.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c index a2b540c90b6..e72614164b4 100644 --- a/board/asus/transformer-t30/board-info.c +++ b/board/asus/transformer-t30/board-info.c @@ -11,14 +11,14 @@ #include /* - * PCB_ID[1] is kb_row5_pr5 * PCB_ID[3] is kb_col7_pq7 * PCB_ID[4] is kb_row2_pr2 * PCB_ID[5] is kb_col5_pq5 + * PCB_ID[7] is gmi_cs1_n_pj2 * * Project ID * ===================================================== - * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project + * PCB_ID[7] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project * 0 0 0 0 TF201 * 0 0 0 1 P1801 * 0 0 1 0 TF300T @@ -45,10 +45,10 @@ static const char * const project_id_to_fdt[] = { [TF600T] = "tegra30-asus-tf600t", }; -static int id_gpio_get_value(u32 pingrp, u32 pin) +static int id_gpio_get_value(u32 pingrp, u32 func, u32 pin) { /* Configure pinmux */ - pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_func(pingrp, func); pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); pinmux_tristate_enable(pingrp); pinmux_set_io(pingrp, PMUX_PIN_INPUT); @@ -65,19 +65,19 @@ static int id_gpio_get_value(u32 pingrp, u32 pin) static int get_project_id(void) { - u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5; + u32 pcb_id3, pcb_id4, pcb_id5, pcb_id7; - pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5, - TEGRA_GPIO(R, 5)); pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7, - TEGRA_GPIO(Q, 7)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 7)); pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2, - TEGRA_GPIO(R, 2)); + PMUX_FUNC_KBC, TEGRA_GPIO(R, 2)); pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5, - TEGRA_GPIO(Q, 5)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 5)); + pcb_id7 = id_gpio_get_value(PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_FUNC_RSVD1, TEGRA_GPIO(J, 2)); /* Construct board ID */ - int proj_id = pcb_id1 << 3 | pcb_id5 << 2 | + int proj_id = pcb_id7 << 3 | pcb_id5 << 2 | pcb_id4 << 1 | pcb_id3; log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id, From f9edd081b11b5eda06581b4f0c4f738359895507 Mon Sep 17 00:00:00 2001 From: ZHANG Yuntian Date: Tue, 11 Feb 2025 15:30:27 +0800 Subject: [PATCH 32/68] mbedtls/external: remove broken git submodule When we squash imported mbedtls, the git submodule "framework" was preserved in the commit. However, U-Boot itself does not use git submodule, and provides no .gitmodules file to specify the submodule repository. This is normally not an issue when cloning U-Boot repository. However, when U-Boot is imported as a submodule, this will break git option `--recurse-submodules` as it fails to resolve "framework". As we do not use the submodule, remove it to unbreak existing workflows. Fixes: 12f1212e95fe ("Merge commit '0344c602eadc0802776b65ff90f0a02c856cf53c' as 'lib/mbedtls/external/mbedtls'") Signed-off-by: ZHANG Yuntian --- lib/mbedtls/external/mbedtls/framework | 1 - 1 file changed, 1 deletion(-) delete mode 160000 lib/mbedtls/external/mbedtls/framework diff --git a/lib/mbedtls/external/mbedtls/framework b/lib/mbedtls/external/mbedtls/framework deleted file mode 160000 index 750634d3a51..00000000000 --- a/lib/mbedtls/external/mbedtls/framework +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 750634d3a51eb9d61b59fd5d801546927c946588 From 9f95282f31d28323d0c99b258b648936e5eadf60 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jan 2025 22:59:18 +0100 Subject: [PATCH 33/68] arm64: Add late jump to kernel board hook Add empty weak assembler function armv8_switch_to_el2_prep() which is jumped to just before U-Boot determines which EL it is running in and decides which path to take to boot the Linux kernel. This weak function is meant to be used by architecture specific code to implement jump to a firmware blob, which then returns right past this weak function and continues execution of U-Boot code which then boots the Linux kernel. One example of such use case is when U-Boot jump tp TFA BL31, which switches from EL3 to EL2 and then returns to U-Boot code newly running in EL2 and starts the Linux kernel. The weak function is called with caches already disabled and DM shut down. Any preparatory work or even loading of more data must be done in board_prep_linux(), this hook is meant only for the final jump to the firmware and return to U-Boot before booting Linux. Reviewed-by: Tom Rini Signed-off-by: Marek Vasut --- arch/arm/cpu/armv8/transition.S | 8 ++++++++ arch/arm/include/asm/system.h | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index 9dbdff3a4fc..85f13ccd0d2 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -9,8 +9,16 @@ #include #include +.pushsection .text.armv8_switch_to_el2_prep, "ax" +WEAK(armv8_switch_to_el2_prep) + ret +ENDPROC(armv8_switch_to_el2_prep) +.popsection + .pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) + bl armv8_switch_to_el2_prep + nop switch_el x6, 1f, 0f, 0f 0: cmp x5, #ES_TO_AARCH64 diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dbf9ab43e28..091082281c7 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -238,6 +238,22 @@ int __asm_flush_l3_dcache(void); int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); +/* + * armv8_switch_to_el2_prep() - prepare for switch from EL3 to EL2 for ARMv8 + * + * @args: For loading 64-bit OS, fdt address. + * For loading 32-bit OS, zero. + * @mach_nr: For loading 64-bit OS, zero. + * For loading 32-bit OS, machine nr + * @fdt_addr: For loading 64-bit OS, zero. + * For loading 32-bit OS, fdt address. + * @arg4: Input argument. + * @entry_point: kernel entry point + * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 + */ +void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point, u64 es_flag); + /* * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 * From 854a5a00cadd6ea4adcc9e4a923124887989f5f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jan 2025 22:59:19 +0100 Subject: [PATCH 34/68] image: Add support for starting TFA BL31 as fitImage loadables Add support for starting TFA from U-Boot running in EL3 as part of fitImage boot, so the user can start U-Boot in the highest privilege level on the platform, bundle TFA, Linux, DT into a single fitImage and boot such a bundle as a whole. There are two main benefits of this approach. First is the ability to run U-Boot in EL3, where it has unrestricted access to the entire system and can act as a useful debug tool, as it was always intended to be used. Second is the ability to easily and safely update of any component in the fitImage, be it TFA, Linux or DT. The boot process is similar to regular Linux with DT fitImage boot process, except the TFA has to be bundled into the fitImage. For the bundling instructions, see below. The TFA is started as a 'loadables' with custom U_BOOT_FIT_LOADABLE_HANDLER and armv8_switch_to_el2_prep() handling implemented in board code, and performing the handoff and boot in case the TFA was loaded. The loadables handler is optional and meant to set up any sort of handoff structures used by the TFA BL31 or perform any other setup that is needed by the blob. The custom armv8_switch_to_el2_prep() has to implement the jump to TFA BL31 with return to U-Boot just before booting the Linux kernel. Example fitImage image and configuration section: /dts-v1/; / { description = "Linux kernel with FDT blob and TFA BL31"; images { kernel-1 { ... }; fdt-1 { ... }; atf-1 { /* This is the TFA BL31 image */ description = "TFA BL31"; data = /incbin/("../build/plat/release/bl31.bin"); type = "tfa-bl31"; arch = "arm64"; os = "arm-trusted-firmware"; compression = "none"; load = <0x46400000>; entry = <0x46400000>; }; }; configurations { default = "conf-1"; conf-1 { description = "Boot Linux"; kernel = "kernel-1"; fdt = "fdt-1"; loadables = "atf-1"; /* This is the TFA BL31 loadable */ }; }; }; Reviewed-by: Tom Rini Signed-off-by: Marek Vasut --- boot/image-fit.c | 1 + boot/image.c | 1 + include/image.h | 1 + 3 files changed, 3 insertions(+) diff --git a/boot/image-fit.c b/boot/image-fit.c index aa139da628c..41ab1f552b0 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -2175,6 +2175,7 @@ int fit_image_load(struct bootm_headers *images, ulong addr, type_ok = fit_image_check_type(fit, noffset, image_type) || fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) || fit_image_check_type(fit, noffset, IH_TYPE_TEE) || + fit_image_check_type(fit, noffset, IH_TYPE_TFA_BL31) || (image_type == IH_TYPE_KERNEL && fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD)); diff --git a/boot/image.c b/boot/image.c index abac254e026..139c5bd035a 100644 --- a/boot/image.c +++ b/boot/image.c @@ -183,6 +183,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", }, { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" }, { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" }, + { IH_TYPE_TFA_BL31, "tfa-bl31", "TFA BL31 Image", }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 8a9f779d3ff..07912606f33 100644 --- a/include/image.h +++ b/include/image.h @@ -232,6 +232,7 @@ enum image_type_t { IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */ + IH_TYPE_TFA_BL31, /* TFA BL31 image */ IH_TYPE_COUNT, /* Number of image types */ }; From ad3ec11b393b7d89d1df353324df4600b219a647 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 21 Jan 2024 15:37:57 +0200 Subject: [PATCH 35/68] board: acer: picasso: add Acer Iconia Tab A500 support The Acer Iconia A500 is a tablet computer designed, developed and marketed by Acer Inc. It is powered by 1 GHz Nvidia Tegra 2 processor and 1GB DDR2 RAM. The A500 is sold with 64 GB, although both 16 GB and 32 GB models are available. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra20-acer-a500-picasso.dts | 508 +++++++++++++++++++++ arch/arm/mach-tegra/tegra20/Kconfig | 5 + board/acer/picasso/Kconfig | 12 + board/acer/picasso/MAINTAINERS | 7 + board/acer/picasso/Makefile | 9 + board/acer/picasso/picasso.c | 57 +++ board/acer/picasso/picasso.env | 18 + configs/picasso_defconfig | 83 ++++ doc/board/acer/index.rst | 9 + doc/board/acer/picasso.rst | 125 +++++ doc/board/index.rst | 1 + include/configs/picasso.h | 23 + 13 files changed, 858 insertions(+) create mode 100644 arch/arm/dts/tegra20-acer-a500-picasso.dts create mode 100644 board/acer/picasso/Kconfig create mode 100644 board/acer/picasso/MAINTAINERS create mode 100644 board/acer/picasso/Makefile create mode 100644 board/acer/picasso/picasso.c create mode 100644 board/acer/picasso/picasso.env create mode 100644 configs/picasso_defconfig create mode 100644 doc/board/acer/index.rst create mode 100644 doc/board/acer/picasso.rst create mode 100644 include/configs/picasso.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bf3697bdbe..acea0cc2ec1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_TEGRA) += \ + tegra20-acer-a500-picasso.dtb \ tegra20-asus-sl101.dtb \ tegra20-asus-tf101.dtb \ tegra20-asus-tf101g.dtb \ diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts new file mode 100644 index 00000000000..0c301483180 --- /dev/null +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra20.dtsi" + +/ { + model = "Acer Iconia Tab A500"; + compatible = "acer,picasso", "nvidia,tegra20"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "csus", "dap1", + "dap4", "dte", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", + "sdc", "sdd", "slxc", "slxd", "slxk", + "spdi", "spdo", "uac", "uad", "uda"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", + "gmd", "owc", "spia", "spib", "spic", + "spid", "spie"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spig", + "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_dte { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = ; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", + "uab", "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0"; + nvidia,pull = ; + }; + drive_ddc { + nvidia,pins = "drive_ddc", + "drive_vi1", + "drive_sdio1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = ; + nvidia,high-speed-mode = ; + nvidia,low-power-mode = ; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_dbg { + nvidia,pins = "drive_dbg", + "drive_vi2", + "drive_at1", + "drive_ao1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = ; + nvidia,high-speed-mode = ; + nvidia,low-power-mode = ; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + clock-frequency = <216000000>; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + avdd_usb: ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + }; + }; + }; + + usb1: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb3: usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 41667>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "tps658621-out32k"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + switch-rotation-lock { + label = "Rotate-lock"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + clock-frequency = <71200000>; + + hactive = <1280>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + + vactive = <800>; + vfront-porch = <4>; + vback-porch = <8>; + vsync-len = <3>; + }; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 6458827d6dc..e2735d93e28 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -33,6 +33,10 @@ config TARGET_PAZ00 bool "Paz00 board" select BOARD_LATE_INIT +config TARGET_PICASSO + bool "Acer Tegra20 Picasso board" + select BOARD_LATE_INIT + config TARGET_PLUTUX bool "Avionic Design Plutux board" select BOARD_LATE_INIT @@ -73,6 +77,7 @@ config SYS_SOC source "board/nvidia/harmony/Kconfig" source "board/avionic-design/medcom-wide/Kconfig" source "board/compal/paz00/Kconfig" +source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" source "board/nvidia/seaboard/Kconfig" source "board/avionic-design/tec/Kconfig" diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig new file mode 100644 index 00000000000..73c0aa08508 --- /dev/null +++ b/board/acer/picasso/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PICASSO + +config SYS_BOARD + default "picasso" + +config SYS_VENDOR + default "acer" + +config SYS_CONFIG_NAME + default "picasso" + +endif diff --git a/board/acer/picasso/MAINTAINERS b/board/acer/picasso/MAINTAINERS new file mode 100644 index 00000000000..99f8c0b6d7f --- /dev/null +++ b/board/acer/picasso/MAINTAINERS @@ -0,0 +1,7 @@ +PICASSO BOARD +M: Svyatoslav Ryhel +S: Maintained +F: board/acer/picasso/ +F: configs/picasso_defconfig +F: doc/board/acer/picasso.rst +F: include/configs/picasso.h diff --git a/board/acer/picasso/Makefile b/board/acer/picasso/Makefile new file mode 100644 index 00000000000..675059c112d --- /dev/null +++ b/board/acer/picasso/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation +# +# (C) Copyright 2024 +# Svyatoslav Ryhel + +obj-y += picasso.o diff --git a/board/acer/picasso/picasso.c b/board/acer/picasso/picasso.c new file mode 100644 index 00000000000..d3e600cad52 --- /dev/null +++ b/board/acer/picasso/picasso.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * (C) Copyright 2024 + * Svyatoslav Ryhel + */ + +/* Picasso derives from Ventana board */ + +#include +#include +#include +#include + +#define TPS6586X_I2C_ADDRESS 0x34 +#define TPS6586X_SUPPLYENE 0x14 +#define EXITSLREQ_BIT BIT(1) +#define SLEEP_MODE_BIT BIT(3) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] &= ~EXITSLREQ_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= SLEEP_MODE_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + printf("Failed to power off!!!\n"); + return 1; +} +#endif diff --git a/board/acer/picasso/picasso.env b/board/acer/picasso/picasso.env new file mode 100644 index 00000000000..d9409b07d98 --- /dev/null +++ b/board/acer/picasso/picasso.env @@ -0,0 +1,18 @@ +#include + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +boot_block_size_r=0x100000 +boot_block_size=0x800 +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig new file mode 100644 index 00000000000..994951bb81e --- /dev/null +++ b/configs/picasso_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x00110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="picasso" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra20-acer-a500-picasso" +CONFIG_SPL_STACK=0xffffc +CONFIG_SPL_TEXT_BASE=0x00108000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_TEGRA20=y +CONFIG_TARGET_PICASSO=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; poweroff" +CONFIG_SYS_PBSIZE=2085 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra20 (Picasso) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x11000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Acer" +CONFIG_USB_GADGET_VENDOR_NUM=0x0502 +CONFIG_USB_GADGET_PRODUCT_NUM=0x3325 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +# CONFIG_VIDEO_BPP8 is not set +CONFIG_VIDEO_TEGRA20=y diff --git a/doc/board/acer/index.rst b/doc/board/acer/index.rst new file mode 100644 index 00000000000..3741a700ccd --- /dev/null +++ b/doc/board/acer/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ACER +==== + +.. toctree:: + :maxdepth: 2 + + picasso diff --git a/doc/board/acer/picasso.rst b/doc/board/acer/picasso.rst new file mode 100644 index 00000000000..b1d360defd8 --- /dev/null +++ b/doc/board/acer/picasso.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Acer Iconia Tab A500 +=================================== + +``DISCLAMER!`` Moving your Acer Iconia Tab A500 to use U-Boot assumes +replacement of the vendor Acer bootloader. Vendor Android firmwares will no +longer be able to run on the device. This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Process U-Boot +- Flashing U-Boot into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make picasso_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Process U-Boot +-------------- + +``DISCLAMER!`` All questions related to the re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form +usable by device. This process is required only on the first installation or +to recover the device in case of a failed update. + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Processing for the NV3P protocol +******************************** + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev a500 + +The script will produce a ``repart-block.bin`` ready to flash. + +Processing for pre-loaded U-Boot +******************************** + +The procedure is the same, but the ``--split`` argument is used with the +``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready +to flash. + +Flashing U-Boot into the eMMC +----------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Flashing with the NV3P protocol +******************************* + +Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can +enter it either by pre-loading vendor bootloader into RAM with the nvflash. + +With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in +encrypted state in form, which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ nvflash --setbct --bct picasso.bct --configfile flash.cfg --bl bootloader.bin + --sbk 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX --sync # replace with your SBK + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +When flashing is done, reboot the device. + +Flashing with a pre-loaded U-Boot +********************************* + +U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently +U-Boot supports bootmenu entry fastboot, which allows to write a processed copy +of U-Boot permanently into eMMC. + +While pre-loading U-Boot, hold the ``volume down`` button which will trigger +the bootmenu. There, select ``fastboot`` using the volume and power buttons. +After, on host PC, do: + +.. code-block:: bash + + $ fastboot flash 0.1 bct.img + $ fastboot flash 0.2 ebt.img + $ fastboot reboot + +Device will reboot. + +Boot +---- + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while booting, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console +and update bootloader (check the next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows +the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card +and insert it into the tablet. Enter bootmenu, choose update the bootloader +option with the Power button and U-Boot should update itself. Once the process +is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/index.rst b/doc/board/index.rst index 74c4dd1f42d..b055046e649 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -6,6 +6,7 @@ Board-specific doc .. toctree:: :maxdepth: 2 + acer/index actions/index advantech/index andestech/index diff --git a/include/configs/picasso.h b/include/configs/picasso.h new file mode 100644 index 00000000000..a58c7e5f353 --- /dev/null +++ b/include/configs/picasso.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * (C) Copyright 2024 + * Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ From 714a0227fefc51e0f7b072d39f5ccc4ebc1f9140 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 16 Feb 2025 10:29:03 -0600 Subject: [PATCH 36/68] Gitlab: Add missing symlink for qemu_arm64_lwip boardenv file When adding the symlink for the conf file so qemu_arm64_lwip uses qemu_arm64 configuration information, the symlink for the boardenv file was missed in Gitlab (but not Azure). Add that in now. Fixes: fd10d156db3f ("CI: add qemu_arm64_lwip to the test matrix") Reviewed-by: Jerome Forissier Signed-off-by: Tom Rini --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 920f61eaa09..46226eb2fc1 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -40,6 +40,7 @@ stages: # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled. # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks - ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na + - ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then From 92880a58cafc93c0907b9d3a6b13e6425366b7c0 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Thu, 6 Feb 2025 11:28:56 +0200 Subject: [PATCH 37/68] tpm: unconstify tpm_tis_chip_data The struct contains an iomem pointer that we later remap and update. Remove const from the struct definition. Signed-off-by: Ilias Apalodimas --- drivers/tpm/tpm2_tis_mmio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c index dee5503c055..fc62dcda9ef 100644 --- a/drivers/tpm/tpm2_tis_mmio.c +++ b/drivers/tpm/tpm2_tis_mmio.c @@ -135,7 +135,7 @@ static const struct tpm_ops tpm_tis_ops = { .cleanup = tpm_tis_cleanup, }; -static const struct tpm_tis_chip_data tpm_tis_std_chip_data = { +static struct tpm_tis_chip_data tpm_tis_std_chip_data = { .pcr_count = 24, .pcr_select_min = 3, }; From e93f11148ae42bbb805077a48ab8cb63137a3a17 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Tue, 11 Feb 2025 23:21:58 +0530 Subject: [PATCH 38/68] power: regulator: tps65941: Fix voltage calculation for ldo As per TRM[0] Section 8.7.1 "TPS6594-Q1 Registers", LDOx_Vout bit 6-1, define the NVM voltage settings. Along side table 8-4 of above TRM, shows voltage to value mapping. Driver wrongly using bits 5-1 to calculate voltage, and to convert voltage to value driver was using buck's calculation. So fix those calculation. [0]: https://www.ti.com/lit/ds/symlink/tps6594-q1.pdf Fixes: 5d7dbd22cf7d ("power: regulator: tps65941: use function callbacks for conversion ops") Signed-off-by: Udit Kumar Reviewed-by: Neha Malcom Francis --- drivers/power/regulator/tps65941_regulator.c | 16 +++++++++++++--- include/power/tps65941.h | 3 ++- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index bc4d153fd84..13f94b730d4 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -388,6 +388,14 @@ static int tps65941_ldo_enable(struct udevice *dev, int op, bool *enable) return 0; } +static int tps65941_ldo_volt2val(__maybe_unused int idx, int uV) +{ + if (uV > TPS65941_LDO_VOLT_MAX || uV < TPS65941_LDO_VOLT_MIN) + return -EINVAL; + + return ((uV - 600000) / 50000 + 0x4) << TPS65941_LDO_MODE_MASK; +} + static int tps65941_ldo_val2volt(__maybe_unused int idx, int val) { if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX) @@ -459,7 +467,7 @@ static int tps65224_ldo_val2volt(int idx, int val) static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { [TPS65941_LDO_CONV_OPS_IDX] = { .volt_mask = TPS65941_LDO_VOLT_MASK, - .volt2val = tps65941_buck_volt2val, + .volt2val = tps65941_ldo_volt2val, .val2volt = tps65941_ldo_val2volt, }, [TPS65224_LDO_CONV_OPS_IDX] = { @@ -472,7 +480,7 @@ static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) { unsigned int hex, adr; - int ret, ret_volt, idx; + int ret, ret_volt, idx, ldo_bypass; struct dm_regulator_uclass_plat *uc_pdata; const struct tps65941_reg_conv_ops *conv_ops; ulong chip_id; @@ -502,7 +510,9 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) if (ret < 0) return ret; + ldo_bypass = ret & TPS65941_LDO_BYPASS_EN; ret &= conv_ops->volt_mask; + ret = ret >> TPS65941_LDO_MODE_MASK; ret_volt = conv_ops->val2volt(idx, ret); if (ret_volt < 0) return ret_volt; @@ -531,7 +541,7 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) ret &= ~TPS65224_LDO_VOLT_MASK; ret |= hex; } else { - ret = hex; + ret = hex | ldo_bypass; } ret = pmic_reg_write(dev->parent, adr, ret); diff --git a/include/power/tps65941.h b/include/power/tps65941.h index cec85333f0b..a026ec56958 100644 --- a/include/power/tps65941.h +++ b/include/power/tps65941.h @@ -21,10 +21,11 @@ #define TPS65941_BUCK_VOLT_MAX 3340000 #define TPS65941_BUCK_MODE_MASK 0x1 -#define TPS65941_LDO_VOLT_MASK 0x3E +#define TPS65941_LDO_VOLT_MASK 0x7E #define TPS65941_LDO_VOLT_MAX_HEX 0x3A #define TPS65941_LDO_VOLT_MIN_HEX 0x4 #define TPS65941_LDO_VOLT_MAX 3300000 +#define TPS65941_LDO_VOLT_MIN 600000 #define TPS65941_LDO_MODE_MASK 0x1 #define TPS65941_LDO_BYPASS_EN 0x80 #define TP65941_BUCK_CONF_SLEW_MASK 0x7 From 50e8089c1de107137c7a30fd5691ebd449f42e2d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 11 Feb 2025 14:55:22 +0100 Subject: [PATCH 39/68] tools: use cryptographically safe RNG The PRNG implementing the random() function only has 2^31 states and therefore is unsafe to use for cryptography. Use arc4random() instead. Fixes: cc34f04efd63 ("tools: image-host.c: use random instead of rand") Addresses-Coverity-ID: 312953 Calling risky function Signed-off-by: Heinrich Schuchardt --- tools/image-host.c | 55 ++++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/tools/image-host.c b/tools/image-host.c index 84095d760c1..e6de34fa059 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -364,33 +364,46 @@ static int fit_image_read_key_iv_data(const char *keydir, const char *key_iv_nam return ret; } -static int get_random_data(void *data, int size) +/** + * get_random_data() - fill buffer with random data + * + * There is no common cryptographically safe function in Linux and BSD. + * Hence directly access the /dev/urandom PRNG. + * + * @data: buffer to fill + * @size: buffer size + */ +static int get_random_data(void *data, size_t size) { - unsigned char *tmp = data; - struct timespec date; - int i, ret; + int fd; + int ret; - if (!tmp) { - fprintf(stderr, "%s: pointer data is NULL\n", __func__); - ret = -1; - goto out; + fd = open("/dev/urandom", O_RDONLY); + if (fd < 0) { + perror("Failed to open /dev/urandom"); + return -1; } - ret = clock_gettime(CLOCK_MONOTONIC, &date); - if (ret) { - fprintf(stderr, "%s: clock_gettime has failed (%s)\n", __func__, - strerror(errno)); - goto out; + while (size) { + ssize_t count; + + count = read(fd, data, size); + if (count < 0) { + if (errno == EINTR) { + continue; + } else { + perror("Failed to read from /dev/urandom"); + ret = -1; + goto out; + } + } + data += count; + size -= count; } + ret = 0; +out: + close(fd); - srandom(date.tv_nsec); - - for (i = 0; i < size; i++) { - *tmp = random() & 0xff; - tmp++; - } - - out: return ret; } From cdc67e27500fbde1fc42528c38842e5c5d785a51 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 12 Feb 2025 10:10:55 +0100 Subject: [PATCH 40/68] led: fix coverity scan error The following was reported by Covervity scan: *** CID 541279: (TAINTED_SCALAR) /drivers/led/led-uclass.c: 284 in led_get_function_name() 278 if (!ret) { 279 snprintf(uc_plat->name, LED_MAX_NAME_SIZE, 280 "%s:%s-%d", 281 cp ? "" : led_colors[color], 282 func ? func : "", enumerator); 283 } else { >>> CID 541279: (TAINTED_SCALAR) >>> Using tainted variable "color" as an index into an array "led_colors". Fix it. Addresses-Coverity-ID: 541279 (TAINTED_SCALAR) Link: https://lists.denx.de/pipermail/u-boot/2025-February/580250.html Signed-off-by: Heiko Schocher --- drivers/led/led-uclass.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 27ef890ed0a..22f61d12d38 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -273,6 +273,10 @@ static const char *led_get_function_name(struct udevice *dev) /* Now try to detect function label name */ func = dev_read_string(dev, "function"); cp = dev_read_u32(dev, "color", &color); + // prevent coverity scan error CID 541279: (TAINTED_SCALAR) + if (color < LED_COLOR_ID_WHITE || color >= LED_COLOR_ID_MAX) + cp = -EINVAL; + if (cp == 0 || func) { ret = dev_read_u32(dev, "function-enumerator", &enumerator); if (!ret) { From 7a45cb4ffeff034304789954bb222ddd7d02104a Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Thu, 13 Feb 2025 19:28:47 +0800 Subject: [PATCH 41/68] fs/erofs: fix an integer overflow in symlink resolution See the original report [1], otherwise len + 1 will be overflowed. Note that EROFS archive can record arbitary symlink sizes in principle, so we don't assume a short number like 4096. [1] https://lore.kernel.org/r/20250210164151.GN1233568@bill-the-cat Fixes: 830613f8f5bb ("fs/erofs: add erofs filesystem support") Signed-off-by: Gao Xiang --- fs/erofs/fs.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c index 7bd2e8fcfc5..dcdc883e34c 100644 --- a/fs/erofs/fs.c +++ b/fs/erofs/fs.c @@ -59,16 +59,19 @@ struct erofs_dir_stream { static int erofs_readlink(struct erofs_inode *vi) { - size_t len = vi->i_size; + size_t alloc_size; char *target; int err; - target = malloc(len + 1); + if (__builtin_add_overflow(vi->i_size, 1, &alloc_size)) + return -EFSCORRUPTED; + + target = malloc(alloc_size); if (!target) return -ENOMEM; - target[len] = '\0'; + target[vi->i_size] = '\0'; - err = erofs_pread(vi, target, len, 0); + err = erofs_pread(vi, target, vi->i_size, 0); if (err) goto err_out; From 3f866c47b58236d15a4ff761dd62e8955d7826b3 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Mon, 10 Feb 2025 08:27:47 +0100 Subject: [PATCH 42/68] board: verdin-am62: add dram_init_banksize Add the dram_init_banksize function to the board file to properly set DRAM memory sizes during boot. The commit bc07851897bd ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled") relocated the dram_init_banksize function from architecture specific initialization to the TI board initialization code. As a result, boards relying on the previous setup now require this function to be defined within their board file to handle DRAM sizing correctly. Without this function defined the following error appears during boot: ERROR: Failed to allocate 0x1000 bytes below 0x0. Fixes: bc07851897bd ("board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled") Signed-off-by: Stefan Eichenberger Acked-by: Francesco Dolcini --- board/toradex/verdin-am62/verdin-am62.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index e948fc16ba9..b80b39b6767 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -35,6 +35,17 @@ int dram_init(void) return 0; } +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + return ret; +} + /* * Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM */ From 7dba748433e16206feaee0e1590d74e22986d8be Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 8 Feb 2025 22:49:38 +0000 Subject: [PATCH 43/68] Revert "rockchip: rk3399: Drop unneeded bob and kevin board specific code" These power rails must be on very early for the U-Boos SPL banner to be show over debug UART. This reverts commit af518a1dfe637cb4dc486d7a832585e4a48bc970. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/rk3399.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 1ce43c6f0d4..ba89079b1e7 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -15,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -133,6 +133,27 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + + if (IS_ENABLED(CONFIG_SPL_BUILD) && + (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || + IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running + * the SPI-Flash-based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), + GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), + GPIO_PULL_NORMAL); + } + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, From 227b505f04571dbaeff77001c8d383314b524d3c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 8 Feb 2025 22:49:39 +0000 Subject: [PATCH 44/68] rockchip: rk3399-gru: Enable TPL_GPIO for bob and kevin The PP1500 and PP3000 power rails must be on very early for the U-Boot TPL banner to be shown on debug UART. Enable TPL_GPIO Kconfig option for bob and kevin to allow use of spl_gpio.h functions in TPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- configs/chromebook_bob_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 1b018ef4d7c..5b8c0d35de6 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 1ee0c0e6c9d..a29a04aadde 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y From 76228340658f27f7b165e722c12f269095e3b857 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 8 Feb 2025 22:49:40 +0000 Subject: [PATCH 45/68] Revert "rockchip: rk3399: Fix TPL build of bob and kevin" These power rails must be on very early for the U-Boos TPL banner to be show over debug UART. This reverts commit 4576e65a5d6b10fd207c3a44061676ce0220d794. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index ba89079b1e7..0c28241c603 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -136,7 +136,7 @@ void board_debug_uart_init(void) struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; - if (IS_ENABLED(CONFIG_SPL_BUILD) && + if (IS_ENABLED(CONFIG_XPL_BUILD) && (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { rk_setreg(&grf->io_vsel, 1 << 0); From 64cec76899a9a32c2434a324cd400492e4f5a59d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 5 Feb 2025 01:29:53 +0800 Subject: [PATCH 46/68] rockchip: rk3399: grf: Fix enum typos for UART2 In the GRF header file, some instances of UART2 pinmux are prefixed with "GRF_UART2DBG" while others have "GRF_UART2DGB". Since UART2 is the default console UART and used for debugging, it is more likely the name should be UART2DBG. Fix the ones that are wrong. Fixes: a2c08df3813b ("pinctrl: add driver for rk3399") Fixes: fa72de10452c ("rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h") Signed-off-by: Chen-Yu Tsai Reviewed-by: Quentin Schulz Reviewed-by: Paul Kocialkowski Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 6 +++--- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index dd89cd20505..e6125d6bf54 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -466,18 +466,18 @@ enum { /* GRF_GPIO4C_IOMUX */ GRF_GPIO4C0_SEL_SHIFT = 0, GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, - GRF_UART2DGBB_SIN = 2, + GRF_UART2DBGB_SIN = 2, GRF_HDMII2C_SCL = 3, GRF_GPIO4C1_SEL_SHIFT = 2, GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, - GRF_UART2DGBB_SOUT = 2, + GRF_UART2DBGB_SOUT = 2, GRF_HDMII2C_SDA = 3, GRF_GPIO4C2_SEL_SHIFT = 4, GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, GRF_PWM_0 = 1, GRF_GPIO4C3_SEL_SHIFT = 6, GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, + GRF_UART2DBGC_SIN = 1, GRF_GPIO4C4_SEL_SHIFT = 8, GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, GRF_UART2DBGC_SOUT = 1, diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 0c28241c603..99597076d2c 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -157,7 +157,7 @@ void board_debug_uart_init(void) /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT); rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C4_SEL_MASK, GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); From 57ad1ed7e84ac36d3d838d8c1eba96f586995a42 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 30 Jan 2025 22:07:11 +0000 Subject: [PATCH 47/68] rockchip: sdram: Allow the first bank to extend beyond 4 GiB Allow the first bank to extend beyond 4 GiB when the blob of space for peripheral is located before start of DRAM, e.g. when start of DRAM is 0x40000000 and continue beyond the 4 GiB mark. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/sdram.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 1fb01e1c4b1..96a791bda2c 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -309,6 +309,8 @@ int dram_init_banksize(void) if (ram_top > SZ_4G && top < SZ_4G) { gd->bd->bi_dram[1].start = SZ_4G; gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + } else if (ram_top > SZ_4G && top == SZ_4G) { + gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE From 356236126da7877ab115c65f8cb21215443beb2f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 30 Jan 2025 22:07:12 +0000 Subject: [PATCH 48/68] rockchip: sdram: Limit usable ram_top to max 4G U-Boot only works correctly when it uses RAM below the 4G address boundary on Rockchip SoCs. Limit usable gd->ram_top to max 4G. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/sdram.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 96a791bda2c..4b8b6b9da7c 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -487,7 +487,8 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + /* Make sure U-Boot only uses the space below the 4G address boundary */ + u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); return (gd->ram_top > top) ? top : gd->ram_top; } From d5fc369a598d0e84dbcfe08e80d676cdd0a54a78 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 30 Jan 2025 22:07:13 +0000 Subject: [PATCH 49/68] rockchip: sdram: Ensure ram_base is correct in SPL Most Rockchip SoCs use 0x0 as DRAM base address, however some SoCs use 0x60000000 and RK3576 use 0x40000000 as DRAM base address. CFG_SYS_SDRAM_BASE is defined with correct address for each SoC and U-Boot proper use this to set correct gd->ram_base in setup_dest_addr(). SPL never assign any value to gd->ram_base and instead use the default, 0x0. Set correct gd->ram_base in dram_init() to ensure its correctness in SPL. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/sdram.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 4b8b6b9da7c..f7d32829295 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -478,6 +478,7 @@ int dram_init(void) debug("Cannot get DRAM size: %d\n", ret); return ret; } + gd->ram_base = ram.base; gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", (unsigned long)ram.base, (unsigned long)ram.size); From d4aac2894a8f4e6c01b7384d52ad5716b9289a37 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 7 Jan 2025 22:36:01 +0100 Subject: [PATCH 50/68] rockchip: use OF_UPSTREAM for rk3036 The device tree for rk3036 combined is now available in the /dts/upstream directory. Use imply OF_UPSTREAM to migrate all rk3036 boards. Reviewed-by: Kever Yang Signed-off-by: Johan Jonker --- arch/arm/dts/Makefile | 3 - ...sdk-u-boot.dtsi => rk3036-evb-u-boot.dtsi} | 8 +- arch/arm/dts/rk3036-kylin-u-boot.dtsi | 13 + arch/arm/dts/rk3036-sdk.dts | 74 --- arch/arm/dts/rk3036.dtsi | 439 ------------------ arch/arm/mach-rockchip/Kconfig | 1 + configs/evb-rk3036_defconfig | 4 +- configs/kylin-rk3036_defconfig | 4 +- include/dt-bindings/clock/rk3036-cru.h | 185 -------- 9 files changed, 22 insertions(+), 709 deletions(-) rename arch/arm/dts/{rk3036-sdk-u-boot.dtsi => rk3036-evb-u-boot.dtsi} (100%) create mode 100644 arch/arm/dts/rk3036-kylin-u-boot.dtsi delete mode 100644 arch/arm/dts/rk3036-sdk.dts delete mode 100644 arch/arm/dts/rk3036.dtsi delete mode 100644 include/dt-bindings/clock/rk3036-cru.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bf3697bdbe..d6a32975bfb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK3036) += \ - rk3036-sdk.dtb - dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-evb-u-boot.dtsi similarity index 100% rename from arch/arm/dts/rk3036-sdk-u-boot.dtsi rename to arch/arm/dts/rk3036-evb-u-boot.dtsi index ef7e0207c3e..f8857c736d0 100644 --- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi +++ b/arch/arm/dts/rk3036-evb-u-boot.dtsi @@ -1,9 +1,5 @@ #include "rk3036-u-boot.dtsi" -&uart2 { - bootph-all; -}; - &grf { bootph-all; }; @@ -11,3 +7,7 @@ &pinctrl { bootph-all; }; + +&uart2 { + bootph-all; +}; diff --git a/arch/arm/dts/rk3036-kylin-u-boot.dtsi b/arch/arm/dts/rk3036-kylin-u-boot.dtsi new file mode 100644 index 00000000000..f8857c736d0 --- /dev/null +++ b/arch/arm/dts/rk3036-kylin-u-boot.dtsi @@ -0,0 +1,13 @@ +#include "rk3036-u-boot.dtsi" + +&grf { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&uart2 { + bootph-all; +}; diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts deleted file mode 100644 index 3493150df92..00000000000 --- a/arch/arm/dts/rk3036-sdk.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "SDK-RK3036"; - compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; - - chosen { - stdout-path = &uart2; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&usb_host { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb_otg { - otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi deleted file mode 100644 index 75588de4863..00000000000 --- a/arch/arm/dts/rk3036.dtsi +++ /dev/null @@ -1,439 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include -#include -#include -#include -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3036"; - - interrupt-parent = <&gic>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - i2c1 = &i2c1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3036-smp"; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - arm,pl330-broken-no-flushp; - interrupts = , - ; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - sram: sram@10080000 { - compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; - reg = <0x10080000 0x2000>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = ; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon"; - reg = <0x20008000 0x1000>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - status = "disabled"; - }; - - emmc: dwmmc@1021c000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x1021c000 0x4000>; - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - disable-wp; - fifo-mode; - non-removable; - num-slots = <1>; - default-sample-phase = <158>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - }; - - sdmmc: dwmmc@10214000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = ; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3036-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>; - /* - <1 28 RK_FUNC_2 &pcfg_pull_up>, - <1 29 RK_FUNC_2 &pcfg_pull_up>, - <1 30 RK_FUNC_2 &pcfg_pull_up>, - <1 31 RK_FUNC_2 &pcfg_pull_up>; - */ - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart1 */ - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4d3157b2edd..adac11a6b89 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,6 +29,7 @@ config ROCKCHIP_RK3036 select CPU_V7A select SUPPORT_SPL select SPL + imply OF_UPSTREAM imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB imply ROCKCHIP_COMMON_BOARD diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index ba79960495e..d215af0c046 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -11,7 +11,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-evb" CONFIG_ROCKCHIP_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0x10081fff @@ -23,7 +23,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index dd25fd60107..bc60bc57075 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -12,7 +12,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-kylin" CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h deleted file mode 100644 index 2c0552d1a93..00000000000 --- a/include/dt-bindings/clock/rk3036-cru.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_NANDC 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 - -#define DCLK_LCDC 190 - -/* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_LCDC 197 -#define ACLK_VIO 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_SPI 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 - -/* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 -#define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 - -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_SFC 47 - -#define SRST_PWM0 48 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_MAC 66 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_MMC0 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_WDT 86 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 - -#define SRST_HDMI_P 96 -#define SRST_VIO_BUS_H 99 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 - -#define SRST_DBG_P 131 - -#endif From 110428931cbc5791697a09096bf5f16ad016da20 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 12 Jan 2025 22:27:29 +0000 Subject: [PATCH 51/68] rockchip: rk3288: Use rk3288-cru.h from dts/upstream clock/rk3288-cru.h in include/dt-bindings is almost identical to the version in dts/upstream, remove the copy from include/dt-bindings to only use the version from dts/upstream. One clk, SCLK_MAC_PLL, is not part of the upstream bindings, this clk is not used by upstream, in-tree or vendor DTs and can safely be dropped. No functional change to board DTs is intended with this removal. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3288-cru.h | 381 ------------------------- 1 file changed, 381 deletions(-) delete mode 100644 include/dt-bindings/clock/rk3288-cru.h diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 453f66718c6..00000000000 --- a/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC_PLL 150 -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif From d5a3fb9ef82a99f3d6498d562691a6a3c84c5528 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 6 Jan 2025 21:39:42 +0000 Subject: [PATCH 52/68] pinctrl: rockchip: rk3328: Fix pinmux for GPIO2-B and GPIO3-B pins The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is recalculated so it remain unchanged. Add missing GPIO3-B1 to GPIO3-B7 pinmux data to rk3328_mux_recalced_data as mux register offset for these pins does not follow rockchip convention. This matches changes in following Linux commits: - e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins") - 5ef6914e0bf5 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins") - 128f71fe014f ("pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 59 ++++++++++++++++++++--- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 47c2e923a1b..dd0dc2eff27 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -14,23 +14,68 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -275,7 +320,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + IOMUX_8WIDTH_2BIT, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", From c4ec920cb9452a59ab054f98debecd41c4f21515 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 9 Feb 2025 23:27:55 +0000 Subject: [PATCH 53/68] net: dwc_eth_qos_rockchip: Fix disable of RX/TX delay for RK356x When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX and/or TX delay. Currently RX/TX delay is configured as enabled using zero as delay value for the rgmii-rxid/txid/id modes. Change to disable RX and/or TX delay and using zero as delay value. Signed-off-by: Jonas Karlman Reviewed-by: Quentin Schulz Reviewed-by: Kever Yang --- drivers/net/dwc_eth_qos_rockchip.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 9fc8c686b88..3e10e07403c 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -46,6 +46,10 @@ struct rockchip_platform_data { #define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) #define GRF_CLR_BIT(nr) (BIT((nr) + 16)) +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev, regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RGMII | - RK3568_GMAC_RXCLK_DLY_ENABLE | - RK3568_GMAC_TXCLK_DLY_ENABLE); + DELAY_ENABLE(RK3568, tx_delay, rx_delay)); return 0; } From 8d25dbb725fd07ff43efc7cca80a56b04c48eb06 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 9 Feb 2025 23:27:56 +0000 Subject: [PATCH 54/68] net: dwc_eth_qos_rockchip: Fix disable of RX/TX delay for RK3588 When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX and/or TX delay. Currently RX/TX delay is configured as enabled using zero as delay value for the rgmii-rxid/txid/id modes. Change to disable RX and/or TX delay and using zero as delay value. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/net/dwc_eth_qos_rockchip.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 3e10e07403c..f3a0f63003e 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -134,6 +134,10 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; } +#define RK3588_DELAY_ENABLE(id, tx, rx) \ + (((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \ + ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id))) + /* sys_grf */ #define RK3588_GRF_GMAC_CON7 0x031c #define RK3588_GRF_GMAC_CON8 0x0320 @@ -192,8 +196,7 @@ static int rk3588_set_to_rgmii(struct udevice *dev, RK3588_GMAC_CLK_RGMII_MODE(id)); regmap_write(data->grf, RK3588_GRF_GMAC_CON7, - RK3588_GMAC_RXCLK_DLY_ENABLE(id) | - RK3588_GMAC_TXCLK_DLY_ENABLE(id)); + RK3588_DELAY_ENABLE(id, tx_delay, rx_delay)); regmap_write(data->grf, offset_con, RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | From d69097683d65652554639e9ff8cdb53e6e3ee63b Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 4 Feb 2025 21:38:43 +0000 Subject: [PATCH 55/68] arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boards BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MCI driver set PRWEN high on MMC_POWER_UP and low on MMC_POWER_OFF. Similarly U-Boot also set PRWEN high before accessing mmc. However, HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact. Model an always-on active low fixed regulator using GPIO4_D6 to fix use of sdmmc on older HW revisions of the board. Fixes: adeb5d2a4ba4 ("arm64: dts: rockchip: Add Radxa ROCK S0") Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20241119230838.4137130-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner [ upstream commit: 26c100232b09ced0857306ac9831a4fa9c9aa231 ] (cherry picked from commit ca8e0bedbc790b19b11efc223677d178b8eeb74e) Signed-off-by: Jonas Karlman --- .../src/arm64/rockchip/rk3308-rock-s0.dts | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts index bd6419a5c20..8311af4c868 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts @@ -74,6 +74,23 @@ vin-supply = <&vcc5v0_sys>; }; + /* + * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. + * This is modeled as an always-on active low fixed regulator. + */ + vcc_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_2030>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + vcc5v0_sys: regulator-5v0-vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -181,6 +198,12 @@ }; }; + sdmmc { + sdmmc_2030: sdmmc-2030 { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wifi { wifi_reg_on: wifi-reg-on { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -233,7 +256,7 @@ cap-mmc-highspeed; cap-sd-highspeed; disable-wp; - vmmc-supply = <&vcc_io>; + vmmc-supply = <&vcc_sd>; status = "okay"; }; From 3955668a9dd5d4ba5f37ac852e1cae1d3b17e71c Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 6 Feb 2025 14:05:03 +0100 Subject: [PATCH 56/68] configs: microchip_mpfs_icicle: set DEFAULT_FDT_FILE Variable $fdtfile needs to be set for automatically loading a device-tree from the ESP or boot partition. * Set CONFIG_DEFAULT_FDT_FILE in the defconfig. * Add $fdtfile to the default environment. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- configs/microchip_mpfs_icicle_defconfig | 1 + include/configs/microchip_mpfs_icicle.h | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 5ea6cc371aa..f8acaa98672 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 CONFIG_DISPLAY_CPUINFO=y diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 5ced45b88b2..0077f6a5f95 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -26,6 +26,7 @@ "scriptaddr=0x88100000\0" \ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV #endif /* __CONFIG_H */ From c6337c91e5dddad038886ad97435539dbf702130 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Mon, 10 Feb 2025 10:57:43 +0800 Subject: [PATCH 57/68] board: starfive: Update the maintainer file for VisionFive 2 board Update the maintainer file and mark jh7110 / visionfive2 related files with N: patterns. Signed-off-by: Hal Feng Reviewed-by: Leo Yu-Chi Liang --- board/starfive/visionfive2/MAINTAINERS | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index d7f638f9b41..898e284ce2c 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,8 +1,7 @@ STARFIVE JH7110 VISIONFIVE2 BOARD M: Minda Chen +M: Hal Feng S: Maintained -F: arch/riscv/include/asm/arch-jh7110/ -F: board/starfive/visionfive2/ -F: include/configs/starfive-visionfive2.h -F: configs/starfive_visionfive2_defconfig -F: drivers/pci/pcie_starfive_jh7110.c +F: drivers/ram/starfive/ +N: jh7110 +N: visionfive2 From 399a03442f0874bd2eecaa22f96a37378dabf390 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Mon, 10 Feb 2025 12:22:08 -0800 Subject: [PATCH 58/68] configs: starfive: use LwIP network stack and enable wget command Use LwIP network stack and enable wget HTTP command. The tftpput command is not currently supported by LwIP network stack so remove it. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- configs/starfive_visionfive2_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index c3f2142ae1b..1e0a99ed17b 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -75,7 +75,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y -CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" @@ -84,6 +84,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_LWIP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SYSCON=y From 87ef1987de3a47910b5b0a8fd84e1b928e56ceb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Fri, 17 Jan 2025 18:13:26 +0100 Subject: [PATCH 59/68] lib: uuid: support more efi protocols in uuid_guid_get_str() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add more EFI protocols GUIDs to the translation table used by uuid_guid_get_str(). Signed-off-by: Vincent Stehlé Cc: Tom Rini --- lib/uuid.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/uuid.c b/lib/uuid.c index 97388f597a6..75658778044 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -119,6 +119,10 @@ static const struct { "Block IO", EFI_BLOCK_IO_PROTOCOL_GUID, }, + { + "Disk IO", + EFI_DISK_IO_PROTOCOL_GUID, + }, { "Simple File System", EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID, @@ -127,6 +131,10 @@ static const struct { "Loaded Image", EFI_LOADED_IMAGE_PROTOCOL_GUID, }, + { + "Loaded Image Device Path", + EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID, + }, { "Graphics Output", EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID, @@ -139,10 +147,18 @@ static const struct { "HII Database", EFI_HII_DATABASE_PROTOCOL_GUID, }, + { + "HII Config Access", + EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID, + }, { "HII Config Routing", EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID, }, + { + "Load File", + EFI_LOAD_FILE_PROTOCOL_GUID, + }, { "Load File2", EFI_LOAD_FILE2_PROTOCOL_GUID, From 80908fee7705cd2edb2df94c3d124c44dd515582 Mon Sep 17 00:00:00 2001 From: Maks Mishin Date: Sun, 2 Feb 2025 20:59:40 +0300 Subject: [PATCH 60/68] efi_loader: Fix potential deref-after-null After having been compared to a NULL value at efi_disk.c:426, pointer 'part_info' is dereferenced at efi_disk.c:534. Signed-off-by: Maks Mishin Reviewed-by: Heinrich Schuchardt --- lib/efi_loader/efi_disk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 1f3de0a2339..5452640354e 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -531,7 +531,8 @@ static efi_status_t efi_disk_add_dev( /* Store first EFI system partition */ if (part && efi_system_partition.uclass_id == UCLASS_INVALID) { - if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) { + if (part_info && + part_info->bootable & PART_EFI_SYSTEM_PARTITION) { efi_system_partition.uclass_id = desc->uclass_id; efi_system_partition.devnum = desc->devnum; efi_system_partition.part = part; From 530e869ff89d9575103637af201fe97864d4f577 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 14 Feb 2025 15:46:45 +0200 Subject: [PATCH 61/68] efi_loader: remove comparisons to string literals from runtime For EFI runtime services, we manage to preserve string literals by placing the .efi_runtime section just before .data and preserving it when marking the runtime memory by marking surrounding boottime code as runtime. This is ok for now but will break if we update any linker scripts and decouple .text and .runtime sections. So let's define the strings we used to compare in the appropriate section for runtime services Signed-off-by: Ilias Apalodimas Reviewed-by: Mark Kettenis --- lib/efi_loader/efi_var_mem.c | 3 ++- lib/efi_loader/efi_variable_tee.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index b265d95dd6b..31180df9e3a 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -19,6 +19,7 @@ */ static struct efi_var_file __efi_runtime_data *efi_var_buf; static struct efi_var_entry __efi_runtime_data *efi_current_var; +static const u16 __efi_runtime_rodata vtf[] = u"VarToFile"; /** * efi_var_mem_compare() - compare GUID and name with a variable @@ -331,7 +332,7 @@ efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, if (timep) *timep = var->time; - if (!u16_strcmp(variable_name, u"VarToFile")) + if (!u16_strcmp(variable_name, vtf)) return efi_var_collect_mem(data, data_size, EFI_VARIABLE_NON_VOLATILE); old_size = *data_size; diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index 0d090d051dd..6a1fa39bb6f 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -41,6 +41,7 @@ static u16 mm_sp_id; extern struct efi_var_file __efi_runtime_data *efi_var_buf; static efi_uintn_t max_buffer_size; /* comm + var + func + data */ static efi_uintn_t max_payload_size; /* func + data */ +static const u16 __efi_runtime_rodata pk[] = u"PK"; struct mm_connection { struct udevice *tee; @@ -858,7 +859,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (alt_ret != EFI_SUCCESS) goto out; - if (!u16_strcmp(variable_name, u"PK")) + if (!u16_strcmp(variable_name, pk)) alt_ret = efi_init_secure_state(); out: free(comm_buf); From bd8bc53162edde1970c04c472a8058c69bd71f3d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sat, 15 Feb 2025 16:22:06 +0100 Subject: [PATCH 62/68] efi_driver: create a parent device for all EFI block devices Up to now root has been the parent device for all block devices created via calling ConnectController(). This does not work well together with the implementation of bootstd. Add a dummy parent device for all EFI block devices. With this change EFI block devices are also accessible via commands like 'cat', 'load', and 'ls'. => dm tree Class Seq Probed Driver Name ----------------------------------------------------------- efi 0 [ + ] EFI block driver `-- efi blk 3 [ + ] efi_blk `-- efi.efiblk#0 partition 0 [ + ] blk_partition `-- efi.efiblk#0:1 => ls efiloader 0:1 13 hello.txt 7 u-boot.txt 2 file(s), 0 dir(s) => cat efiloader 0:1 hello.txt Hello world! => efidebug dh 0000000018df1700 (efi.efiblk#0:1) /VenHw(dbca4c98-6cb0-694d-0872-819c650cb7b8)/HD(1,MBR,0xd1535d21,0x1,0x7f) Block IO Simple File System Adjust the event dump unit test to consider the new event spy. Signed-off-by: Heinrich Schuchardt --- lib/efi_driver/efi_block_device.c | 29 ++++++++++++++++++++++++++++- test/py/tests/test_event_dump.py | 1 + 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index d3c668dc183..070747de515 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -35,8 +35,10 @@ #include #include #include +#include #include #include +#include /** * struct efi_blk_plat - attributes of a block device @@ -118,13 +120,18 @@ static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, static efi_status_t efi_bl_create_block_device(efi_handle_t handle, void *interface) { - struct udevice *bdev = NULL, *parent = dm_root(); + struct udevice *bdev = NULL, *parent; efi_status_t ret; + int r; int devnum; char *name; struct efi_block_io *io = interface; struct efi_blk_plat *plat; + r = uclass_find_first_device(UCLASS_EFI_LOADER, &parent); + if (r) + return EFI_OUT_OF_RESOURCES; + devnum = blk_next_free_devnum(UCLASS_EFI_LOADER); if (devnum < 0) return EFI_OUT_OF_RESOURCES; @@ -221,6 +228,24 @@ efi_bl_init(struct efi_driver_binding_extended_protocol *this) return EFI_SUCCESS; } +/** + * efi_block_device_create() - create parent for EFI block devices + * + * Create a device that serves as parent for all block devices created via + * ConnectController(). + * + * Return: 0 for success + */ +static int efi_block_device_create(void) +{ + int ret; + struct udevice *dev; + + ret = device_bind_driver(gd->dm_root, "EFI block driver", "efi", &dev); + + return ret; +} + /* Block device driver operators */ static const struct blk_ops efi_blk_ops = { .read = efi_bl_read, @@ -249,3 +274,5 @@ U_BOOT_DRIVER(efi_block) = { .id = UCLASS_EFI_LOADER, .ops = &driver_ops, }; + +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, efi_block_device_create); diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py index 45143c1c7d9..177b982e891 100644 --- a/test/py/tests/test_event_dump.py +++ b/test/py/tests/test_event_dump.py @@ -19,6 +19,7 @@ def test_event_dump(u_boot_console): EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.* EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.* EVT_LAST_STAGE_INIT alloc_write_acpi_tables .*lib/acpi/acpi_table.c:.* +EVT_LAST_STAGE_INIT efi_block_device_create .*lib/efi_driver/efi_block_device.c:.* EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.* EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.* EVT_TEST h_adder_simple .*test/common/event.c:''' From 08573d7688a8c133bd4a7354cf928f96e778b42a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 16 Feb 2025 12:12:39 +0100 Subject: [PATCH 63/68] lmb: avoid superfluous value check in lmb_map_update_notify() Instead of testing the value of parameter op at runtime use an enum to ensure that only valid values are used. Reviewed-by: Ilias Apalodimas Signed-off-by: Heinrich Schuchardt --- include/lmb.h | 12 ++++++++++++ lib/lmb.c | 23 +++++++---------------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/include/lmb.h b/include/lmb.h index d9d7435a431..09297a4f530 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -31,6 +31,18 @@ #define LMB_NOOVERWRITE BIT(1) #define LMB_NONOTIFY BIT(2) +/** + * enum lmb_map_op - memory map operation + */ +enum lmb_map_op { + /** @LMB_MAP_OP_RESERVE: reserve memory */ + LMB_MAP_OP_RESERVE = 1, + /** @LMB_MAP_OP_FREE: free memory */ + LMB_MAP_OP_FREE, + /** @LMB_MAP_OP_ADD: add memory */ + LMB_MAP_OP_ADD, +}; + /** * struct lmb_region - Description of one region * @base: Base address of the region diff --git a/lib/lmb.c b/lib/lmb.c index 7ca44591e1d..7534a231c99 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -23,10 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define MAP_OP_RESERVE (u8)0x1 -#define MAP_OP_FREE (u8)0x2 -#define MAP_OP_ADD (u8)0x3 - /* * The following low level LMB functions must not access the global LMB memory * map since they are also used to manage IOVA memory maps in iommu drivers like @@ -436,18 +432,13 @@ static bool lmb_should_notify(u32 flags) CONFIG_IS_ENABLED(EFI_LOADER); } -static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op, - u32 flags) +static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op, u32 flags) { u64 efi_addr; u64 pages; efi_status_t status; - if (op != MAP_OP_RESERVE && op != MAP_OP_FREE && op != MAP_OP_ADD) { - log_err("Invalid map update op received (%d)\n", op); - return -1; - } - if (!lmb_should_notify(flags)) return 0; @@ -456,7 +447,7 @@ static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op, efi_addr &= ~EFI_PAGE_MASK; status = efi_add_memory_map_pg(efi_addr, pages, - op == MAP_OP_RESERVE ? + op == LMB_MAP_OP_RESERVE ? EFI_BOOT_SERVICES_DATA : EFI_CONVENTIONAL_MEMORY, false); @@ -642,7 +633,7 @@ long lmb_add(phys_addr_t base, phys_size_t size) if (ret) return ret; - return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE); + return lmb_map_update_notify(base, size, LMB_MAP_OP_ADD, LMB_NONE); } long lmb_free_flags(phys_addr_t base, phys_size_t size, @@ -654,7 +645,7 @@ long lmb_free_flags(phys_addr_t base, phys_size_t size, if (ret < 0) return ret; - return lmb_map_update_notify(base, size, MAP_OP_FREE, flags); + return lmb_map_update_notify(base, size, LMB_MAP_OP_FREE, flags); } long lmb_free(phys_addr_t base, phys_size_t size) @@ -671,7 +662,7 @@ long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags) if (ret) return ret; - return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags); + return lmb_map_update_notify(base, size, LMB_MAP_OP_RESERVE, flags); } static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, @@ -712,7 +703,7 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, return 0; ret = lmb_map_update_notify(base, size, - MAP_OP_RESERVE, + LMB_MAP_OP_RESERVE, flags); if (ret) return ret; From 41d5734442c03439a534abfc2493d0ce9ca5000a Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 16 Feb 2025 12:12:40 +0100 Subject: [PATCH 64/68] lmb: move lmb_map_update_notify() to EFI When building with qemu_arm64_defconfig with CONFIG_CC_OPTIMIZE_FOR_DEBUG=y and CONFIG_EFI_LOADER=n an error undefined reference to efi_add_memory_map_pg occurs. Move the EFI dependent part of lmb_map_update_notify() to the EFI sub-system. Reported-by: Liya Huang <1425075683@qq.com> Acked-by: Liya Huang <1425075683@qq.com> Signed-off-by: Heinrich Schuchardt --- include/efi_loader.h | 15 +++++++++++++++ lib/efi_loader/efi_memory.c | 27 +++++++++++++++++++++++++++ lib/lmb.c | 31 +++---------------------------- 3 files changed, 45 insertions(+), 28 deletions(-) diff --git a/include/efi_loader.h b/include/efi_loader.h index dcae6a731a0..db3d20fd753 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1263,6 +1263,21 @@ efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int */ void efi_add_known_memory(void); +/** + * efi_map_update_notify() - notify EFI of memory map changes + * + * @addr: start of memory area + * @size: size of memory area + * @op: type of change + * Return: 0 if change could be processed + */ +#ifdef CONFIG_EFI_LOADER +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op); +#else +#define efi_map_update_notify(addr, size, op) (0) +#endif + /** * efi_load_option_dp_join() - join device-paths for load option * diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 1212772471e..11d092dc289 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -865,3 +865,30 @@ int efi_memory_init(void) return 0; } + +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op) +{ + u64 efi_addr; + u64 pages; + efi_status_t status; + + efi_addr = (uintptr_t)map_sysmem(addr, 0); + pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); + efi_addr &= ~EFI_PAGE_MASK; + + status = efi_add_memory_map_pg(efi_addr, pages, + op == LMB_MAP_OP_RESERVE ? + EFI_BOOT_SERVICES_DATA : + EFI_CONVENTIONAL_MEMORY, + false); + if (status != EFI_SUCCESS) { + log_err("LMB Map notify failure %lu\n", + status & ~EFI_ERROR_MASK); + return -1; + } + unmap_sysmem((void *)(uintptr_t)efi_addr); + + return 0; +} + diff --git a/lib/lmb.c b/lib/lmb.c index 7534a231c99..93fc1bea07c 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -426,37 +426,12 @@ long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size) static struct lmb lmb; -static bool lmb_should_notify(u32 flags) -{ - return !lmb.test && !(flags & LMB_NONOTIFY) && - CONFIG_IS_ENABLED(EFI_LOADER); -} - static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, enum lmb_map_op op, u32 flags) { - u64 efi_addr; - u64 pages; - efi_status_t status; - - if (!lmb_should_notify(flags)) - return 0; - - efi_addr = (uintptr_t)map_sysmem(addr, 0); - pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); - efi_addr &= ~EFI_PAGE_MASK; - - status = efi_add_memory_map_pg(efi_addr, pages, - op == LMB_MAP_OP_RESERVE ? - EFI_BOOT_SERVICES_DATA : - EFI_CONVENTIONAL_MEMORY, - false); - if (status != EFI_SUCCESS) { - log_err("%s: LMB Map notify failure %lu\n", __func__, - status & ~EFI_ERROR_MASK); - return -1; - } - unmap_sysmem((void *)(uintptr_t)efi_addr); + if (CONFIG_IS_ENABLED(EFI_LOADER) && + !lmb.test && !(flags & LMB_NONOTIFY)) + return efi_map_update_notify(addr, size, op); return 0; } From 5ce629db2512d70f298bc1d422fefad63a74c7f5 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 16 Feb 2025 12:12:41 +0100 Subject: [PATCH 65/68] efi_loader: make efi_add_memory_map_pg() static The function is only used in the efi_memory.c module. Reviewed-by: Ilias Apalodimas Signed-off-by: Heinrich Schuchardt --- include/efi_loader.h | 15 --------------- lib/efi_loader/efi_memory.c | 1 + 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/include/efi_loader.h b/include/efi_loader.h index db3d20fd753..1d75d97ebbc 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -852,21 +852,6 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, /* Adds a range into the EFI memory map */ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type); -/** - * efi_add_memory_map_pg() - add pages to the memory map - * - * @start: start address, must be a multiple of - * EFI_PAGE_SIZE - * @pages: number of pages to add - * @memory_type: type of memory added - * @overlap_conventional: region may only overlap free(conventional) - * memory - * Return: status code - */ -efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, - int memory_type, - bool overlap_conventional); - /* Called by board init to initialize the EFI drivers */ efi_status_t efi_driver_init(void); /* Called when a block device is added */ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 11d092dc289..6d00b186250 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -268,6 +268,7 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map, * memory * Return: status code */ +static efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, int memory_type, bool overlap_conventional) From 59fd62d71c6a04b3ab9db848414a7c386cfd2cfb Mon Sep 17 00:00:00 2001 From: Joao Marcos Costa Date: Wed, 19 Feb 2025 11:16:33 +0100 Subject: [PATCH 66/68] fs/squashfs: fix potential integer overflows The length of buffers used to read inode tables, directory tables, and reading a file are calculated as: number of blocks * block size, and such plain multiplication is prone to overflowing (thus unsafe). Replace it by __builtin_mul_overflow, i.e. safe math. Signed-off-by: Joao Marcos Costa --- fs/squashfs/sqfs.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index b9314019b1b..8fac6c6c5a9 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -719,6 +719,7 @@ static int sqfs_read_inode_table(unsigned char **inode_table) u32 src_len, dest_offset = 0; unsigned long dest_len = 0; bool compressed; + size_t buf_size; table_size = get_unaligned_le64(&sblk->directory_table_start) - get_unaligned_le64(&sblk->inode_table_start); @@ -728,7 +729,10 @@ static int sqfs_read_inode_table(unsigned char **inode_table) sblk->directory_table_start, &table_offset); /* Allocate a proper sized buffer (itb) to store the inode table */ - itb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + itb = malloc_cache_aligned(buf_size); if (!itb) return -ENOMEM; @@ -806,6 +810,7 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) u32 src_len, dest_offset = 0; unsigned long dest_len = 0; bool compressed; + size_t buf_size; *dir_table = NULL; *pos_list = NULL; @@ -818,7 +823,10 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) sblk->fragment_table_start, &table_offset); /* Allocate a proper sized buffer (dtb) to store the directory table */ - dtb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + dtb = malloc_cache_aligned(buf_size); if (!dtb) return -ENOMEM; @@ -1369,6 +1377,7 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, unsigned long dest_len; struct fs_dirent *dent; unsigned char *ipos; + size_t buf_size; *actread = 0; @@ -1573,7 +1582,10 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, table_offset = frag_entry.start - (start * ctxt.cur_dev->blksz); n_blks = DIV_ROUND_UP(table_size + table_offset, ctxt.cur_dev->blksz); - fragment = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + fragment = malloc_cache_aligned(buf_size); if (!fragment) { ret = -ENOMEM; From dbb9e136b8c01de581a08113ae6124f484b29362 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jan 2025 12:15:54 +0100 Subject: [PATCH 67/68] mmc: Fix size calculation for sector addressed MMC version 4 For eMMC v4 and newer that is smaller than 2 GiB, the JEDEC JESD84-B51 section 6.2.4 Configure partitions indicates that EXT_CSD SEC_COUNT should not be used to determine device size, and instead device size should be calculated from C_SIZE and C_SIZE_MULT. This is not exactly accurate, the 2 GiB limit is not a hard line, there are eMMC devices which are smaller than 2 GiB and still require device size to be determined from EXT_CSD SEC_COUNT. The hard line is instead OCR HCS bit, which indicates whether the device is byte or sector addressed, the former applies to most devices below 2 GiB, and the later applies mostly to devices above 2 GiB. However, there are a couple of devices which are smaller than 2 GiB and still set the OCR HCS bit to indicate they are sector addressed, and therefore the size calculation for those devices should also use EXT_CSD SEC_COUNT . Use mmc->high_capacity flag to discern the devices instead of arbitrary 2 GiB limit. The mmc->high_capacity flag reflects the OCR HCS bit state. Fixes: 639b7827d1ca ("mmc: fix the condition for MMC version 4") Signed-off-by: Marek Vasut --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 799586891af..31a72366206 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2376,7 +2376,7 @@ static int mmc_startup_v4(struct mmc *mmc) | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; capacity *= MMC_MAX_BLOCK_LEN; - if ((capacity >> 20) > 2 * 1024) + if (mmc->high_capacity) mmc->capacity_user = capacity; } From dc0ee458f1afae4cb5c8a7b2c875bb24ffdf71ca Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 24 Feb 2025 16:53:59 -0600 Subject: [PATCH 68/68] Prepare v2025.04-rc3 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index b32606b69f5..b4cac995b8e 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 03deea2af1a..b6ad7218614 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -72,7 +72,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.04-rc2 was released on Mon 10 February 2025. -.. * U-Boot v2025.04-rc3 was released on Mon 24 February 2025. +* U-Boot v2025.04-rc3 was released on Mon 24 February 2025. .. * U-Boot v2025.04-rc4 was released on Mon 10 March 2025.