diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b5c588c3363..9ed751af411 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb dtb-$(CONFIG_ARCH_APPLE) += \ t8103-j274.dtb \ diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi new file mode 100644 index 00000000000..7ad11e9faab --- /dev/null +++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + */ + +&cmu_top { + bootph-all; +}; + +&cmu_peri { + bootph-all; +}; + +&oscclk { + bootph-all; +}; + +&pinctrl_alive { + bootph-all; +}; + +&pmu_system_controller { + bootph-all; + samsung,uart-debug-1; +}; + +&serial_0 { + bootph-all; +}; + +&uart1_pins { + bootph-all; +}; + +&usi_uart { + bootph-all; +}; diff --git a/arch/arm/dts/exynos850-e850-96.dts b/arch/arm/dts/exynos850-e850-96.dts new file mode 100644 index 00000000000..f074df8982b --- /dev/null +++ b/arch/arm/dts/exynos850-e850-96.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include +#include +#include + +/ { + model = "WinLink E850-96 board"; + compatible = "winlink,e850-96", "samsung,exynos850"; + + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-supply = <®_usb_host_vbus>; + id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <µ_usb_det_pins>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + /* + * RAM: 4 GiB (eMCP): + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label = "yellow:user1"; + gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label = "yellow:user2"; + gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>; + color = ; + linux,default-trigger = "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label = "white:user3"; + gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SD; + linux,default-trigger = "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label = "yellow:wlan"; + gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label = "blue:bt"; + gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_BLUETOOTH; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + + reg_usb_host_vbus: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpa3 5 GPIO_ACTIVE_LOW>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ramoops@f0000000 { + compatible = "ramoops"; + reg = <0x0 0xf0000000 0x200000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x100000>; + pmsg-size = <0x20000>; + }; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible = "fixed-clock"; + clock-output-names = "rtcclk"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&cmu_hsi { + clocks = <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; +}; + +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup_pins: key-volup-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + micro_usb_det_pins: micro-usb-det-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usbdrd_phy { + status = "okay"; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&watchdog_cl0 { + status = "okay"; +}; + +&watchdog_cl1 { + status = "okay"; +}; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 45fc6bb024b..af00ee1db07 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -2,7 +2,7 @@ if ARCH_EXYNOS config BOARD_COMMON def_bool y - depends on !TARGET_SMDKV310 && !TARGET_ARNDALE + depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96 config SPI_BOOTING bool @@ -237,6 +237,22 @@ config TARGET_A3Y17LTE endchoice endif +if ARCH_EXYNOS9 + +choice + prompt "EXYNOS9 board select" + +config TARGET_E850_96 + bool "WinLink E850-96 board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS850 + +endchoice +endif + config SYS_SOC default "exynos" @@ -261,5 +277,6 @@ source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" +source "board/samsung/e850-96/Kconfig" endif diff --git a/board/samsung/e850-96/Kconfig b/board/samsung/e850-96/Kconfig new file mode 100644 index 00000000000..f891a906959 --- /dev/null +++ b/board/samsung/e850-96/Kconfig @@ -0,0 +1,16 @@ +if TARGET_E850_96 + +config EXYNOS850 + bool "Exynos850 SoC support" + default y + +config SYS_BOARD + default "e850-96" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "e850-96" + +endif diff --git a/board/samsung/e850-96/MAINTAINERS b/board/samsung/e850-96/MAINTAINERS new file mode 100644 index 00000000000..e8b9365eea8 --- /dev/null +++ b/board/samsung/e850-96/MAINTAINERS @@ -0,0 +1,9 @@ +WINLINK E850-96 BOARD +M: Sam Protsenko +S: Maintained +F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi +F: arch/arm/dts/exynos850-e850-96.dts +F: board/samsung/e850-96/ +F: configs/e850-96_defconfig +F: doc/board/samsung/e850-96.rst +F: include/configs/e850-96.h diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile new file mode 100644 index 00000000000..301c2233711 --- /dev/null +++ b/board/samsung/e850-96/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020, Linaro Limited +# Sam Protsenko + +obj-y := e850-96.o diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c new file mode 100644 index 00000000000..a00d81b5d4c --- /dev/null +++ b/board/samsung/e850-96/e850-96.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Linaro Limited + * Sam Protsenko + */ + +#include + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int board_init(void) +{ + return 0; +} diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig new file mode 100644 index 00000000000..bb41635ff78 --- /dev/null +++ b/configs/e850-96_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TEXT_BASE=0xf8800000 +CONFIG_SYS_MALLOC_LEN=0x81f000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ARCH_EXYNOS9=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 +CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96" +CONFIG_SYS_LOAD_ADDR=0x80000000 +# CONFIG_AUTOBOOT is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_NET is not set +CONFIG_CLK_EXYNOS850=y +# CONFIG_MMC is not set +CONFIG_SOC_SAMSUNG=y +CONFIG_EXYNOS_PMU=y +CONFIG_EXYNOS_USI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_SYSCON=y diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst new file mode 100644 index 00000000000..0cb95473e53 --- /dev/null +++ b/doc/board/samsung/e850-96.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sam Protsenko + +WinLink E850-96 board +===================== + +Overview +-------- + +WinLink's E850-96 board [1]_ is based on Samsung Exynos850 SoC and follows +96Boards Consumer Edition specification [2]_. That makes it possible to use +96Boards mezzanine boards [3]_ along with it. It's an open-hardware board and +the hardware design files [4]_ were published, along with the supported +software [5]_ and related documentation. + +U-Boot can be used on E850-96 instead of the original Samsung LittleKernel based +bootloader [6]_. Because FWBL1 [7]_ doesn't verify bootloader's signature, there +is no need to sign a U-Boot binary. That means U-Boot binary can be flashed into +``bootloader`` partition (instead of LittleKernel bootloader) and it will just +work. + +Because BL2 bootloader already sets up DRAM and runs the final bootloader +(U-Boot) from DRAM, there is no need in U-Boot SPL. It's enough to have only +U-Boot proper (``u-boot.bin``). + +Boot Flow +--------- + +The boot path for Exynos850 is shown on the figure below. + +.. image:: img/exynos850-boot-architecture.svg + :alt: Exynos850 SoC boot flow + +Legend: + +* ``BL0``: Boot ROM code +* ``BL1``: Software part of Boot ROM +* ``EPBL``: Exynos Primary Boot Loader +* ``BL2``: Initializes CMU and DRAM and runs the final bootloader +* ``Bootloader``: Final bootloader (e.g. U-Boot); also called BL33 in terms of + ARM boot flow +* ``EL3_MON``: EL3 monitor (trusted firmware, handles SMC calls); also called + BL31 in terms of ARM boot flow +* ``LDFW``: Loadable Firmware + +Build Procedure +--------------- + +.. warning:: + At the moment both eMMC and USB features are not enabled in U-Boot. Flashing + U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can + be used then to perform USB boot and flash LittleKernel bootloader binary [7]_ + to unbrick and revive the board. Flashing U-Boot binary might be helpful for + developers or anybody who want to check current state of U-Boot enablement on + E850-96 (which is mostly serial console and related blocks). + +Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain): + +.. prompt:: bash $ + + export PATH=/bin:$PATH + export CROSS_COMPILE= + make e850-96_defconfig + make + +Boot E850-96 board into fastboot mode as described in board software doc [9]_, +and flash U-Boot binary into ``bootloader`` eMMC partition: + +.. prompt:: bash $ + + fastboot flash bootloader u-boot.bin + fastboot reboot + +U-Boot will boot up to the shell. + +References +---------- + +.. [1] https://www.96boards.org/product/e850-96b/ +.. [2] https://www.96boards.org/products/ce/ +.. [3] https://www.96boards.org/products/mezzanine/ +.. [4] https://www.96boards.org/documentation/consumer/e850-96b/hardware-docs/ +.. [5] https://gitlab.com/Linaro/96boards/e850-96/ +.. [6] https://gitlab.com/Linaro/96boards/e850-96/lk +.. [7] https://gitlab.com/Linaro/96boards/e850-96/images +.. [8] https://gitlab.com/Linaro/96boards/e850-96/tools/dltool +.. [9] https://gitlab.com/Linaro/96boards/e850-96/doc diff --git a/doc/board/samsung/img/exynos850-boot-architecture.svg b/doc/board/samsung/img/exynos850-boot-architecture.svg new file mode 100644 index 00000000000..c6e850407b4 --- /dev/null +++ b/doc/board/samsung/img/exynos850-boot-architecture.svg @@ -0,0 +1,1283 @@ + + + + + + + + + + + + + + + Secure World + + + + Secure World + + + + + + + + + + + + + + + Non-Secure World + + + + Non-SecureWorld + + + + + + + + + +Booting Period + + + + Booting Period + + + + + + + + + + + BL0 + + + + BL0 + + + + + + + + + + + BL1 + + + + BL1 + + + + + + + + + + + + + EPBL + + + + EPBL + + + + + + + + + + + + + BL2 + + + + BL2 + + + + + + + + + + + + + Bootloader + + + + Bootloader + + + + + + + + + + + + + EL3_MON + + + + EL3_MON + + + + + + + + + + + Linux + + + + Linux + + + + + + + + + + Android + + + + + Android + + + + + + + + + Secure App + + + + Secure App + + + + + + + + + + + Secure OS + + + + Secure OS + + + + + + + + + LDFW + + + + LDFW + + + + + + + + + + iROM + + + + + iROM + + + + + + + + + + iRAM + + + + + iRAM + + + + + + + + + + DRAM + + + + + DRAM + + + + + + + + + + + + EL0 + + + + EL0 + + + + + + + + + EL1 + + + + EL1 + + + + + + + + + EL3 + + + + EL3 + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst index 971805e2016..a1c9636b050 100644 --- a/doc/board/samsung/index.rst +++ b/doc/board/samsung/index.rst @@ -7,3 +7,4 @@ Samsung :maxdepth: 2 axy17lte + e850-96 diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h new file mode 100644 index 00000000000..4607b3089b2 --- /dev/null +++ b/include/configs/e850-96.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020, Linaro Limited + * Sam Protsenko + * + * Configuration for E850-96 board. + */ + +#ifndef __E850_96_H +#define __E850_96_H + +#endif /* __E850_96_H */