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clk: imx8m: register ARM A53 core clock

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Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing
for enabling the 'cpu' command, which depends on this to print CPU core
frequency.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This commit is contained in:
Hou Zhiqiang 2024-08-01 11:59:46 +08:00 • committed by Fabio Estevam
parent ecc5dd777e
commit 3cdcdcecac
3 changed files with 24 additions and 0 deletions
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8
drivers/clk/imx/clk-imx8mm.c
View file

@ -21,6 +21,8 @@ static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@ -417,6 +419,12 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
#endif
clk_dm(IMX8MM_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
imx8mm_arm_core_sels,
ARRAY_SIZE(imx8mm_arm_core_sels),
CLK_IS_CRITICAL));
return 0;
}

8
drivers/clk/imx/clk-imx8mn.c
View file

@ -23,6 +23,8 @@ static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@ -403,6 +405,12 @@ static int imx8mn_clk_probe(struct udevice *dev)
imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
#endif
clk_dm(IMX8MN_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
imx8mn_arm_core_sels,
ARRAY_SIZE(imx8mn_arm_core_sels),
CLK_IS_CRITICAL));
return 0;
}

8
drivers/clk/imx/clk-imx8mp.c
View file

@ -21,6 +21,8 @@ static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_se
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@ -354,6 +356,12 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
clk_dm(IMX8MP_CLK_ARM,
imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
imx8mp_arm_core_sels,
ARRAY_SIZE(imx8mp_arm_core_sels),
CLK_IS_CRITICAL));
return 0;
}