Merge branch 'next'

.azure-pipelines.yml

@@ -2,7 +2,7 @@ variables:
   windows_vm: windows-2022
   ubuntu_vm: ubuntu-24.04
   macos_vm: macOS-14
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240911.1-08Dec2024
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
@@ -245,8 +245,6 @@ stages:
           ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
           ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
           ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
-          grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
-          grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
           if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
               wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
               export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
@@ -268,8 +266,8 @@ stages:
           fi
           pip install -r tools/buildman/requirements.txt
           tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
-          cp ~/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
-          cp ~/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
+          cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
+          cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
           cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
           cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
           cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi

.gitlab-ci.yml

@@ -1,17 +1,25 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 variables:
-  DEFAULT_TAG: ""
+  DEFAULT_ALL_TAG: "all"
+  DEFAULT_ARM64_TAG: "arm64"
+  DEFAULT_AMD64_TAG: "amd64"
+  DEFAULT_FAST_AMD64_TAG: "fast amd64"
   MIRROR_DOCKER: docker.io
   SJG_LAB: ""
+  PLATFORM: linux/amd64,linux/arm64
 
 default:
   tags:
-    - ${DEFAULT_TAG}
+    - ${DEFAULT_ALL_TAG}
+
+workflow:
+  rules:
+    - when: always
 
 # Grab our configured image.  The source for this is found
 # in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240911.1-08Dec2024
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -23,8 +31,7 @@ stages:
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
   stage: test.py
   retry: 2 # QEMU may be too slow, etc.
-  rules:
-    - when: always
+  needs: [ "Run binman, buildman, dtoc, Kconfig and patman testsuites" ]
   before_script:
     # Clone uboot-test-hooks
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
@@ -34,8 +41,6 @@ stages:
     - ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
     - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
     - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
-    - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
-    - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
     - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
         wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
         export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
@@ -62,8 +67,8 @@ stages:
       fi
     - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
         --board ${TEST_PY_BD} ${OVERRIDE}
-    - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
-    - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
+    - cp /opt/grub/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
+    - cp /opt/grub/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
     - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
     - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
     - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
@@ -103,54 +108,20 @@ stages:
       junit: results.xml
     expire_in: 1 week
 
-.world_build:
+build all platforms in a single job:
   stage: world build
-  rules:
-    - when: always
-
-build all 32bit ARM platforms:
-  extends: .world_build
+  dependencies: []
+  parallel:
+    matrix:
+      - HOST: "arm64"
+      - HOST: "fast amd64"
+  tags:
+    - ${HOST}
   script:
     - ret=0;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
       pip install -r tools/buildman/requirements.txt;
-      ./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
-        exit $ret;
-      fi;
-
-build all 64bit ARM platforms:
-  extends: .world_build
-  script:
-    - virtualenv -p /usr/bin/python3 /tmp/venv
-    - . /tmp/venv/bin/activate
-    - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
-      pip install -r tools/buildman/requirements.txt;
-      ./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
-        exit $ret;
-      fi;
-
-build all PowerPC platforms:
-  extends: .world_build
-  script:
-    - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
-      ./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
-        exit $ret;
-      fi;
-
-build all other platforms:
-  extends: .world_build
-  script:
-    - ret=0;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
-      ./tools/buildman/buildman -o /tmp -PEWM -x arm,powerpc || ret=$?;
+      ./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
         exit $ret;
@@ -158,8 +129,6 @@ build all other platforms:
 
 .testsuites:
   stage: testsuites
-  rules:
-    - when: always
 
 check for new CONFIG symbols outside Kconfig:
   extends: .testsuites
@@ -199,6 +168,8 @@ Build tools-only and envtools:
 
 Run binman, buildman, dtoc, Kconfig and patman testsuites:
   extends: .testsuites
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   script:
     - git config --global user.name "GitLab CI Runner";
       git config --global user.email trini@konsulko.com;
@@ -258,22 +229,30 @@ Check packing of Python tools:
 
 # Test sandbox with test.py
 sandbox test.py:
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   variables:
     TEST_PY_BD: "sandbox"
   <<: *buildman_and_testpy_dfn
 
 sandbox with clang test.py:
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   variables:
     TEST_PY_BD: "sandbox"
     OVERRIDE: "-O clang-17"
   <<: *buildman_and_testpy_dfn
 
 sandbox64 test.py:
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   variables:
     TEST_PY_BD: "sandbox64"
   <<: *buildman_and_testpy_dfn
 
 sandbox64 with clang test.py:
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   variables:
     TEST_PY_BD: "sandbox64"
     OVERRIDE: "-O clang-17"
@@ -328,6 +307,8 @@ evb-ast2600 test.py:
   <<: *buildman_and_testpy_dfn
 
 sandbox_flattree test.py:
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   variables:
     TEST_PY_BD: "sandbox_flattree"
   <<: *buildman_and_testpy_dfn
@@ -452,6 +433,8 @@ qemu-xtensa-dc233c test.py:
   variables:
     TEST_PY_BD: "qemu-xtensa-dc233c"
     TEST_PY_TEST_SPEC: "not sleep and not efi"
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   <<: *buildman_and_testpy_dfn
 
 r2dplus_i82557c test.py:
@@ -515,6 +498,8 @@ xtfpga test.py:
     TEST_PY_BD: "xtfpga"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
+  tags:
+    - ${DEFAULT_AMD64_TAG}
   <<: *buildman_and_testpy_dfn
 
 coreboot test.py:
@@ -532,6 +517,7 @@ coreboot test.py:
     - if: $SJG_LAB != "1"
       when: manual
       allow_failure: true
+  dependencies: []
   tags: [ 'lab' ]
   script:
     - if [[ -z "${SJG_LAB}" ]]; then

Kconfig

@@ -596,27 +596,6 @@ config SYS_MEM_TOP_HIDE
 	  WARNING: Please make sure that this value is a multiple of the OS
 	  page size.
 
-config SYS_HAS_SRAM
-	bool
-	default y if TARGET_PIC32MZDASK
-	default y if TARGET_DEVKIT8000
-	help
-	  Enable this to allow support for the on board SRAM.
-	  SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
-	  SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
-
-config SYS_SRAM_BASE
-	hex
-	default 0x80000000 if TARGET_PIC32MZDASK
-	default 0x40200000 if TARGET_DEVKIT8000
-	default 0x0
-
-config SYS_SRAM_SIZE
-	hex
-	default 0x00080000 if TARGET_PIC32MZDASK
-	default 0x10000 if TARGET_DEVKIT8000
-	default 0x0
-
 config SYS_MONITOR_LEN
 	int "Maximum size in bytes reserved for U-Boot in memory"
 	default 1048576 if X86

MAINTAINERS

@@ -1736,6 +1736,11 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
 F:	drivers/mtd/ubi/
 
+UFETCH
+M:	Caleb Connolly <caleb.connolly@linaro.org>
+S:	Maintained
+F:	cmd/ufetch.c
+
 UFS
 M:	Neil Armstrong <neil.armstrong@linaro.org>
 M:	Bhupesh Sharma <bhupesh.linux@gmail.com>

Makefile

@@ -1148,13 +1148,6 @@ ifeq ($(CONFIG_OF_EMBED)$(CONFIG_EFI_APP),y)
 	@echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
 	@echo >&2 "See doc/develop/devicetree/control.rst for more info."
 	@echo >&2 "===================================================="
-endif
-ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
-	@echo >&2 "===================== WARNING ======================"
-	@echo >&2 "This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate"
-	@echo >&2 "to binman instead, to avoid the proliferation of"
-	@echo >&2 "arch-specific scripts with no tests."
-	@echo >&2 "===================================================="
 endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
@@ -1392,12 +1385,21 @@ endif
 default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
 endif
 
+binman_dtb := $(shell echo $(CONFIG_BINMAN_DTB))
+ifeq ($(strip $(binman_dtb)),)
+ifeq ($(CONFIG_OF_EMBED),y)
+binman_dtb = ./dts/dt.dtb
+else
+binman_dtb = ./u-boot.dtb
+endif
+endif
+
 quiet_cmd_binman = BINMAN  $@
 cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
-		build -u -d u-boot.dtb -O . -m \
+		build -u -d $(binman_dtb) -O . -m \
 		--allow-missing --fake-ext-blobs \
 		$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
@@ -1427,17 +1429,6 @@ OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
 u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
 	$(call if_changed,objcopy)
 
-# Boards with more complex image requirements can provide an .its source file
-# or a generator script
-# NOTE: Please do not use this. We are migrating away from Makefile rules to use
-# binman instead.
-ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
-U_BOOT_ITS := u-boot.its
-$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
-	$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
-	$(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
-endif
-
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \

api/api_platform-powerpc.c

@@ -43,7 +43,6 @@ int platform_sys_info(struct sys_info *si)
 
 	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
 	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
-	platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
 
 	return 1;
 }

arch/Kconfig

@@ -37,6 +37,14 @@ config 32BIT
 
 config 64BIT
 	bool
+	help
+	  Indicates that U-Boot proper will be built for a 64 bit
+	  architecture.
+
+config SPL_64BIT
+	bool
+	help
+	  Indicates that SPL will be built for a 64 bit architecture.
 
 config SYS_CACHELINE_SIZE
 	int

arch/arm/Kconfig

@@ -7,6 +7,7 @@ config SYS_ARCH
 config ARM64
 	bool
 	select 64BIT
+	select SPL_64BIT if SPL
 	select PHYS_64BIT
 	select SYS_CACHE_SHIFT_6
 	imply SPL_SEPARATE_BSS
@@ -1177,7 +1178,6 @@ config ARCH_SUNXI
 	select SUNXI_GPIO
 	select SYS_NS16550
 	select SYS_THUMB_BUILD if !ARM64
-	select USB if DISTRO_DEFAULTS
 	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
 	select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
 	select SPL_USE_TINY_PRINTF if SPL
@@ -1203,6 +1203,7 @@ config ARCH_SUNXI
 	imply SYSRESET
 	imply SYSRESET_WATCHDOG
 	imply SYSRESET_WATCHDOG_AUTO
+	imply USB
 	imply USB_GADGET
 	imply WDT
 
@@ -1324,6 +1325,7 @@ config ARCH_ZYNQMP_R5
 config ARCH_ZYNQMP
 	bool "Xilinx ZynqMP based platform"
 	select ARM64
+	select BINMAN
 	select CLK
 	select DM
 	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART

arch/arm/cpu/armv8/cache_v8.c

@@ -825,7 +825,7 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-	uint32_t sctlr;
+	unsigned long sctlr;
 
 	sctlr = get_sctlr();
 

arch/arm/cpu/armv8/cpu.c

@@ -94,3 +94,8 @@ void armv8_setup_psci(void)
 	secure_ram_addr(psci_arch_init)();
 }
 #endif
+
+void allow_unaligned(void)
+{
+	set_sctlr(get_sctlr() & ~CR_A);
+}

arch/arm/dts/Makefile

@@ -275,6 +275,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-mini-qspi-x1-stacked.dtb		\
 	zynqmp-mini-qspi-x2-single.dtb		\
 	zynqmp-mini-qspi-x2-stacked.dtb		\
+	zynqmp-binman-mini.dtb			\
 	zynqmp-sc-revB.dtb			\
 	zynqmp-sc-revC.dtb			\
 	zynqmp-sm-k24-revA.dtb			\
@@ -320,6 +321,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman.dtb
 
 zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo
 zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo
@@ -370,6 +372,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman-som.dtb
 
 dtb-$(CONFIG_ARCH_VERSAL) += \
 	versal-mini.dtb \
@@ -936,8 +939,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
 	fsl-imx8qxp-mek.dtb \
-	imx8-deneb.dtb \
-	imx8-giedi.dtb
+	imx8-capricorn-cxg3.dtb \
 
 dtb-$(CONFIG_ARCH_IMX8ULP) += \
 	imx8ulp-evk.dtb
@@ -976,10 +978,6 @@ dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
 	imxrt1020-evk.dtb \
 	imxrt1170-evk.dtb \
 
-ifdef CONFIG_RCAR_64
-DTC_FLAGS += -R 4 -p 0x1000
-endif
-
 dtb-$(CONFIG_RZA1) += \
 	r7s72100-gr-peach.dtb
 
@@ -1157,14 +1155,11 @@ dtb-$(CONFIG_STM32MP25X) += \
 	stm32mp257f-ev1.dtb
 
 dtb-$(CONFIG_SOC_K3_AM654) += \
-	k3-am654-base-board.dtb \
-	k3-am654-r5-base-board.dtb \
-	k3-am654-icssg2.dtbo
+	k3-am654-r5-base-board.dtb
 
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
 			      k3-j7200-r5-common-proc-board.dtb \
 			      k3-j721e-r5-sk.dtb \
-			      k3-j721e-beagleboneai64.dtb \
 			      k3-j721e-r5-beagleboneai64.dtb
 
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
@@ -1184,7 +1179,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \
 			      k3-am625-verdin-r5.dtb \
 			      k3-am625-r5-phycore-som-2gb.dtb
 
-dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb
+dtb-$(CONFIG_SOC_K3_AM62A7) += \
+	k3-am62a7-r5-sk.dtb \
+	k3-am62a7-r5-phycore-som-2gb.dtb
 
 dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
 

arch/arm/dts/imx8-capricorn-cxg3.dts

@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Siemens AG
+ */
+
+#include "imx8-capricorn.dtsi"
+
+/ {
+	model = "Siemens CXG3";
+
+	leds_default: leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		run {
+			label = "run";
+			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		flt {
+			label = "flt";
+			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		svc {
+			label = "svc";
+			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com1_tx {
+			label = "com1-tx";
+			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com1_rx {
+			label = "com1-rx";
+			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com2_tx {
+			label = "com2-tx";
+			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		com2_rx {
+			label = "com2-rx";
+			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		cloud {
+			label = "cloud";
+			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		wlan {
+			label = "wlan";
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		apps {
+			label = "apps";
+			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg2 {
+			label = "dbg2";
+			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg3 {
+			label = "dbg3";
+			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		dbg4 {
+			label = "dbg4";
+			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&iomuxc {
+	pinctrl-0 = <&pinctrl_gpio_keys>;
+
+	muxcgrp: imx8qxp-som {
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
+			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
+			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
+			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
+			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
+			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
+			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
+			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
+			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
+			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
+			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
+			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
+			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
+			>;
+		};
+	};
+
+	pinctrl_gpio_keys: gpiokeysgrp {
+		fsl,pins = <
+		SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021
+		>;
+	};
+};

arch/arm/dts/imx8-capricorn-u-boot.dtsi

@@ -6,130 +6,133 @@
 #include "imx8qxp-u-boot.dtsi"
 
 &{/imx8qx-pm} {
+	bootph-all;
+};
 
-	bootph-pre-ram;
+&A35_0 {
+        bootph-all;
 };
 
 &mu {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &clk {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &iomuxc {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio0 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio1 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio2 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio3 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio4 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio5 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio6 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_lsio_gpio7 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_dma {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_dma_lpuart0 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_dma_lpuart2 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_conn {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_conn_sdch0 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_conn_sdch1 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pd_conn_sdch2 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio0 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio1 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio2 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio3 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio4 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio5 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio6 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &gpio7 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &lpuart0 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &lpuart2 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &usdhc1 {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &usdhc2 {
-	bootph-pre-ram;
+	bootph-all;
 };

arch/arm/dts/imx8-capricorn.dtsi

@@ -9,124 +9,25 @@
 /dts-v1/;
 
 #include "fsl-imx8qxp.dtsi"
-#include "imx8qxp-capricorn-u-boot.dtsi"
+#include "imx8-capricorn-u-boot.dtsi"
 
 / {
-	model = "Siemens Giedi";
-	compatible = "siemens,capricorn", "fsl,imx8qxp";
-
 	chosen {
 		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
 		stdout-path = &lpuart2;
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_leds>;
-
-		run {
-			label = "run";
-			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		flt {
-			label = "flt";
-			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		svc {
-			label = "svc";
-			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com1_tx {
-			label = "com1-tx";
-			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com1_rx {
-			label = "com1-rx";
-			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com2_tx {
-			label = "com2-tx";
-			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		com2_rx {
-			label = "com2-rx";
-			gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		cloud {
-			label = "cloud";
-			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		wlan {
-			label = "wlan";
-			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg1 {
-			label = "dbg1";
-			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg2 {
-			label = "dbg2";
-			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg3 {
-			label = "dbg3";
-			gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
-
-		dbg4 {
-			label = "dbg4";
-			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
-			default-state = "on";
-		};
+	/* create device for u-boot wdt command */
+	scu-wdt {
+		compatible = "siemens,scu-wdt";
 	};
+
 };
 
 &iomuxc {
 	pinctrl-names = "default";
 
 	muxcgrp: imx8qxp-som {
-		pinctrl_gpio_leds: gpioledsgrp {
-			fsl,pins = <
-			SC_P_ESAI0_FST_LSIO_GPIO0_IO01		0x06000021
-			SC_P_ESAI0_TX0_LSIO_GPIO0_IO04		0x06000021
-			SC_P_SAI0_TXC_LSIO_GPIO0_IO26		0x06000021
-			SC_P_SAI1_RXD_LSIO_GPIO0_IO29		0x06000021
-			SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17	0x06000021
-			SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18	0x06000021
-			SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17	0x06000021
-			SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18	0x06000021
-			SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19	0x06000021
-			SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000021
-			SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x06000021
-			SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x06000021
-			SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000021
-			>;
-		};
-
 		pinctrl_lpi2c0: lpi2c0grp {
 			fsl,pins = <
 			SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x0C000020

arch/arm/dts/imx8-deneb.dts

@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-capricorn.dtsi"
-
-/ {
-	model = "Siemens Deneb";
-};

arch/arm/dts/imx8-giedi.dts

@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2019 Siemens AG
- */
-
-#include "imx8qxp-capricorn.dtsi"
-
-/ {
-	model = "Siemens Giedi";
-};

arch/arm/dts/imx8mm-phyboard-polis-rdk-u-boot.dtsi

@@ -14,6 +14,10 @@
 	};
 };
 
+&pinctrl_i2c1 {
+	bootph-pre-ram;
+};
+
 &pinctrl_uart3 {
 	bootph-pre-ram;
 };
@@ -54,6 +58,10 @@
 	bootph-pre-ram;
 };
 
+&i2c1 {
+	bootph-pre-ram;
+};
+
 &uart3 {
 	bootph-pre-ram;
 };

arch/arm/dts/imx8mp-dhcom-u-boot.dtsi

@@ -9,6 +9,8 @@
 	aliases {
 		eeprom0 = &eeprom0;
 		eeprom1 = &eeprom1;
+		eeprom0wl = &eeprom0wl;
+		eeprom1wl = &eeprom1wl;
 		mmc0 = &usdhc2;	/* MicroSD */
 		mmc1 = &usdhc3;	/* eMMC */
 		mmc2 = &usdhc1;	/* SDIO */

arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi

@@ -4,15 +4,6 @@
  */
 #include "imx8mp-venice-gw702x-u-boot.dtsi"
 
-&gpio1 {
-	tpm_rst {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_HIGH>;
-		line-name = "tpm_rst#";
-	};
-};
-
 &gpio4 {
 	dio_1 {
 		gpio-hog;
@@ -21,6 +12,13 @@
 		line-name = "dio1";
 	};
 
+	tpm_rst {
+		gpio-hog;
+		output-high;
+		gpios = <9 GPIO_ACTIVE_HIGH>;
+		line-name = "tpm_rst#";
+	};
+
 	dio_0 {
 		gpio-hog;
 		input;

arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi

@@ -4,15 +4,6 @@
  */
 #include "imx8mp-venice-gw702x-u-boot.dtsi"
 
-&gpio1 {
-	tpm_rst {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_HIGH>;
-		line-name = "tpm_rst#";
-	};
-};
-
 &gpio4 {
 	dio_1 {
 		gpio-hog;
@@ -21,6 +12,13 @@
 		line-name = "dio1";
 	};
 
+	tpm_rst {
+		gpio-hog;
+		output-high;
+		gpios = <9 GPIO_ACTIVE_HIGH>;
+		line-name = "tpm_rst#";
+	};
+
 	dio_0 {
 		gpio-hog;
 		input;

arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi

@@ -10,15 +10,6 @@
 	reset-post-delay-us = <300000>;
 };
 
-&gpio1 {
-	tpm_rst {
-		gpio-hog;
-		output-high;
-		gpios = <11 GPIO_ACTIVE_HIGH>;
-		line-name = "tpm_rst#";
-	};
-};
-
 &gpio4 {
 	dio_1 {
 		gpio-hog;
@@ -27,6 +18,13 @@
 		line-name = "dio1";
 	};
 
+	tpm_rst {
+		gpio-hog;
+		output-high;
+		gpios = <9 GPIO_ACTIVE_HIGH>;
+		line-name = "tpm_rst#";
+	};
+
 	dio_0 {
 		gpio-hog;
 		input;

arch/arm/dts/imx8qxp-u-boot.dtsi

@@ -120,6 +120,7 @@
 		};
 	};
 
+#ifdef CONFIG_XPL_BUILD
 	imx-boot {
 		filename = "flash.bin";
 		pad-byte = <0x00>;
@@ -130,4 +131,5 @@
 			type = "blob-ext";
 		};
 	};
+#endif
 };

arch/arm/dts/imx91-11x11-evk-u-boot.dtsi

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx91-u-boot.dtsi"
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		bootph-pre-ram;
+		bootph-some-ram;
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0} {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&aips1 {
+	bootph-pre-ram;
+	bootph-all;
+};
+
+&aips2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&aips3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&iomuxc {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_usdhc2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpuart1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&usdhc2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c1 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c2 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&pinctrl_lpi2c3 {
+	bootph-pre-ram;
+	bootph-some-ram;
+};
+
+&fec {
+	compatible = "fsl,imx91-fec", "fsl,imx93-fec", "fsl,imx8mq-fec";
+	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <15>;
+	phy-reset-post-delay = <100>;
+};
+
+&ethphy1 {
+	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+	reset-assert-us = <15000>;
+	reset-deassert-us = <100000>;
+};
+
+&s4muap {
+	bootph-pre-ram;
+	bootph-some-ram;
+	status = "okay";
+};
+
+&clk {
+	bootph-all;
+	bootph-pre-ram;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+	/delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&osc_24m {
+	bootph-all;
+	bootph-pre-ram;
+};
+
+&clk_ext1 {
+	bootph-all;
+	bootph-pre-ram;
+};

arch/arm/dts/imx91-u-boot.dtsi

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
+ */
+
+/ {
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&A55_0 {
+	clocks = <&clk IMX93_CLK_A55_SEL>;
+};
+
+&binman {
+	u-boot-spl-ddr {
+		align = <4>;
+		align-size = <4>;
+		filename = "u-boot-spl-ddr.bin";
+		pad-byte = <0xff>;
+
+		u-boot-spl {
+			align-end = <4>;
+			filename = "u-boot-spl.bin";
+		};
+
+		ddr-1d-imem-fw {
+			filename = "lpddr4_imem_1d_v202201.bin";
+			align-end = <4>;
+			type = "blob-ext";
+		};
+
+		ddr-1d-dmem-fw {
+			filename = "lpddr4_dmem_1d_v202201.bin";
+			align-end = <4>;
+			type = "blob-ext";
+		};
+
+		ddr-2d-imem-fw {
+			filename = "lpddr4_imem_2d_v202201.bin";
+			align-end = <4>;
+			type = "blob-ext";
+		};
+
+		ddr-2d-dmem-fw {
+			filename = "lpddr4_dmem_2d_v202201.bin";
+			align-end = <4>;
+			type = "blob-ext";
+		};
+	};
+
+	spl {
+		filename = "spl.bin";
+
+		mkimage {
+			args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x204A0000";
+
+			blob {
+				filename = "u-boot-spl-ddr.bin";
+			};
+		};
+	};
+
+	u-boot-container {
+		filename = "u-boot-container.bin";
+
+		mkimage {
+			args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
+
+			blob {
+				filename = "u-boot.bin";
+			};
+		};
+	};
+
+	imx-boot {
+		filename = "flash.bin";
+		pad-byte = <0x00>;
+
+		spl: blob-ext@1 {
+			filename = "spl.bin";
+			offset = <0x0>;
+			align-size = <0x400>;
+			align = <0x400>;
+		};
+
+		uboot: blob-ext@2 {
+			filename = "u-boot-container.bin";
+		};
+	};
+};

arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi

@@ -2,15 +2,22 @@
 /*
  * Copyright (C) 2023 PHYTEC Messtechnik GmbH
  * Christoph Stoidner <c.stoidner@phytec.de>
+ * Copyright (C) 2024 PHYTEC Messtechnik GmbH
  *
  * Product homepage:
- * phyBOARD-Segin carrier board is reused for the i.MX93 design.
- * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
+   https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/
  */
 
 #include "imx93-u-boot.dtsi"
 
 / {
+	/*
+	 * The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as
+	 * reference, but does only make use of its SoM (phyCORE) contained
+	 * periphery.
+	 */
+	model = "PHYTEC phyCORE-i.MX93";
+
 	wdt-reboot {
 		compatible = "wdt-reboot";
 		wdt = <&wdog3>;
@@ -139,6 +146,13 @@
 &usdhc1 {
 	bootph-pre-ram;
 	bootph-some-ram;
+	/*
+	 * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
+	 */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 };
 
 &usdhc2 {
@@ -215,6 +229,48 @@
 			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x31e
 		>;
 	};
+
+	/*
+	 * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
+	 * are added to imx93-phycore-som.dtsi
+	 */
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		bootph-pre-ram;
+		bootph-some-ram;
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
+		>;
+	};
+
+	/* need to config the SION for data and cmd pad, refer to ERR052021 */
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		bootph-pre-ram;
+		bootph-some-ram;
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
+			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
+		>;
+	};
 };
 
 &lpi2c3 {
@@ -305,4 +361,13 @@
 			};
 		};
 	};
+
+	eeprom@50 {
+		bootph-pre-ram;
+		bootph-some-ram;
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+		vcc-supply = <&buck4>;
+	};
 };

arch/arm/dts/k3-am62-lp-sk-u-boot.dtsi

@@ -5,13 +5,3 @@
  */
 
 #include "k3-am62-lp-sk-binman.dtsi"
-
-/ {
-	chosen {
-		tick-timer = &main_timer0;
-	};
-};
-
-&main_timer0 {
-	clock-frequency = <25000000>;
-};

arch/arm/dts/k3-am62-r5-lp-sk.dts

@@ -12,6 +12,7 @@
 
 / {
 	aliases {
+		tick-timer = &main_timer0;
 		remoteproc0 = &sysctrler;
 		remoteproc1 = &a53_0;
 		serial0 = &wkup_uart0;
@@ -72,6 +73,14 @@
 	};
 };
 
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
 	status = "okay";

arch/arm/dts/k3-am625-phycore-som-binman.dtsi

@@ -137,6 +137,20 @@
 		};
 	};
 };
+
+#include "k3-binman-capsule-r5.dtsi"
+
+&capsule_tiboot3 {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am625-r5-phycore-som-2gb.dtb PHYCORE_AM62X_TIBOOT3
+		 */
+		image-guid = "C7D64D6D-10B2-54BC-A3BF-06A9DC3653D9";
+	};
+};
+
 #endif /* CONFIG_TARGET_PHYCORE_AM62X_R5 */
 
 #ifdef CONFIG_TARGET_PHYCORE_AM62X_A53
@@ -460,4 +474,29 @@
 		};
 	};
 };
+
+#include "k3-binman-capsule.dtsi"
+
+&capsule_tispl {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am625-phyboard-lyra-rdk.dtb PHYCORE_AM62X_SPL
+		 */
+		image-guid = "09841C3F-F177-5D57-B1F6-754D92879205";
+	};
+};
+
+&capsule_uboot {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am625-phyboard-lyra-rdk.dtb PHYCORE_AM62X_UBOOT
+		 */
+		image-guid = "D11A9016-515E-503A-8872-3FF65384D0C4";
+	};
+};
+
 #endif /* CONFIG_TARGET_PHYCORE_AM62X_A53 */

arch/arm/dts/k3-am625-r5-sk.dts

@@ -12,6 +12,7 @@
 
 / {
 	aliases {
+		tick-timer = &main_timer0;
 		remoteproc0 = &sysctrler;
 		remoteproc1 = &a53_0;
 		serial0 = &wkup_uart0;
@@ -70,6 +71,14 @@
 	};
 };
 
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
 	status = "okay";

arch/arm/dts/k3-am625-sk-u-boot.dtsi

@@ -6,16 +6,6 @@
 
 #include "k3-am625-sk-binman.dtsi"
 
-/ {
-	chosen {
-		tick-timer = &main_timer0;
-	};
-};
-
-&main_timer0 {
-	clock-frequency = <25000000>;
-};
-
 &main_bcdma {
 	reg = <0x00 0x485c0100 0x00 0x100>,
 	      <0x00 0x4c000000 0x00 0x20000>,

arch/arm/dts/k3-am62a-phycore-som-binman.dtsi

@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Based on k3-am62a-sk-binman.dtsi
+ *
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ */
+
+#include "k3-binman.dtsi"
+
+#ifdef CONFIG_TARGET_PHYCORE_AM62AX_R5
+
+&rcfg_yaml_tifs {
+	config = "tifs-rm-cfg.yaml";
+};
+
+&binman {
+	tiboot3-am62ax-hs-phycore-som.bin {
+		filename = "tiboot3-am62ax-hs-phycore-som.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				<&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62ax-hs-fs-phycore-som.bin {
+		filename = "tiboot3-am62ax-hs-fs-phycore-som.bin";
+		symlink = "tiboot3.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c3a800>;
+		};
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-am62ax-gp-phycore-som.bin {
+		filename = "tiboot3-am62ax-gp-phycore-som.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+			combined;
+			dm-data;
+			content-sbl = <&u_boot_spl_unsigned>;
+			load = <0x43c00000>;
+			content-sysfw = <&ti_fs_gp>;
+			load-sysfw = <0x40000>;
+			content-sysfw-data = <&combined_tifs_cfg_gp>;
+			load-sysfw-data = <0x67000>;
+			content-dm-data = <&combined_dm_cfg_gp>;
+			load-dm-data = <0x43c3a800>;
+			sw-rev = <1>;
+			keyfile = "ti-degenerate-key.pem";
+		};
+		u_boot_spl_unsigned: u-boot-spl {
+			no-expanded;
+		};
+		ti_fs_gp: ti-fs-gp.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+		combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+		combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+#endif
+
+#ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53
+
+#define SPL_AM62A7_PHYBOARD_LYRA_DTB "spl/dts/ti/k3-am62a7-phyboard-lyra-rdk.dtb"
+#define AM62A7_PHYBOARD_LYRA_DTB "u-boot.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+		blob-ext {
+			filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tifsstub-hs {
+		filename = "tifsstub.bin_hs";
+		ti-secure-rom {
+			content = <&tifsstub_hs_cert>;
+			core = "secure";
+			load = <0x60000>;
+			sw-rev = <CONFIG_K3_X509_SWRV>;
+			keyfile = "custMpk.pem";
+			countersign;
+			tifsstub;
+		};
+		tifsstub_hs_cert: tifsstub-hs-cert.bin {
+			filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		tifsstub_hs_enc: tifsstub-hs-enc.bin {
+			filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+
+	tifsstub-fs {
+		filename = "tifsstub.bin_fs";
+		tifsstub_fs_cert: tifsstub-fs-cert.bin {
+			filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+		tifsstub_fs_enc: tifsstub-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+	};
+
+	tifsstub-gp {
+		filename = "tifsstub.bin_gp";
+		ti-secure-rom {
+			content = <&tifsstub_gp>;
+			core = "secure";
+			load = <0x60000>;
+			sw-rev = <CONFIG_K3_X509_SWRV>;
+			keyfile = "ti-degenerate-key.pem";
+			tifsstub;
+		};
+		tifsstub_gp: tifsstub-gp.bin {
+			filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
+			type = "blob-ext";
+			optional;
+		};
+	};
+
+	ti-spl {
+		insert-template = <&ti_spl_template>;
+
+		fit {
+			images {
+				tifsstub-hs {
+					description = "TIFSSTUB";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "tifsstub-hs";
+					load = <0x9ca00000>;
+					entry = <0x9ca00000>;
+					blob-ext {
+						filename = "tifsstub.bin_hs";
+					};
+				};
+
+				tifsstub-fs {
+					description = "TIFSSTUB";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "tifsstub-fs";
+					load = <0x9ca00000>;
+					entry = <0x9ca00000>;
+					blob-ext {
+						filename = "tifsstub.bin_fs";
+					};
+				};
+
+				tifsstub-gp {
+					description = "TIFSSTUB";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "tifsstub-gp";
+					load = <0x9ca00000>;
+					entry = <0x9ca00000>;
+					blob-ext {
+						filename = "tifsstub.bin_gp";
+					};
+				};
+				dm {
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+					dm: ti-dm {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&spl_am62a7_phyboard_lyra_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					spl_am62a7_phyboard_lyra_dtb: blob-ext {
+						filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl",
+					"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		insert-template = <&u_boot_template>;
+
+		fit {
+			images {
+				uboot {
+					description = "U-Boot for AM62Ax board";
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					ti-secure {
+						content = <&am62a7_phyboard_lyra_dtb>;
+						keyfile = "custMpk.pem";
+					};
+					am62a7_phyboard_lyra_dtb: blob-ext {
+						filename = AM62A7_PHYBOARD_LYRA_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	ti-spl_unsigned {
+		insert-template = <&ti_spl_unsigned_template>;
+
+		fit {
+			images {
+				tifsstub-hs {
+					description = "tifsstub";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "tifsstub-hs";
+					load = <0x9ca00000>;
+					entry = <0x9ca00000>;
+					blob-ext {
+						filename = "tifsstub.bin_hs";
+					};
+				};
+
+				tifsstub-fs {
+					description = "tifsstub";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "tifsstub-fs";
+					load = <0x9ca00000>;
+					entry = <0x9ca00000>;
+					blob-ext {
+						filename = "tifsstub.bin_fs";
+					};
+				};
+
+				tifsstub-gp {
+					description = "tifsstub";
+					type = "firmware";
+					arch = "arm32";
+					compression = "none";
+					os = "tifsstub-gp";
+					load = <0x9ca00000>;
+					entry = <0x9ca00000>;
+					blob-ext {
+						filename = "tifsstub.bin_gp";
+					};
+				};
+				dm {
+					ti-dm {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					spl_am62a7_phyboard_lyra_dtb_unsigned: blob {
+						filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl",
+					"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot_unsigned {
+		insert-template = <&u_boot_unsigned_template>;
+
+		fit {
+			images {
+				uboot {
+					description = "U-Boot for AM62Ax board";
+				};
+
+				fdt-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+					blob {
+						filename = AM62A7_PHYBOARD_LYRA_DTB;
+					};
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am62a7-phyboard-lyra-rdk";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+#endif

arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi

@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * phyCORE-AM62Ax dts file for SPLs
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phycore-am62ax
+ */
+
+#include "k3-am62a-phycore-som-binman.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &main_timer0;
+	};
+
+	aliases {
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+	};
+
+	memory@80000000 {
+		bootph-all;
+	};
+};
+
+&cbass_main {
+	bootph-all;
+};
+
+&cbass_mcu {
+	bootph-all;
+};
+
+&cbass_wakeup {
+	bootph-all;
+};
+
+&chipid {
+	bootph-all;
+};
+
+&cpsw3g {
+	bootph-all;
+	ethernet-ports {
+		bootph-all;
+	};
+};
+
+&cpsw3g_mdio {
+	bootph-all;
+};
+
+&cpsw3g_phy1 {
+	bootph-all;
+};
+
+&cpsw3g_phy3 {
+	bootph-all;
+};
+
+&cpsw_port1 {
+	bootph-all;
+};
+
+&cpsw_port2 {
+	bootph-all;
+};
+
+&dmsc {
+	bootph-all;
+};
+
+&dmss {
+	bootph-all;
+};
+
+&fss {
+	bootph-all;
+};
+
+&k3_pds {
+	bootph-all;
+};
+
+&k3_clks {
+	bootph-all;
+};
+
+&k3_reset {
+	bootph-all;
+};
+
+&main_bcdma {
+	bootph-all;
+	reg = <0x00 0x485c0100 0x00 0x100>,
+	      <0x00 0x4c000000 0x00 0x20000>,
+	      <0x00 0x4a820000 0x00 0x20000>,
+	      <0x00 0x4aa40000 0x00 0x20000>,
+	      <0x00 0x4bc00000 0x00 0x100000>,
+	      <0x00 0x48600000 0x00 0x8000>,
+	      <0x00 0x484a4000 0x00 0x2000>,
+	      <0x00 0x484c2000 0x00 0x2000>;
+	reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+		    "ringrt", "cfg", "tchan", "rchan";
+};
+
+&main_conf {
+	bootph-all;
+};
+
+&main_gpio0 {
+	bootph-all;
+};
+
+&main_i2c0 {
+	bootph-all;
+};
+
+&main_i2c0_pins_default {
+	bootph-all;
+};
+
+&main_mdio1_pins_default {
+	bootph-all;
+};
+
+&main_mmc0_pins_default {
+	bootph-all;
+};
+
+&main_mmc1_pins_default {
+	bootph-all;
+};
+
+&main_pktdma {
+	bootph-all;
+	reg = <0x00 0x485c0000 0x00 0x100>,
+	      <0x00 0x4a800000 0x00 0x20000>,
+	      <0x00 0x4aa00000 0x00 0x40000>,
+	      <0x00 0x4b800000 0x00 0x400000>,
+	      <0x00 0x485e0000 0x00 0x20000>,
+	      <0x00 0x484a0000 0x00 0x4000>,
+	      <0x00 0x484c0000 0x00 0x2000>,
+	      <0x00 0x48430000 0x00 0x4000>;
+	reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+		    "cfg", "tchan", "rchan", "rflow";
+};
+
+&main_pmx0 {
+	bootph-all;
+};
+
+&main_rgmii1_pins_default {
+	bootph-all;
+};
+
+&main_timer0 {
+	bootph-all;
+};
+
+&main_uart0 {
+	bootph-all;
+};
+
+&main_uart0_pins_default {
+	bootph-all;
+};
+
+&main_uart1 {
+	bootph-all;
+};
+
+&mcu_pmx0 {
+	bootph-all;
+};
+
+&ospi0_pins_default {
+	bootph-all;
+};
+
+&ospi0 {
+	bootph-all;
+	flash@0 {
+		bootph-all;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "ospi.tiboot3";
+				reg = <0x00000 0x80000>;
+			};
+			partition@80000 {
+				label = "ospi.tispl";
+				reg = <0x080000 0x200000>;
+			};
+			partition@280000 {
+				label = "ospi.u-boot";
+				reg = <0x280000 0x400000>;
+			};
+			partition@680000 {
+				label = "ospi.env";
+				reg = <0x680000 0x40000>;
+			};
+			partition@6c0000 {
+				label = "ospi.env.backup";
+				reg = <0x6c0000 0x40000>;
+			};
+		};
+	};
+};
+
+&phy_gmii_sel {
+	bootph-all;
+};
+
+&sdhci0 {
+	bootph-all;
+};
+
+&sdhci1 {
+	bootph-all;
+};
+
+&secure_proxy_main {
+	bootph-all;
+};
+
+&usbss0 {
+	bootph-all;
+};
+
+&usb0 {
+	dr_mode = "peripheral";
+	bootph-all;
+};
+
+&vcc_3v3_mmc {
+	bootph-all;
+};
+
+&wkup_conf {
+	bootph-all;
+};
+
+&wkup_uart0 {
+	bootph-all;
+};

arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts

@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * phyCORE-AM62Ax dts file for R5 SPL
+ * Copyright (C) 2024 PHYTEC America LLC
+ * Author: Garrett Giordano <ggiordano@phytec.com>
+ *
+ * Product homepage:
+ * https://www.phytec.com/product/phycore-am62ax
+ */
+
+#include "k3-am62a7-phyboard-lyra-rdk.dts"
+#include "k3-am62a-phycore-som-ddr4-2gb.dtsi"
+#include "k3-am62a-ddr.dtsi"
+
+#include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi"
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial3 = &main_uart1;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-pre-ram;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-pre-ram;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+		bootph-pre-ram;
+	};
+};
+
+&cbass_main {
+	bootph-pre-ram;
+	sa3_secproxy: secproxy@44880000 {
+		compatible = "ti,am654-secure-proxy";
+		#mbox-cells = <1>;
+		reg = <0x00 0x44880000 0x00 0x20000>,
+		      <0x0 0x44860000 0x0 0x20000>,
+		      <0x0 0x43600000 0x0 0x10000>;
+		reg-names = "rt", "scfg", "target_data";
+		bootph-pre-ram;
+	};
+
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&sa3_secproxy 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-pre-ram;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&main_bcdma {
+	ti,sci = <&dm_tifs>;
+};
+
+&main_pktdma {
+	ti,sci = <&dm_tifs>;
+};
+
+&main_pmx0 {
+	bootph-pre-ram;
+};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+	status = "okay";
+	bootph-pre-ram;
+};
+
+&mcu_pmx0 {
+	status = "okay";
+	bootph-pre-ram;
+
+	wkup_uart0_pins_default: wkup-uart0-pins-default {
+		pinctrl-single,pins = <
+			AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0)	/* (C6) WKUP_UART0_CTSn */
+			AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0)	/* (A4) WKUP_UART0_RTSn */
+			AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (B4) WKUP_UART0_RXD */
+			AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (C5) WKUP_UART0_TXD */
+		>;
+		bootph-pre-ram;
+	};
+};
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_uart0_pins_default>;
+	status = "okay";
+	bootph-pre-ram;
+};

arch/arm/dts/k3-am62a7-r5-sk.dts

@@ -12,6 +12,7 @@
 
 / {
 	aliases {
+		tick-timer = &main_timer0;
 		remoteproc0 = &sysctrler;
 		remoteproc1 = &a53_0;
 	};
@@ -71,6 +72,15 @@
 	};
 };
 
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+	bootph-pre-ram;
+};
+
 &wkup_uart0_pins_default {
 	bootph-pre-ram;
 };

arch/arm/dts/k3-am62a7-sk-u-boot.dtsi

@@ -9,7 +9,6 @@
 / {
 	chosen {
 		stdout-path = "serial2:115200n8";
-		tick-timer = &main_timer0;
 	};
 
 	memory@80000000 {
@@ -17,10 +16,6 @@
 	};
 };
 
-&main_timer0 {
-	bootph-all;
-};
-
 &cbass_main {
 	bootph-all;
 };

arch/arm/dts/k3-am62p-sk-binman.dtsi

@@ -57,6 +57,55 @@
 			type = "blob-ext";
 		};
 	};
+
+	tiboot3-am62px-hs-evm.bin {
+		filename = "tiboot3-am62px-hs-evm.bin";
+
+		ti-secure-rom {
+			content = <&u_boot_spl_hs>, <&ti_fs_enc_hs>, <&combined_tifs_cfg_hs>,
+				  <&combined_dm_cfg_hs>, <&sysfw_inner_cert_hs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_hs>;
+			content-sysfw = <&ti_fs_enc_hs>;
+			content-sysfw-data = <&combined_tifs_cfg_hs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_hs>;
+			content-dm-data = <&combined_dm_cfg_hs>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c4a800>;
+		};
+
+		u_boot_spl_hs: u-boot-spl {
+			no-expanded;
+		};
+
+		ti_fs_enc_hs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_tifs_cfg_hs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+
+		sysfw_inner_cert_hs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_dm_cfg_hs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
 };
 
 #include "k3-binman-capsule-r5.dtsi"

arch/arm/dts/k3-am62p5-r5-sk.dts

@@ -78,6 +78,14 @@
 	};
 };
 
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
 	status = "okay";

arch/arm/dts/k3-am642-phycore-som-binman.dtsi

@@ -118,6 +118,19 @@
 	};
 };
 
+#include "k3-binman-capsule-r5.dtsi"
+
+&capsule_tiboot3 {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am642-r5-phycore-som-2gb.dtb PHYCORE_AM64X_TIBOOT3
+		 */
+		image-guid = "B0A6B4FA-5DF0-5CD1-90EC-B60BDE798486";
+	};
+};
+
 #endif
 
 #ifdef CONFIG_TARGET_PHYCORE_AM64X_A53
@@ -502,4 +515,29 @@
 		};
 	};
 };
+
+#include "k3-binman-capsule.dtsi"
+
+&capsule_tispl {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am642-phyboard-electra-rdk.dtb PHYCORE_AM64X_SPL
+		 */
+		image-guid = "D0F34382-C2C4-509C-A1D4-BC1CB1B992A8";
+	};
+};
+
+&capsule_uboot {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am642-phyboard-electra-rdk.dtb PHYCORE_AM64X_UBOOT
+		 */
+		image-guid = "0BB40539-DB41-5407-B4D4-EAD057FE10F4";
+	};
+};
+
 #endif /* CONFIG_TARGET_PHYCORE_AM64X_A53 */

arch/arm/dts/k3-am65-mcu.dtsi

@@ -1,440 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
-	mcu_conf: scm-conf@40f00000 {
-		compatible = "syscon", "simple-mfd";
-		reg = <0x0 0x40f00000 0x0 0x20000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x40f00000 0x20000>;
-
-		phy_gmii_sel: phy@4040 {
-			compatible = "ti,am654-phy-gmii-sel";
-			reg = <0x4040 0x4>;
-			#phy-cells = <1>;
-		};
-	};
-
-	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
-	mcu_timerio_input: pinctrl@40f04200 {
-		compatible = "pinctrl-single";
-		reg = <0x0 0x40f04200 0x0 0x10>;
-		#pinctrl-cells = <1>;
-		pinctrl-single,register-width = <32>;
-		pinctrl-single,function-mask = <0x00000101>;
-	};
-
-	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
-	mcu_timerio_output: pinctrl@40f04280 {
-		compatible = "pinctrl-single";
-		reg = <0x0 0x40f04280 0x0 0x8>;
-		#pinctrl-cells = <1>;
-		pinctrl-single,register-width = <32>;
-		pinctrl-single,function-mask = <0x00000003>;
-	};
-
-	mcu_uart0: serial@40a00000 {
-		compatible = "ti,am654-uart";
-		reg = <0x00 0x40a00000 0x00 0x100>;
-		interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <96000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
-	};
-
-	mcu_ram: sram@41c00000 {
-		compatible = "mmio-sram";
-		reg = <0x00 0x41c00000 0x00 0x80000>;
-		ranges = <0x0 0x00 0x41c00000 0x80000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-
-	mcu_i2c0: i2c@40b00000 {
-		compatible = "ti,am654-i2c", "ti,omap4-i2c";
-		reg = <0x0 0x40b00000 0x0 0x100>;
-		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 114 1>;
-		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
-	};
-
-	mcu_spi0: spi@40300000 {
-		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
-		reg = <0x0 0x40300000 0x0 0x400>;
-		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&k3_clks 142 1>;
-		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	mcu_spi1: spi@40310000 {
-		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
-		reg = <0x0 0x40310000 0x0 0x400>;
-		interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&k3_clks 143 1>;
-		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	mcu_spi2: spi@40320000 {
-		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
-		reg = <0x0 0x40320000 0x0 0x400>;
-		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&k3_clks 144 1>;
-		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	tscadc0: tscadc@40200000 {
-		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
-		reg = <0x0 0x40200000 0x0 0x1000>;
-		interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&k3_clks 0 2>;
-		assigned-clocks = <&k3_clks 0 2>;
-		assigned-clock-rates = <60000000>;
-		clock-names = "fck";
-		dmas = <&mcu_udmap 0x7100>,
-			<&mcu_udmap 0x7101 >;
-		dma-names = "fifo0", "fifo1";
-		status = "disabled";
-
-		adc {
-			#io-channel-cells = <1>;
-			compatible = "ti,am654-adc", "ti,am3359-adc";
-		};
-	};
-
-	tscadc1: tscadc@40210000 {
-		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
-		reg = <0x0 0x40210000 0x0 0x1000>;
-		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&k3_clks 1 2>;
-		assigned-clocks = <&k3_clks 1 2>;
-		assigned-clock-rates = <60000000>;
-		clock-names = "fck";
-		dmas = <&mcu_udmap 0x7102>,
-			<&mcu_udmap 0x7103>;
-		dma-names = "fifo0", "fifo1";
-		status = "disabled";
-
-		adc {
-			#io-channel-cells = <1>;
-			compatible = "ti,am654-adc", "ti,am3359-adc";
-		};
-	};
-
-	/*
-	 * The MCU domain timer interrupts are routed only to the ESM module,
-	 * and not currently available for Linux. The MCU domain timers are
-	 * of limited use without interrupts, and likely reserved by the ESM.
-	 */
-	mcu_timer0: timer@40400000 {
-		compatible = "ti,am654-timer";
-		reg = <0x00 0x40400000 0x00 0x400>;
-		clocks = <&k3_clks 35 0>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
-		ti,timer-pwm;
-		status = "reserved";
-	};
-
-	mcu_timer1: timer@40410000 {
-		compatible = "ti,am654-timer";
-		reg = <0x00 0x40410000 0x00 0x400>;
-		clocks = <&k3_clks 36 0>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
-		ti,timer-pwm;
-		status = "reserved";
-	};
-
-	mcu_timer2: timer@40420000 {
-		compatible = "ti,am654-timer";
-		reg = <0x00 0x40420000 0x00 0x400>;
-		clocks = <&k3_clks 37 0>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
-		ti,timer-pwm;
-		status = "reserved";
-	};
-
-	mcu_timer3: timer@40430000 {
-		compatible = "ti,am654-timer";
-		reg = <0x00 0x40430000 0x00 0x400>;
-		clocks = <&k3_clks 38 0>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
-		ti,timer-pwm;
-		status = "reserved";
-	};
-
-	mcu_navss: bus@28380000 {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
-		dma-coherent;
-		dma-ranges;
-
-		ti,sci-dev-id = <119>;
-
-		mcu_ringacc: ringacc@2b800000 {
-			compatible = "ti,am654-navss-ringacc";
-			reg = <0x0 0x2b800000 0x0 0x400000>,
-			      <0x0 0x2b000000 0x0 0x400000>,
-			      <0x0 0x28590000 0x0 0x100>,
-			      <0x0 0x2a500000 0x0 0x40000>,
-			      <0x0 0x28440000 0x0 0x40000>;
-			reg-names = "rt", "fifos", "proxy_gcfg",
-				    "proxy_target", "cfg";
-			ti,num-rings = <286>;
-			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
-			ti,sci = <&dmsc>;
-			ti,sci-dev-id = <195>;
-			msi-parent = <&inta_main_udmass>;
-		};
-
-		mcu_udmap: dma-controller@285c0000 {
-			compatible = "ti,am654-navss-mcu-udmap";
-			reg = <0x0 0x285c0000 0x0 0x100>,
-			      <0x0 0x2a800000 0x0 0x40000>,
-			      <0x0 0x2aa00000 0x0 0x40000>;
-			reg-names = "gcfg", "rchanrt", "tchanrt";
-			msi-parent = <&inta_main_udmass>;
-			#dma-cells = <1>;
-
-			ti,sci = <&dmsc>;
-			ti,sci-dev-id = <194>;
-			ti,ringacc = <&mcu_ringacc>;
-
-			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
-						<0xd>; /* TX_CHAN */
-			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
-						<0xa>; /* RX_CHAN */
-			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
-		};
-	};
-
-	secure_proxy_mcu: mailbox@2a480000 {
-		compatible = "ti,am654-secure-proxy";
-		#mbox-cells = <1>;
-		reg-names = "target_data", "rt", "scfg";
-		reg = <0x0 0x2a480000 0x0 0x80000>,
-		      <0x0 0x2a380000 0x0 0x80000>,
-		      <0x0 0x2a400000 0x0 0x80000>;
-		/*
-		 * Marked Disabled:
-		 * Node is incomplete as it is meant for bootloaders and
-		 * firmware on non-MPU processors
-		 */
-		status = "disabled";
-	};
-
-	m_can0: can@40528000 {
-		compatible = "bosch,m_can";
-		reg = <0x0 0x40528000 0x0 0x400>,
-		      <0x0 0x40500000 0x0 0x4400>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
-		clock-names = "hclk", "cclk";
-		interrupt-parent = <&gic500>;
-		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
-		status = "disabled";
-	};
-
-	m_can1: can@40568000 {
-		compatible = "bosch,m_can";
-		reg = <0x0 0x40568000 0x0 0x400>,
-		      <0x0 0x40540000 0x0 0x4400>;
-		reg-names = "m_can", "message_ram";
-		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
-		clock-names = "hclk", "cclk";
-		interrupt-parent = <&gic500>;
-		interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "int0", "int1";
-		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
-		status = "disabled";
-	};
-
-	fss: bus@47000000 {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		ospi0: spi@47040000 {
-			compatible = "ti,am654-ospi", "cdns,qspi-nor";
-			reg = <0x0 0x47040000 0x0 0x100>,
-				<0x5 0x00000000 0x1 0x0000000>;
-			interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
-			cdns,fifo-depth = <256>;
-			cdns,fifo-width = <4>;
-			cdns,trigger-address = <0x0>;
-			clocks = <&k3_clks 248 0>;
-			assigned-clocks = <&k3_clks 248 0>;
-			assigned-clock-parents = <&k3_clks 248 2>;
-			assigned-clock-rates = <166666666>;
-			power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		ospi1: spi@47050000 {
-			compatible = "ti,am654-ospi", "cdns,qspi-nor";
-			reg = <0x0 0x47050000 0x0 0x100>,
-				<0x7 0x00000000 0x1 0x00000000>;
-			interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
-			cdns,fifo-depth = <256>;
-			cdns,fifo-width = <4>;
-			cdns,trigger-address = <0x0>;
-			clocks = <&k3_clks 249 6>;
-			power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-	};
-
-	mcu_cpsw: ethernet@46000000 {
-		compatible = "ti,am654-cpsw-nuss";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		reg = <0x0 0x46000000 0x0 0x200000>;
-		reg-names = "cpsw_nuss";
-		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
-		dma-coherent;
-		clocks = <&k3_clks 5 10>;
-		clock-names = "fck";
-		power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
-
-		dmas = <&mcu_udmap 0xf000>,
-		       <&mcu_udmap 0xf001>,
-		       <&mcu_udmap 0xf002>,
-		       <&mcu_udmap 0xf003>,
-		       <&mcu_udmap 0xf004>,
-		       <&mcu_udmap 0xf005>,
-		       <&mcu_udmap 0xf006>,
-		       <&mcu_udmap 0xf007>,
-		       <&mcu_udmap 0x7000>;
-		dma-names = "tx0", "tx1", "tx2", "tx3",
-			    "tx4", "tx5", "tx6", "tx7",
-			    "rx";
-
-		ethernet-ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			cpsw_port1: port@1 {
-				reg = <1>;
-				ti,mac-only;
-				label = "port1";
-				ti,syscon-efuse = <&mcu_conf 0x200>;
-				phys = <&phy_gmii_sel 1>;
-			};
-		};
-
-		davinci_mdio: mdio@f00 {
-			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
-			reg = <0x0 0xf00 0x0 0x100>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&k3_clks 5 10>;
-			clock-names = "fck";
-			bus_freq = <1000000>;
-			status = "disabled";
-		};
-
-		cpts@3d000 {
-			compatible = "ti,am65-cpts";
-			reg = <0x0 0x3d000 0x0 0x400>;
-			clocks = <&mcu_cpsw_cpts_mux>;
-			clock-names = "cpts";
-			interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "cpts";
-			ti,cpts-ext-ts-inputs = <4>;
-			ti,cpts-periodic-outputs = <2>;
-
-			mcu_cpsw_cpts_mux: refclk-mux {
-				#clock-cells = <0>;
-				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
-					<&k3_clks 118 6>, <&k3_clks 118 3>,
-					<&k3_clks 118 8>, <&k3_clks 118 14>,
-					<&k3_clks 120 3>, <&k3_clks 121 3>;
-				assigned-clocks = <&mcu_cpsw_cpts_mux>;
-				assigned-clock-parents = <&k3_clks 118 5>;
-			};
-		};
-	};
-
-	mcu_r5fss0: r5fss@41000000 {
-		compatible = "ti,am654-r5fss";
-		ti,cluster-mode = <1>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x41000000 0x00 0x41000000 0x20000>,
-			 <0x41400000 0x00 0x41400000 0x20000>;
-		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
-
-		mcu_r5fss0_core0: r5f@41000000 {
-			compatible = "ti,am654-r5f";
-			reg = <0x41000000 0x00008000>,
-			      <0x41010000 0x00008000>;
-			reg-names = "atcm", "btcm";
-			ti,sci = <&dmsc>;
-			ti,sci-dev-id = <159>;
-			ti,sci-proc-ids = <0x01 0xff>;
-			resets = <&k3_reset 159 1>;
-			firmware-name = "am65x-mcu-r5f0_0-fw";
-			ti,atcm-enable = <1>;
-			ti,btcm-enable = <1>;
-			ti,loczrama = <1>;
-		};
-
-		mcu_r5fss0_core1: r5f@41400000 {
-			compatible = "ti,am654-r5f";
-			reg = <0x41400000 0x00008000>,
-			      <0x41410000 0x00008000>;
-			reg-names = "atcm", "btcm";
-			ti,sci = <&dmsc>;
-			ti,sci-dev-id = <245>;
-			ti,sci-proc-ids = <0x02 0xff>;
-			resets = <&k3_reset 245 1>;
-			firmware-name = "am65x-mcu-r5f0_1-fw";
-			ti,atcm-enable = <1>;
-			ti,btcm-enable = <1>;
-			ti,loczrama = <1>;
-		};
-	};
-
-	mcu_rti1: watchdog@40610000 {
-		compatible = "ti,j7-rti-wdt";
-		reg = <0x0 0x40610000 0x0 0x100>;
-		clocks = <&k3_clks 135 0>;
-		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
-		assigned-clocks = <&k3_clks 135 0>;
-		assigned-clock-parents = <&k3_clks 135 4>;
-	};
-};

arch/arm/dts/k3-am65-wakeup.dtsi

@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_wakeup {
-	dmsc: system-controller@44083000 {
-		compatible = "ti,am654-sci";
-		ti,host-id = <12>;
-
-		mbox-names = "rx", "tx";
-
-		mboxes = <&secure_proxy_main 11>,
-			 <&secure_proxy_main 13>;
-
-		reg-names = "debug_messages";
-		reg = <0x44083000 0x1000>;
-
-		k3_pds: power-controller {
-			compatible = "ti,sci-pm-domain";
-			#power-domain-cells = <2>;
-		};
-
-		k3_clks: clock-controller {
-			compatible = "ti,k2g-sci-clk";
-			#clock-cells = <2>;
-		};
-
-		k3_reset: reset-controller {
-			compatible = "ti,sci-reset";
-			#reset-cells = <2>;
-		};
-	};
-
-	chipid@43000014 {
-		compatible = "ti,am654-chipid";
-		reg = <0x43000014 0x4>;
-	};
-
-	wkup_pmx0: pinctrl@4301c000 {
-		compatible = "pinctrl-single";
-		reg = <0x4301c000 0x118>;
-		#pinctrl-cells = <1>;
-		pinctrl-single,register-width = <32>;
-		pinctrl-single,function-mask = <0xffffffff>;
-	};
-
-	wkup_uart0: serial@42300000 {
-		compatible = "ti,am654-uart";
-		reg = <0x42300000 0x100>;
-		interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <48000000>;
-		current-speed = <115200>;
-		power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
-	};
-
-	wkup_i2c0: i2c@42120000 {
-		compatible = "ti,am654-i2c", "ti,omap4-i2c";
-		reg = <0x42120000 0x100>;
-		interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clock-names = "fck";
-		clocks = <&k3_clks 115 1>;
-		power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
-		status = "disabled";
-	};
-
-	intr_wkup_gpio: interrupt-controller@42200000 {
-		compatible = "ti,sci-intr";
-		reg = <0x42200000 0x200>;
-		ti,intr-trigger-type = <1>;
-		interrupt-controller;
-		interrupt-parent = <&gic500>;
-		#interrupt-cells = <1>;
-		ti,sci = <&dmsc>;
-		ti,sci-dev-id = <156>;
-		ti,interrupt-ranges = <0 712 16>;
-	};
-
-	wkup_gpio0: gpio@42110000 {
-		compatible = "ti,am654-gpio", "ti,keystone-gpio";
-		reg = <0x42110000 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		interrupt-parent = <&intr_wkup_gpio>;
-		interrupts = <60>, <61>, <62>, <63>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		ti,ngpio = <56>;
-		ti,davinci-gpio-unbanked = <0>;
-		clocks = <&k3_clks 59 0>;
-		clock-names = "gpio";
-	};
-
-	wkup_vtm0: temperature-sensor@42050000 {
-		compatible = "ti,am654-vtm";
-		reg = <0x42050000 0x25c>;
-		power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
-		#thermal-sensor-cells = <1>;
-	};
-};

arch/arm/dts/k3-am65.dtsi

@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC Family
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
-	model = "Texas Instruments K3 AM654 SoC";
-	compatible = "ti,am654";
-	interrupt-parent = <&gic500>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	chosen { };
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-
-		psci: psci {
-			compatible = "arm,psci-1.0";
-			method = "smc";
-		};
-	};
-
-	a53_timer0: timer-cl0-cpu0 {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a53-pmu";
-		/* Recommendation from GIC500 TRM Table A.3 */
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	cbass_main: bus@100000 {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
-			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
-			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
-			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
-			 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
-			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
-			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
-			 /* MCUSS Range */
-			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
-			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
-			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
-			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
-			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
-			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
-			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
-			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
-			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
-			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
-			 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
-			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
-			 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
-			 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
-			 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
-
-		cbass_mcu: bus@28380000 {
-			compatible = "simple-bus";
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
-				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
-				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
-				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
-				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
-				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
-				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
-				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
-				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
-				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
-				 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
-				 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
-				 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
-
-			cbass_wakeup: bus@42040000 {
-				compatible = "simple-bus";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				/* WKUP  Basic peripherals */
-				ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
-			};
-		};
-	};
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am65-main.dtsi"
-#include "k3-am65-mcu.dtsi"
-#include "k3-am65-wakeup.dtsi"

arch/arm/dts/k3-am654-base-board.dts

@@ -1,630 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am654.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
-	compatible = "ti,am654-evm", "ti,am654";
-	model = "Texas Instruments AM654 Base Board";
-
-	aliases {
-		serial0 = &wkup_uart0;
-		serial1 = &mcu_uart0;
-		serial2 = &main_uart0;
-		i2c0 = &wkup_i2c0;
-		i2c1 = &mcu_i2c0;
-		i2c2 = &main_i2c0;
-		i2c3 = &main_i2c1;
-		i2c4 = &main_i2c2;
-		ethernet0 = &cpsw_port1;
-		mmc0 = &sdhci0;
-		mmc1 = &sdhci1;
-	};
-
-	chosen {
-		stdout-path = "serial2:115200n8";
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* 4G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-		      <0x00000008 0x80000000 0x00000000 0x80000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		secure_ddr: secure-ddr@9e800000 {
-			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
-			alignment = <0x1000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
-			compatible = "shared-dma-pool";
-			reg = <0 0xa0000000 0 0x100000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
-			compatible = "shared-dma-pool";
-			reg = <0 0xa0100000 0 0xf00000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
-			compatible = "shared-dma-pool";
-			reg = <0 0xa1000000 0 0x100000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
-			compatible = "shared-dma-pool";
-			reg = <0 0xa1100000 0 0xf00000>;
-			no-map;
-		};
-
-		rtos_ipc_memory_region: ipc-memories@a2000000 {
-			reg = <0x00 0xa2000000 0x00 0x00100000>;
-			alignment = <0x1000>;
-			no-map;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		autorepeat;
-		pinctrl-names = "default";
-		pinctrl-0 = <&push_button_pins_default>;
-
-		switch-5 {
-			label = "GPIO Key USER1";
-			linux,code = <BTN_0>;
-			gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
-		};
-
-		switch-6 {
-			label = "GPIO Key USER2";
-			linux,code = <BTN_1>;
-			gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	evm_12v0: regulator-0 {
-		/* main supply */
-		compatible = "regulator-fixed";
-		regulator-name = "evm_12v0";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vcc3v3_io: regulator-1 {
-		/* Output of TPS54334 */
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3_io";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&evm_12v0>;
-	};
-
-	vdd_mmc1_sd: regulator-2 {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd_mmc1_sd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		enable-active-high;
-		vin-supply = <&vcc3v3_io>;
-		gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
-	};
-
-	vtt_supply: regulator-3 {
-		compatible = "regulator-fixed";
-		regulator-name = "vtt";
-		pinctrl-names = "default";
-		pinctrl-0 = <&ddr_vtt_pins_default>;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		enable-active-high;
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc3v3_io>;
-		gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&wkup_pmx0 {
-	wkup_uart0_pins_default: wkup-uart0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0)	/* (AB1) WKUP_UART0_RXD */
-			AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0)	/* (AB5) WKUP_UART0_TXD */
-			AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1)	/* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
-			AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1)	/* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
-		>;
-	};
-
-	ddr_vtt_pins_default: ddr-vtt-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7)	/* WKUP_GPIO0_28 */
-		>;
-	};
-
-	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
-			AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
-		>;
-	};
-
-	push_button_pins_default: push-button-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
-			AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
-		>;
-	};
-
-	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
-			AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)	 /* (U2) MCU_OSPI0_DQS */
-			AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
-			AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
-			AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
-			AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
-			AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
-			AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
-			AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
-			AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
-			AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
-		>;
-	};
-
-	wkup_pca554_default: wkup-pca554-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
-		>;
-	};
-
-	mcu_uart0_pins_default: mcu-uart0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)	/* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
-			AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)	/* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
-			AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)	/* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
-			AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4)	/* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
-		>;
-	};
-
-	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
-			AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
-			AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
-			AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
-			AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
-			AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
-			AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
-			AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
-			AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
-			AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
-			AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
-			AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
-		>;
-	};
-
-	mcu_mdio_pins_default: mcu-mdio1-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
-			AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
-		>;
-	};
-
-	mcu_i2c0_pins_default: mcu-i2c0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT,  0) /* (AD8) MCU_I2C0_SCL */
-			AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT,  0) /* (AD7) MCU_I2C0_SDA */
-		>;
-	};
-};
-
-&main_pmx0 {
-	main_uart0_pins_default: main-uart0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x01e4, PIN_INPUT, 0)	/* (AF11) UART0_RXD */
-			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)	/* (AE11) UART0_TXD */
-			AM65X_IOPAD(0x01ec, PIN_INPUT, 0)	/* (AG11) UART0_CTSn */
-			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)	/* (AD11) UART0_RTSn */
-		>;
-	};
-
-	main_i2c2_pins_default: main-i2c2-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
-			AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
-		>;
-	};
-
-	main_spi0_pins_default: main-spi0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
-			AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
-			AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
-			AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
-		>;
-	};
-
-	main_mmc0_pins_default: main-mmc0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
-			AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
-			AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
-			AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
-			AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
-			AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
-			AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
-			AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
-			AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
-			AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
-			AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
-			AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
-		>;
-	};
-
-	main_mmc1_pins_default: main-mmc1-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
-			AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
-			AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
-			AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
-			AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
-			AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
-			AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
-			AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
-		>;
-	};
-
-	usb1_pins_default: usb1-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
-		>;
-	};
-};
-
-&main_pmx1 {
-	main_i2c0_pins_default: main-i2c0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
-			AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
-			AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
-		>;
-	};
-
-	ecap0_pins_default: ecap0-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
-		>;
-	};
-};
-
-&wkup_uart0 {
-	/* Wakeup UART is used by System firmware */
-	status = "reserved";
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&mcu_uart0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_uart0_pins_default>;
-};
-
-&main_uart0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
-	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&wkup_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	eeprom@50 {
-		/* AT24CM01 */
-		compatible = "atmel,24c1024";
-		reg = <0x50>;
-	};
-
-	vdd_mpu: regulator@60 {
-		compatible = "ti,tps62363";
-		reg = <0x60>;
-		regulator-name = "VDD_MPU";
-		regulator-min-microvolt = <500000>;
-		regulator-max-microvolt = <1770000>;
-		regulator-always-on;
-		regulator-boot-on;
-		ti,vsel0-state-high;
-		ti,vsel1-state-high;
-		ti,enable-vout-discharge;
-	};
-
-	gpio@38 {
-		compatible = "nxp,pca9554";
-		reg = <0x38>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	pca9554: gpio@39 {
-		compatible = "nxp,pca9554";
-		reg = <0x39>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&wkup_pca554_default>;
-		interrupt-parent = <&wkup_gpio0>;
-		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-};
-
-&mcu_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_i2c0_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&main_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	pca9555: gpio@21 {
-		compatible = "nxp,pca9555";
-		reg = <0x21>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&main_i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&main_i2c2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c2_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&ecap0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&ecap0_pins_default>;
-};
-
-&main_spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_spi0_pins_default>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	ti,pindir-d0-out-d1-in;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-		spi-max-frequency = <48000000>;
-	};
-};
-
-&sdhci0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc0_pins_default>;
-	bus-width = <8>;
-	non-removable;
-	ti,driver-strength-ohm = <50>;
-	disable-wp;
-};
-
-/*
- * Because of erratas i2025 and i2026 for silicon revision 1.0, the
- * SD card interface might fail. Boards with sr1.0 are recommended to
- * disable sdhci1
- */
-&sdhci1 {
-	vmmc-supply = <&vdd_mmc1_sd>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc1_pins_default>;
-	ti,driver-strength-ohm = <50>;
-	disable-wp;
-};
-
-&usb1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb1_pins_default>;
-	dr_mode = "otg";
-};
-
-&dwc3_0 {
-	status = "disabled";
-};
-
-&usb0_phy {
-	status = "disabled";
-};
-
-&tscadc0 {
-	status = "okay";
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-	};
-};
-
-&tscadc1 {
-	status = "okay";
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6 7>;
-	};
-};
-
-&serdes0 {
-	status = "disabled";
-};
-
-&serdes1 {
-	status = "disabled";
-};
-
-&mailbox0_cluster0 {
-	status = "okay";
-	interrupts = <436>;
-
-	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
-		ti,mbox-tx = <1 0 0>;
-		ti,mbox-rx = <0 0 0>;
-	};
-};
-
-&mailbox0_cluster1 {
-	status = "okay";
-	interrupts = <432>;
-
-	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
-		ti,mbox-tx = <1 0 0>;
-		ti,mbox-rx = <0 0 0>;
-	};
-};
-
-&mcu_r5fss0_core0 {
-	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
-			<&mcu_r5fss0_core0_memory_region>;
-	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
-};
-
-&mcu_r5fss0_core1 {
-	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
-			<&mcu_r5fss0_core1_memory_region>;
-	mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
-};
-
-&ospi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-tx-bus-width = <8>;
-		spi-rx-bus-width = <8>;
-		spi-max-frequency = <25000000>;
-		cdns,tshsl-ns = <60>;
-		cdns,tsd2d-ns = <60>;
-		cdns,tchsh-ns = <60>;
-		cdns,tslch-ns = <60>;
-		cdns,read-delay = <0>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ospi.tiboot3";
-				reg = <0x0 0x80000>;
-			};
-
-			partition@80000 {
-				label = "ospi.tispl";
-				reg = <0x80000 0x200000>;
-			};
-
-			partition@280000 {
-				label = "ospi.u-boot";
-				reg = <0x280000 0x400000>;
-			};
-
-			partition@680000 {
-				label = "ospi.env";
-				reg = <0x680000 0x20000>;
-			};
-
-			partition@6a0000 {
-				label = "ospi.env.backup";
-				reg = <0x6a0000 0x20000>;
-			};
-
-			partition@6c0000 {
-				label = "ospi.sysfw";
-				reg = <0x6c0000 0x100000>;
-			};
-
-			partition@800000 {
-				label = "ospi.rootfs";
-				reg = <0x800000 0x37c0000>;
-			};
-
-			partition@3fe0000 {
-				label = "ospi.phypattern";
-				reg = <0x3fe0000 0x20000>;
-			};
-		};
-	};
-};
-
-&mcu_cpsw {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default>;
-};
-
-&davinci_mdio {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_mdio_pins_default>;
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&phy0>;
-};
-
-&dss {
-	status = "disabled";
-};

arch/arm/dts/k3-am654-icssg2.dtso

@@ -1,145 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/**
- * DT overlay for enabling ICSSG2 on AM654 EVM
- *
- * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-pinctrl.h"
-
-&{/} {
-	aliases {
-		ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
-		ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
-	};
-
-	/* Ethernet node on PRU-ICSSG2 */
-	icssg2_eth: icssg2-eth {
-		compatible = "ti,am654-icssg-prueth";
-		pinctrl-names = "default";
-		pinctrl-0 = <&icssg2_rgmii_pins_default>;
-		sram = <&msmc_ram>;
-		ti,prus = <&pru2_0>, <&rtu2_0>, <&tx_pru2_0>,
-			<&pru2_1>, <&rtu2_1>, <&tx_pru2_1>;
-		firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
-				"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
-				"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
-				"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
-				"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
-				"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
-
-		ti,pruss-gp-mux-sel = <2>,      /* MII mode */
-				      <2>,
-				      <2>,
-				      <2>,	/* MII mode */
-				      <2>,
-				      <2>;
-
-		ti,mii-g-rt = <&icssg2_mii_g_rt>;
-		ti,mii-rt = <&icssg2_mii_rt>;
-		ti,iep = <&icssg2_iep0>, <&icssg2_iep1>;
-
-		interrupt-parent = <&icssg2_intc>;
-		interrupts = <24 0 2>, <25 1 3>;
-		interrupt-names = "tx_ts0", "tx_ts1";
-
-		dmas = <&main_udmap 0xc300>, /* egress slice 0 */
-		       <&main_udmap 0xc301>, /* egress slice 0 */
-		       <&main_udmap 0xc302>, /* egress slice 0 */
-		       <&main_udmap 0xc303>, /* egress slice 0 */
-		       <&main_udmap 0xc304>, /* egress slice 1 */
-		       <&main_udmap 0xc305>, /* egress slice 1 */
-		       <&main_udmap 0xc306>, /* egress slice 1 */
-		       <&main_udmap 0xc307>, /* egress slice 1 */
-		       <&main_udmap 0x4300>, /* ingress slice 0 */
-		       <&main_udmap 0x4301>; /* ingress slice 1 */
-
-		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
-			    "tx1-0", "tx1-1", "tx1-2", "tx1-3",
-			    "rx0", "rx1";
-		ethernet-ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			icssg2_emac0: port@0 {
-				reg = <0>;
-				phy-handle = <&icssg2_phy0>;
-				phy-mode = "rgmii-id";
-				ti,syscon-rgmii-delay = <&scm_conf 0x4120>;
-				/* Filled in by bootloader */
-				local-mac-address = [00 00 00 00 00 00];
-			};
-			icssg2_emac1: port@1 {
-				reg = <1>;
-				phy-handle = <&icssg2_phy1>;
-				phy-mode = "rgmii-id";
-				ti,syscon-rgmii-delay = <&scm_conf 0x4124>;
-				/* Filled in by bootloader */
-				local-mac-address = [00 00 00 00 00 00];
-			};
-		};
-	};
-};
-
-&main_pmx0 {
-
-	icssg2_mdio_pins_default: icssg2-mdio-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x0094, PIN_INPUT, 2) /* (AC19) PRG2_PRU0_GPO7.PRG2_MDIO0_MDIO */
-			AM65X_IOPAD(0x00c8, PIN_OUTPUT, 2) /* (AE15) PRG2_PRU1_GPO7.PRG2_MDIO0_MDC */
-		>;
-	};
-
-	icssg2_rgmii_pins_default: icssg2-rgmii-default-pins {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x00ac, PIN_INPUT, 2) /* (AH15) PRG2_PRU1_GPO0.PRG2_RGMII2_RD0 */
-			AM65X_IOPAD(0x00b0, PIN_INPUT, 2) /* (AC16) PRG2_PRU1_GPO1.PRG2_RGMII2_RD1 */
-			AM65X_IOPAD(0x00b4, PIN_INPUT, 2) /* (AD17) PRG2_PRU1_GPO2.PRG2_RGMII2_RD2 */
-			AM65X_IOPAD(0x00b8, PIN_INPUT, 2) /* (AH14) PRG2_PRU1_GPO3.PRG2_RGMII2_RD3 */
-			AM65X_IOPAD(0x00cc, PIN_OUTPUT, 2) /* (AD15) PRG2_PRU1_GPO8.PRG2_RGMII2_TD0 */
-			AM65X_IOPAD(0x00d0, PIN_OUTPUT, 2) /* (AF14) PRG2_PRU1_GPO9.PRG2_RGMII2_TD1 */
-			AM65X_IOPAD(0x00d4, PIN_OUTPUT, 2) /* (AC15) PRG2_PRU1_GPO10.PRG2_RGMII2_TD2 */
-			AM65X_IOPAD(0x00d8, PIN_OUTPUT, 2) /* (AD14) PRG2_PRU1_GPO11.PRG2_RGMII2_TD3 */
-			AM65X_IOPAD(0x00dc, PIN_INPUT, 2) /* (AE14) PRG2_PRU1_GPO16.PRG2_RGMII2_TXC */
-			AM65X_IOPAD(0x00c4, PIN_OUTPUT, 2) /* (AC17) PRG2_PRU1_GPO6.PRG2_RGMII2_TX_CTL */
-			AM65X_IOPAD(0x00c0, PIN_INPUT, 2) /* (AG15) PRG2_PRU1_GPO5.PRG2_RGMII2_RXC */
-			AM65X_IOPAD(0x00bc, PIN_INPUT, 2) /* (AG14) PRG2_PRU1_GPO4.PRG2_RGMII2_RX_CTL */
-
-			AM65X_IOPAD(0x0078, PIN_INPUT, 2) /* (AF18) PRG2_PRU0_GPO0.PRG2_RGMII1_RD0 */
-			AM65X_IOPAD(0x007c, PIN_INPUT, 2) /* (AE18) PRG2_PRU0_GPO1.PRG2_RGMII1_RD1 */
-			AM65X_IOPAD(0x0080, PIN_INPUT, 2) /* (AH17) PRG2_PRU0_GPO2.PRG2_RGMII1_RD2 */
-			AM65X_IOPAD(0x0084, PIN_INPUT, 2) /* (AG18) PRG2_PRU0_GPO3.PRG2_RGMII1_RD3 */
-			AM65X_IOPAD(0x0098, PIN_OUTPUT, 2) /* (AH16) PRG2_PRU0_GPO8.PRG2_RGMII1_TD0 */
-			AM65X_IOPAD(0x009c, PIN_OUTPUT, 2) /* (AG16) PRG2_PRU0_GPO9.PRG2_RGMII1_TD1 */
-			AM65X_IOPAD(0x00a0, PIN_OUTPUT, 2) /* (AF16) PRG2_PRU0_GPO10.PRG2_RGMII1_TD2 */
-			AM65X_IOPAD(0x00a4, PIN_OUTPUT, 2) /* (AE16) PRG2_PRU0_GPO11.PRG2_RGMII1_TD3 */
-			AM65X_IOPAD(0x00a8, PIN_INPUT, 2) /* (AD16) PRG2_PRU0_GPO16.PRG2_RGMII1_TXC */
-			AM65X_IOPAD(0x0090, PIN_OUTPUT, 2) /* (AE17) PRG2_PRU0_GPO6.PRG2_RGMII1_TX_CTL */
-			AM65X_IOPAD(0x008c, PIN_INPUT, 2) /* (AF17) PRG2_PRU0_GPO5.PRG2_RGMII1_RXC */
-			AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */
-		>;
-	};
-};
-
-&icssg2_mdio {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&icssg2_mdio_pins_default>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	icssg2_phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-
-	icssg2_phy1: ethernet-phy@3 {
-		reg = <3>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};

arch/arm/dts/k3-am654-industrial-thermal.dtsi

@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/thermal/thermal.h>
-
-mpu0_thermal: mpu0-thermal {
-	polling-delay-passive = <250>; /* milliseconds */
-	polling-delay = <500>; /* milliseconds */
-	thermal-sensors = <&wkup_vtm0 0>;
-
-	trips {
-		mpu0_crit: mpu0-crit {
-			temperature = <125000>; /* milliCelsius */
-			hysteresis = <2000>; /* milliCelsius */
-			type = "critical";
-		};
-	};
-};
-
-mpu1_thermal: mpu1-thermal {
-	polling-delay-passive = <250>; /* milliseconds */
-	polling-delay = <500>; /* milliseconds */
-	thermal-sensors = <&wkup_vtm0 1>;
-
-	trips {
-		mpu1_crit: mpu1-crit {
-			temperature = <125000>; /* milliCelsius */
-			hysteresis = <2000>; /* milliCelsius */
-			type = "critical";
-		};
-	};
-};
-
-mcu_thermal: mcu-thermal {
-	polling-delay-passive = <250>; /* milliseconds */
-	polling-delay = <500>; /* milliseconds */
-	thermal-sensors = <&wkup_vtm0 2>;
-
-	trips {
-		mcu_crit: mcu-crit {
-			temperature = <125000>; /* milliCelsius */
-			hysteresis = <2000>; /* milliCelsius */
-			type = "critical";
-		};
-	};
-};

arch/arm/dts/k3-am654.dtsi

@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM6 SoC family in Quad core configuration
- *
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "k3-am65.dtsi"
-
-/ {
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		cpu-map {
-			cluster0: cluster0 {
-				core0 {
-					cpu = <&cpu0>;
-				};
-
-				core1 {
-					cpu = <&cpu1>;
-				};
-			};
-
-			cluster1: cluster1 {
-				core0 {
-					cpu = <&cpu2>;
-				};
-
-				core1 {
-					cpu = <&cpu3>;
-				};
-			};
-		};
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53";
-			reg = <0x000>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53";
-			reg = <0x001>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu2: cpu@100 {
-			compatible = "arm,cortex-a53";
-			reg = <0x100>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_1>;
-		};
-
-		cpu3: cpu@101 {
-			compatible = "arm,cortex-a53";
-			reg = <0x101>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_1>;
-		};
-	};
-
-	L2_0: l2-cache0 {
-		compatible = "cache";
-		cache-level = <2>;
-		cache-unified;
-		cache-size = <0x80000>;
-		cache-line-size = <64>;
-		cache-sets = <512>;
-		next-level-cache = <&msmc_l3>;
-	};
-
-	L2_1: l2-cache1 {
-		compatible = "cache";
-		cache-level = <2>;
-		cache-unified;
-		cache-size = <0x80000>;
-		cache-line-size = <64>;
-		cache-sets = <512>;
-		next-level-cache = <&msmc_l3>;
-	};
-
-	msmc_l3: l3-cache0 {
-		compatible = "cache";
-		cache-level = <3>;
-		cache-unified;
-	};
-
-	thermal_zones: thermal-zones {
-		#include "k3-am654-industrial-thermal.dtsi"
-	};
-};

arch/arm/dts/k3-am65x-binman.dtsi

@@ -95,10 +95,10 @@
 
 #ifdef CONFIG_TARGET_AM654_A53_EVM
 
-#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
+#define SPL_AM654_EVM_DTB "spl/dts/ti/k3-am654-base-board.dtb"
 #define AM654_EVM_DTB "u-boot.dtb"
 
-#define AM654_EVM_ICSSG2_DTBO "arch/arm/dts/k3-am654-icssg2.dtbo"
+#define AM654_EVM_ICSSG2_DTBO "ti/k3-am654-icssg2.dtbo"
 
 &binman {
 	ti-spl {

arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi

@@ -109,10 +109,6 @@
 	bootph-all;
 };
 
-&ospi0 {
-	status = "disabled";
-};
-
 &ospi1 {
 	status = "disabled";
 };

arch/arm/dts/k3-am68-sk-r5-base-board.dts

@@ -10,3 +10,8 @@
 #include "k3-j721s2-ddr.dtsi"
 #include "k3-am68-sk-base-board-u-boot.dtsi"
 #include "k3-j721s2-r5.dtsi"
+
+&wkup_vtm0 {
+	bootph-pre-ram;
+	vdd-supply-2 = <&tps62873a>;
+};

arch/arm/dts/k3-j7200-r5-common-proc-board.dts

@@ -23,11 +23,12 @@
 				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
 				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
 		resets = <&k3_reset 202 0>;
-		clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
-		clock-names = "gtc", "core";
-		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
-		assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
-		assigned-clock-rates = <2000000000>, <200000000>;
+		clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ;
+		clock-names = "gtc", "core", "msmc";
+		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>,
+						  <&k3_clks 323 0>;
+		assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
+		assigned-clock-rates = <2000000000>, <200000000>, <1000000000>;
 		ti,sci = <&dmsc>;
 		ti,sci-proc-id = <32>;
 		ti,sci-host-id = <10>;
@@ -53,6 +54,10 @@
 };
 
 &mcu_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
 	clock-frequency = <250000000>;
 	bootph-pre-ram;
 };
@@ -96,6 +101,13 @@
 	         <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
 };
 
+&hbmc {
+	reg = <0x0 0x47040000 0x0 0x100>,
+		<0x0 0x50000000 0x0 0x8000000>;
+	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>,
+		<0x1 0x0 0x0 0x54000000 0x800000>;
+};
+
 &mcu_ringacc {
     ti,sci = <&dm_tifs>;
 };

arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi

@@ -206,10 +206,10 @@
 #ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64
 
 #define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
-#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb"
+#define SPL_J721E_BBAI64_DTB "spl/dts/ti/k3-j721e-beagleboneai64.dtb"
 
 #define UBOOT_NODTB "u-boot-nodtb.bin"
-#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb"
+#define J721E_BBAI64_DTB "dts/upstream/src/arm64/ti/k3-j721e-beagleboneai64.dtb"
 
 &binman {
 	ti-dm {

arch/arm/dts/k3-j721e-beagleboneai64.dts

@@ -1,993 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * https://beagleboard.org/ai-64
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
- * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
- * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
- */
-
-/dts-v1/;
-
-#include "k3-j721e.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/phy/phy-cadence.h>
-
-/ {
-	compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
-	model = "BeagleBoard.org BeagleBone AI-64";
-
-	aliases {
-		serial0 = &wkup_uart0;
-		serial2 = &main_uart0;
-		mmc0 = &main_sdhci0;
-		mmc1 = &main_sdhci1;
-		i2c0 = &wkup_i2c0;
-		i2c1 = &main_i2c6;
-		i2c2 = &main_i2c2;
-		i2c3 = &main_i2c4;
-	};
-
-	chosen {
-		stdout-path = "serial2:115200n8";
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		/* 4G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-		      <0x00000008 0x80000000 0x00000000 0x80000000>;
-	};
-
-	reserved_memory: reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		secure_ddr: optee@9e800000 {
-			reg = <0x00 0x9e800000 0x00 0x01800000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa0000000 0x00 0x100000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa0100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa1000000 0x00 0x100000>;
-			no-map;
-		};
-
-		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa1100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa2000000 0x00 0x100000>;
-			no-map;
-		};
-
-		main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa2100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa3000000 0x00 0x100000>;
-			no-map;
-		};
-
-		main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa3100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa4000000 0x00 0x100000>;
-			no-map;
-		};
-
-		main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa4100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa5000000 0x00 0x100000>;
-			no-map;
-		};
-
-		main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa5100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa6000000 0x00 0x100000>;
-			no-map;
-		};
-
-		c66_0_memory_region: c66-memory@a6100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa6100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa7000000 0x00 0x100000>;
-			no-map;
-		};
-
-		c66_1_memory_region: c66-memory@a7100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa7100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa8000000 0x00 0x100000>;
-			no-map;
-		};
-
-		c71_0_memory_region: c71-memory@a8100000 {
-			compatible = "shared-dma-pool";
-			reg = <0x00 0xa8100000 0x00 0xf00000>;
-			no-map;
-		};
-
-		rtos_ipc_memory_region: ipc-memories@aa000000 {
-			reg = <0x00 0xaa000000 0x00 0x01c00000>;
-			alignment = <0x1000>;
-			no-map;
-		};
-	};
-
-	gpio_keys: gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&sw_pwr_pins_default>;
-
-		button-1 {
-			label = "BOOT";
-			linux,code = <BTN_0>;
-			gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
-		};
-
-		button-2 {
-			label = "POWER";
-			linux,code = <KEY_POWER>;
-			gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&led_pins_default>;
-
-		led-0 {
-			gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_HEARTBEAT;
-			linux,default-trigger = "heartbeat";
-		};
-
-		led-1 {
-			gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_DISK_ACTIVITY;
-			linux,default-trigger = "mmc0";
-		};
-
-		led-2 {
-			gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_CPU;
-			linux,default-trigger = "cpu";
-		};
-
-		led-3 {
-			gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_DISK_ACTIVITY;
-			linux,default-trigger = "mmc1";
-		};
-
-		led-4 {
-			gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
-			function = LED_FUNCTION_WLAN;
-			default-state = "off";
-		};
-	};
-
-	evm_12v0: regulator-0 {
-		/* main supply */
-		compatible = "regulator-fixed";
-		regulator-name = "evm_12v0";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vsys_3v3: regulator-1 {
-		/* Output of LMS140 */
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&evm_12v0>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vsys_5v0: regulator-2 {
-		/* Output of LM5140 */
-		compatible = "regulator-fixed";
-		regulator-name = "vsys_5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&evm_12v0>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_mmc1: regulator-3 {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&sd_pwr_en_pins_default>;
-		regulator-name = "vdd_mmc1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		enable-active-high;
-		vin-supply = <&vsys_3v3>;
-		gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
-	};
-
-	vdd_sd_dv_alt: regulator-4 {
-		compatible = "regulator-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
-		regulator-name = "tlv71033";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		vin-supply = <&vsys_5v0>;
-		gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
-		states = <1800000 0x0>,
-			 <3300000 0x1>;
-	};
-
-	dp_pwr_3v3: regulator-5 {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&dp0_3v3_en_pins_default>;
-		regulator-name = "dp-pwr";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
-		enable-active-high;
-	};
-
-	dp0: connector {
-		compatible = "dp-connector";
-		label = "DP0";
-		type = "full-size";
-		dp-pwr-supply = <&dp_pwr_3v3>;
-
-		port {
-			dp_connector_in: endpoint {
-				remote-endpoint = <&dp0_out>;
-			};
-		};
-	};
-};
-
-&main_pmx0 {
-	led_pins_default: led-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
-			J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
-			J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
-			J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
-			J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
-		>;
-	};
-
-	main_mmc1_pins_default: main-mmc1-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
-			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
-			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
-			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
-			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
-			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
-			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
-			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
-		>;
-	};
-
-	main_uart0_pins_default: main-uart0-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
-			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
-		>;
-	};
-
-	sd_pwr_en_pins_default: sd-pwr-en-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
-		>;
-	};
-
-	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
-		>;
-	};
-
-	main_usbss0_pins_default: main-usbss0-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
-		>;
-	};
-
-	main_usbss1_pins_default: main-usbss1-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
-		>;
-	};
-
-	dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
-		>;
-	};
-
-	dp0_pins_default: dp0-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
-		>;
-	};
-
-	main_i2c0_pins_default: main-i2c0-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
-			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
-			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
-		>;
-	};
-
-	main_i2c2_pins_default: main-i2c2-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
-			J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
-			J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
-			J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
-		>;
-	};
-
-	main_i2c3_pins_default: main-i2c3-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
-			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
-		>;
-	};
-
-	main_i2c4_pins_default: main-i2c4-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
-			J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
-			J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
-			J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
-		>;
-	};
-
-	main_i2c5_pins_default: main-i2c5-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
-			J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
-		>;
-	};
-
-	main_i2c6_pins_default: main-i2c6-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
-			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
-			J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
-			J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
-		>;
-	};
-
-	csi0_gpio_pins_default: csi0-gpio-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
-			J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
-		>;
-	};
-
-	csi1_gpio_pins_default: csi1-gpio-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
-			J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
-		>;
-	};
-
-	pcie1_rst_pins_default: pcie1-rst-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
-		>;
-	};
-};
-
-&wkup_pmx0 {
-	eeprom_wp_pins_default: eeprom-wp-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
-		>;
-	};
-
-	mcu_adc0_pins_default: mcu-adc0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
-			J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
-			J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
-			J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
-			J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
-			J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
-			J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
-		>;
-	};
-
-	mcu_adc1_pins_default: mcu-adc1-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
-		>;
-	};
-
-	mikro_bus_pins_default: mikro-bus-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
-			J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
-			J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
-			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
-			J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
-
-			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
-			J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
-			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
-			J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
-
-			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
-			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
-
-			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
-			J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
-			J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
-			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
-		>;
-	};
-
-	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
-			J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
-			J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
-			J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
-			J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
-			J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
-			J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
-			J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
-			J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
-			J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
-			J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
-			J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
-		>;
-	};
-
-	mcu_mdio_pins_default: mcu-mdio1-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
-			J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
-		>;
-	};
-
-	sw_pwr_pins_default: sw-pwr-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
-		>;
-	};
-
-	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
-			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
-		>;
-	};
-
-	wkup_uart0_pins_default: wkup-uart0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
-			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
-		>;
-	};
-
-	mcu_usbss1_pins_default: mcu-usbss1-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
-		>;
-	};
-};
-
-&wkup_uart0 {
-	/* Wakeup UART is used by TIFS firmware. */
-	status = "reserved";
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_uart0_pins_default>;
-};
-
-&main_uart0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart0_pins_default>;
-	/* Shared with ATF on this platform */
-	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
-};
-
-&main_sdhci0 {
-	/* eMMC */
-	status = "okay";
-	non-removable;
-	ti,driver-strength-ohm = <50>;
-	disable-wp;
-};
-
-&main_sdhci1 {
-	/* SD Card */
-	status = "okay";
-	vmmc-supply = <&vdd_mmc1>;
-	vqmmc-supply = <&vdd_sd_dv_alt>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mmc1_pins_default>;
-	ti,driver-strength-ohm = <50>;
-	disable-wp;
-};
-
-&main_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&main_i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&main_i2c2 {
-	/* BBB Header: P9.19 and P9.20 */
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c2_pins_default>;
-	clock-frequency = <100000>;
-};
-
-&main_i2c3 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c3_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&main_i2c4 {
-	/* BBB Header: P9.24 and P9.26 */
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c4_pins_default>;
-	clock-frequency = <100000>;
-};
-
-&main_i2c5 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c5_pins_default>;
-	clock-frequency = <400000>;
-};
-
-&main_i2c6 {
-	/* BBB Header: P9.17 and P9.18 */
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c6_pins_default>;
-	clock-frequency = <100000>;
-	status = "okay";
-};
-
-&wkup_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	eeprom@50 {
-		compatible = "atmel,24c04";
-		reg = <0x50>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&eeprom_wp_pins_default>;
-	};
-};
-
-&wkup_gpio0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
-		    <&mikro_bus_pins_default>;
-};
-
-&main_gpio0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
-};
-
-&main_gpio1 {
-	status = "okay";
-};
-
-&usb_serdes_mux {
-	idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
-};
-
-&serdes_ln_ctrl {
-	idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
-		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
-		      <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
-		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
-		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
-		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
-};
-
-&serdes_wiz3 {
-	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
-	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
-};
-
-&serdes3 {
-	serdes3_usb_link: phy@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
-		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
-	};
-};
-
-&serdes4 {
-	torrent_phy_dp: phy@0 {
-		reg = <0>;
-		resets = <&serdes_wiz4 1>;
-		cdns,phy-type = <PHY_TYPE_DP>;
-		cdns,num-lanes = <4>;
-		cdns,max-bit-rate = <5400>;
-		#phy-cells = <0>;
-	};
-};
-
-&mhdp {
-	phys = <&torrent_phy_dp>;
-	phy-names = "dpphy";
-	pinctrl-names = "default";
-	pinctrl-0 = <&dp0_pins_default>;
-};
-
-&usbss0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss0_pins_default>;
-	ti,vbus-divider;
-};
-
-&usb0 {
-	dr_mode = "peripheral";
-	maximum-speed = "super-speed";
-	phys = <&serdes3_usb_link>;
-	phy-names = "cdns3,usb3-phy";
-};
-
-&serdes2 {
-	serdes2_usb_link: phy@1 {
-		reg = <1>;
-		cdns,num-lanes = <1>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
-		resets = <&serdes_wiz2 2>;
-	};
-};
-
-&usbss1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
-	ti,vbus-divider;
-};
-
-&usb1 {
-	dr_mode = "host";
-	maximum-speed = "super-speed";
-	phys = <&serdes2_usb_link>;
-	phy-names = "cdns3,usb3-phy";
-};
-
-&tscadc0 {
-	status = "okay";
-	/* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
-	adc {
-		ti,adc-channels = <0 1 2 3 4 5 6>;
-	};
-};
-
-&tscadc1 {
-	status = "okay";
-	/* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
-	adc {
-		ti,adc-channels = <0>;
-	};
-};
-
-&mcu_cpsw {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default>;
-};
-
-&davinci_mdio {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_mdio_pins_default>;
-
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&phy0>;
-};
-
-&dss {
-	/*
-	 * These clock assignments are chosen to enable the following outputs:
-	 *
-	 * VP0 - DisplayPort SST
-	 * VP1 - DPI0
-	 * VP2 - DSI
-	 * VP3 - DPI1
-	 */
-
-	assigned-clocks = <&k3_clks 152 1>,	/* VP 1 pixel clock */
-			  <&k3_clks 152 4>,	/* VP 2 pixel clock */
-			  <&k3_clks 152 9>,	/* VP 3 pixel clock */
-			  <&k3_clks 152 13>;	/* VP 4 pixel clock */
-	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
-				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
-				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
-				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
-};
-
-&dss_ports {
-	port {
-		dpi0_out: endpoint {
-			remote-endpoint = <&dp0_in>;
-		};
-	};
-};
-
-&dp0_ports {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	port@0 {
-		reg = <0>;
-		dp0_in: endpoint {
-			remote-endpoint = <&dpi0_out>;
-		};
-	};
-
-	port@4 {
-		reg = <4>;
-		dp0_out: endpoint {
-			remote-endpoint = <&dp_connector_in>;
-		};
-	};
-};
-
-&serdes0 {
-	serdes0_pcie_link: phy@0 {
-		reg = <0>;
-		cdns,num-lanes = <1>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>;
-	};
-};
-
-&serdes1 {
-	serdes1_pcie_link: phy@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
-	};
-};
-
-&pcie1_rc {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie1_rst_pins_default>;
-	phys = <&serdes1_pcie_link>;
-	phy-names = "pcie-phy";
-	num-lanes = <2>;
-	max-link-speed = <3>;
-	reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
-};
-
-&ufs_wrapper {
-	status = "disabled";
-};
-
-&mailbox0_cluster0 {
-	status = "okay";
-	interrupts = <436>;
-
-	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster1 {
-	status = "okay";
-	interrupts = <432>;
-
-	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster2 {
-	status = "okay";
-	interrupts = <428>;
-
-	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster3 {
-	status = "okay";
-	interrupts = <424>;
-
-	mbox_c66_0: mbox-c66-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-
-	mbox_c66_1: mbox-c66-1 {
-		ti,mbox-rx = <2 0 0>;
-		ti,mbox-tx = <3 0 0>;
-	};
-};
-
-&mailbox0_cluster4 {
-	status = "okay";
-	interrupts = <420>;
-
-	mbox_c71_0: mbox-c71-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
-&mcu_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
-	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
-			<&mcu_r5fss0_core0_memory_region>;
-};
-
-&mcu_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
-	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
-			<&mcu_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss0_core0 {
-	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
-	memory-region = <&main_r5fss0_core0_dma_memory_region>,
-			<&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
-	mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
-	memory-region = <&main_r5fss0_core1_dma_memory_region>,
-			<&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
-	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
-	memory-region = <&main_r5fss1_core0_dma_memory_region>,
-			<&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
-	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
-	memory-region = <&main_r5fss1_core1_dma_memory_region>,
-			<&main_r5fss1_core1_memory_region>;
-};
-
-&c66_0 {
-	status = "okay";
-	mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
-	memory-region = <&c66_0_dma_memory_region>,
-			<&c66_0_memory_region>;
-};
-
-&c66_1 {
-	status = "okay";
-	mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
-	memory-region = <&c66_1_dma_memory_region>,
-			<&c66_1_memory_region>;
-};
-
-&c71_0 {
-	status = "okay";
-	mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
-	memory-region = <&c71_0_dma_memory_region>,
-			<&c71_0_memory_region>;
-};

arch/arm/dts/k3-j721e-r5-common-proc-board.dts

@@ -51,6 +51,13 @@
 	bootph-pre-ram;
 };
 
+&hbmc {
+	reg = <0x0 0x47040000 0x0 0x100>,
+		<0x0 0x50000000 0x0 0x8000000>;
+	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>,
+		 <0x1 0x0 0x0 0x54000000 0x800000>;
+};
+
 &ospi0 {
 	/* Address change for data region (32-bit) */
 	reg = <0x0 0x47040000 0x0 0x100>,

arch/arm/dts/k3-j721e-r5.dtsi

@@ -42,7 +42,11 @@
 };
 
 &mcu_timer0 {
-	status = "okay";
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <166666666>;
 	bootph-pre-ram;
 };
 

arch/arm/dts/k3-j721s2-r5-common-proc-board.dts

@@ -13,6 +13,10 @@
 
 &tps659411 {
 	bootph-pre-ram;
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		bootph-pre-ram;
+	};
 };
 
 &wkup_vtm0 {

arch/arm/dts/k3-j721s2-r5.dtsi

@@ -43,6 +43,10 @@
 };
 
 &mcu_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
 	clock-frequency = <250000000>;
 	bootph-pre-ram;
 };

arch/arm/dts/k3-j722s-evm-u-boot.dtsi

@@ -16,3 +16,7 @@
 &dmsc {
 	bootph-pre-ram;
 };
+
+&main_bcdma {
+	bootph-pre-ram;
+};

arch/arm/dts/k3-j722s-r5-evm.dts

@@ -41,8 +41,8 @@
 		ti,host-id = <36>;
 		ti,secure-host;
 		mbox-names = "rx", "tx";
-		mboxes= <&secure_proxy_main 22>,
-			<&secure_proxy_main 23>;
+		mboxes= <&secure_proxy_main 28>,
+			<&secure_proxy_main 29>;
 		bootph-all;
 	};
 };
@@ -77,7 +77,28 @@
 	};
 };
 
+&main_timer0 {
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	clock-frequency = <25000000>;
+};
+
 /* WKUP UART0 is used for DM firmware logs */
 &wkup_uart0 {
 	status = "okay";
 };
+
+&ospi0 {
+	reg = <0x00 0x0fc40000 0x00 0x100>,
+	      <0x00 0x60000000 0x00 0x08000000>;
+};
+
+&main_bcdma {
+	ti,sci = <&dm_tifs>;
+};
+
+&main_pktdma {
+	ti,sci = <&dm_tifs>;
+};

arch/arm/dts/k3-j784s4-r5.dtsi

@@ -41,7 +41,10 @@
 };
 
 &mcu_timer0 {
-	status = "okay";
+	/delete-property/ clocks;
+	/delete-property/ clocks-names;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
 	clock-frequency = <250000000>;
 	bootph-pre-ram;
 };
@@ -104,3 +107,9 @@
 &mcu_udmap {
 	ti,sci = <&dm_tifs>;
 };
+
+&wkup_vtm0 {
+	bootph-pre-ram;
+	vdd-supply-2 = <&tps62873a>;
+};
+

arch/arm/dts/meson-a1.dtsi

@@ -1,518 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- */
-
-#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
-#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
-#include <dt-bindings/gpio/meson-a1-gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/power/meson-a1-power.h>
-#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
-
-/ {
-	compatible = "amlogic,a1";
-
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			next-level-cache = <&l2>;
-		};
-
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0x0 0x1>;
-			enable-method = "psci";
-			next-level-cache = <&l2>;
-		};
-
-		l2: l2-cache0 {
-			compatible = "cache";
-			cache-level = <2>;
-			cache-unified;
-		};
-	};
-
-	efuse: efuse {
-		compatible = "amlogic,meson-gxbb-efuse";
-		clocks = <&clkc_periphs CLKID_OTP>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		secure-monitor = <&sm>;
-		power-domains = <&pwrc PWRC_OTP_ID>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		linux,cma {
-			compatible = "shared-dma-pool";
-			reusable;
-			size = <0x0 0x800000>;
-			alignment = <0x0 0x400000>;
-			linux,cma-default;
-		};
-	};
-
-	sm: secure-monitor {
-		compatible = "amlogic,meson-gxbb-sm";
-
-		pwrc: power-controller {
-			compatible = "amlogic,meson-a1-pwrc";
-			#power-domain-cells = <1>;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		spifc: spi@fd000400 {
-			compatible = "amlogic,a1-spifc";
-			reg = <0x0 0xfd000400 0x0 0x290>;
-			clocks = <&clkc_periphs CLKID_SPIFC>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			power-domains = <&pwrc PWRC_SPIFC_ID>;
-			status = "disabled";
-		};
-
-		apb: bus@fe000000 {
-			compatible = "simple-bus";
-			reg = <0x0 0xfe000000 0x0 0x1000000>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
-
-			reset: reset-controller@0 {
-				compatible = "amlogic,meson-a1-reset";
-				reg = <0x0 0x0 0x0 0x8c>;
-				#reset-cells = <1>;
-			};
-
-			periphs_pinctrl: pinctrl@400 {
-				compatible = "amlogic,meson-a1-periphs-pinctrl";
-				#address-cells = <2>;
-				#size-cells = <2>;
-				ranges;
-
-				gpio: bank@400 {
-					reg = <0x0 0x0400 0x0 0x003c>,
-					      <0x0 0x0480 0x0 0x0118>;
-					reg-names = "mux", "gpio";
-					gpio-controller;
-					#gpio-cells = <2>;
-					gpio-ranges = <&periphs_pinctrl 0 0 62>;
-				};
-
-				i2c0_f11_pins: i2c0-f11 {
-					mux {
-						groups = "i2c0_sck_f11",
-							 "i2c0_sda_f12";
-						function = "i2c0";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c0_f9_pins: i2c0-f9 {
-					mux {
-						groups = "i2c0_sck_f9",
-							 "i2c0_sda_f10";
-						function = "i2c0";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c1_x_pins: i2c1-x {
-					mux {
-						groups = "i2c1_sck_x",
-							 "i2c1_sda_x";
-						function = "i2c1";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c1_a_pins: i2c1-a {
-					mux {
-						groups = "i2c1_sck_a",
-							 "i2c1_sda_a";
-						function = "i2c1";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c2_x0_pins: i2c2-x0 {
-					mux {
-						groups = "i2c2_sck_x0",
-							 "i2c2_sda_x1";
-						function = "i2c2";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c2_x15_pins: i2c2-x15 {
-					mux {
-						groups = "i2c2_sck_x15",
-							 "i2c2_sda_x16";
-						function = "i2c2";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c2_a4_pins: i2c2-a4 {
-					mux {
-						groups = "i2c2_sck_a4",
-							 "i2c2_sda_a5";
-						function = "i2c2";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c2_a8_pins: i2c2-a8 {
-					mux {
-						groups = "i2c2_sck_a8",
-							 "i2c2_sda_a9";
-						function = "i2c2";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c3_x_pins: i2c3-x {
-					mux {
-						groups = "i2c3_sck_x",
-							 "i2c3_sda_x";
-						function = "i2c3";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				i2c3_f_pins: i2c3-f {
-					mux {
-						groups = "i2c3_sck_f",
-							 "i2c3_sda_f";
-						function = "i2c3";
-						bias-pull-up;
-						drive-strength-microamp = <3000>;
-					};
-				};
-
-				uart_a_pins: uart-a {
-					mux {
-						groups = "uart_a_tx",
-							 "uart_a_rx";
-						function = "uart_a";
-					};
-				};
-
-				uart_a_cts_rts_pins: uart-a-cts-rts {
-					mux {
-						groups = "uart_a_cts",
-							 "uart_a_rts";
-						function = "uart_a";
-						bias-pull-down;
-					};
-				};
-
-				sdio_pins: sdio {
-					mux0 {
-						groups = "sdcard_d0_x",
-							 "sdcard_d1_x",
-							 "sdcard_d2_x",
-							 "sdcard_d3_x",
-							 "sdcard_cmd_x";
-						function = "sdcard";
-						bias-pull-up;
-					};
-
-					mux1 {
-						groups = "sdcard_clk_x";
-						function = "sdcard";
-						bias-disable;
-					};
-				};
-
-				sdio_clk_gate_pins: sdio-clk-gate {
-					mux {
-						groups = "sdcard_clk_x";
-						function = "sdcard";
-						bias-pull-down;
-					};
-				};
-
-				spifc_pins: spifc {
-					mux {
-						groups = "spif_mo",
-							 "spif_mi",
-							 "spif_clk",
-							 "spif_cs",
-							 "spif_hold_n",
-							 "spif_wp_n";
-						function = "spif";
-					};
-				};
-			};
-
-			gpio_intc: interrupt-controller@440 {
-				compatible = "amlogic,meson-a1-gpio-intc",
-					     "amlogic,meson-gpio-intc";
-				reg = <0x0 0x0440 0x0 0x14>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				amlogic,channel-interrupts =
-					<49 50 51 52 53 54 55 56>;
-			};
-
-			clkc_periphs: clock-controller@800 {
-				compatible = "amlogic,a1-peripherals-clkc";
-				reg = <0 0x800 0 0x104>;
-				#clock-cells = <1>;
-				clocks = <&clkc_pll CLKID_FCLK_DIV2>,
-					 <&clkc_pll CLKID_FCLK_DIV3>,
-					 <&clkc_pll CLKID_FCLK_DIV5>,
-					 <&clkc_pll CLKID_FCLK_DIV7>,
-					 <&clkc_pll CLKID_HIFI_PLL>,
-					 <&xtal>;
-				clock-names = "fclk_div2", "fclk_div3",
-					      "fclk_div5", "fclk_div7",
-					      "hifi_pll", "xtal";
-			};
-
-			i2c0: i2c@1400 {
-				compatible = "amlogic,meson-axg-i2c";
-				status = "disabled";
-				reg = <0x0 0x1400 0x0 0x20>;
-				interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&clkc_periphs CLKID_I2C_M_A>;
-				power-domains = <&pwrc PWRC_I2C_ID>;
-			};
-
-			uart_AO: serial@1c00 {
-				compatible = "amlogic,meson-a1-uart",
-					     "amlogic,meson-ao-uart";
-				reg = <0x0 0x1c00 0x0 0x18>;
-				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
-				status = "disabled";
-			};
-
-			uart_AO_B: serial@2000 {
-				compatible = "amlogic,meson-a1-uart",
-					     "amlogic,meson-ao-uart";
-				reg = <0x0 0x2000 0x0 0x18>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>, <&xtal>, <&xtal>;
-				clock-names = "xtal", "pclk", "baud";
-				status = "disabled";
-			};
-
-			saradc: adc@2c00 {
-				compatible = "amlogic,meson-g12a-saradc",
-					"amlogic,meson-saradc";
-				reg = <0x0 0x2c00 0x0 0x48>;
-				#io-channel-cells = <1>;
-				power-domains = <&pwrc PWRC_I2C_ID>;
-				interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&xtal>,
-					<&clkc_periphs CLKID_SARADC_EN>,
-					<&clkc_periphs CLKID_SARADC>,
-					<&clkc_periphs CLKID_SARADC_SEL>;
-				clock-names = "clkin", "core",
-					"adc_clk", "adc_sel";
-				status = "disabled";
-			};
-
-			i2c1: i2c@5c00 {
-				compatible = "amlogic,meson-axg-i2c";
-				status = "disabled";
-				reg = <0x0 0x5c00 0x0 0x20>;
-				interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&clkc_periphs CLKID_I2C_M_B>;
-				power-domains = <&pwrc PWRC_I2C_ID>;
-			};
-
-			i2c2: i2c@6800 {
-				compatible = "amlogic,meson-axg-i2c";
-				status = "disabled";
-				reg = <0x0 0x6800 0x0 0x20>;
-				interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&clkc_periphs CLKID_I2C_M_C>;
-				power-domains = <&pwrc PWRC_I2C_ID>;
-			};
-
-			i2c3: i2c@6c00 {
-				compatible = "amlogic,meson-axg-i2c";
-				status = "disabled";
-				reg = <0x0 0x6c00 0x0 0x20>;
-				interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&clkc_periphs CLKID_I2C_M_D>;
-				power-domains = <&pwrc PWRC_I2C_ID>;
-			};
-
-			usb2_phy1: phy@4000 {
-				compatible = "amlogic,a1-usb2-phy";
-				clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
-				clock-names = "xtal";
-				reg = <0x0 0x4000 0x0 0x60>;
-				resets = <&reset RESET_USBPHY>;
-				reset-names = "phy";
-				#phy-cells = <0>;
-				power-domains = <&pwrc PWRC_USB_ID>;
-			};
-
-			hwrng: rng@5118 {
-				compatible = "amlogic,meson-rng";
-				reg = <0x0 0x5118 0x0 0x4>;
-				power-domains = <&pwrc PWRC_OTP_ID>;
-			};
-
-			sec_AO: ao-secure@5a20 {
-				compatible = "amlogic,meson-gx-ao-secure", "syscon";
-				reg = <0x0 0x5a20 0x0 0x140>;
-				amlogic,has-chip-id;
-			};
-
-			clkc_pll: pll-clock-controller@7c80 {
-				compatible = "amlogic,a1-pll-clkc";
-				reg = <0 0x7c80 0 0x18c>;
-				#clock-cells = <1>;
-				clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
-					 <&clkc_periphs CLKID_HIFIPLL_IN>;
-				clock-names = "fixpll_in", "hifipll_in";
-			};
-
-			sd_emmc: sd@10000 {
-				compatible = "amlogic,meson-axg-mmc";
-				reg = <0x0 0x10000 0x0 0x800>;
-				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
-					 <&clkc_periphs CLKID_SD_EMMC>,
-					 <&clkc_pll CLKID_FCLK_DIV2>;
-				clock-names = "core",
-					      "clkin0",
-					      "clkin1";
-				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
-				assigned-clock-parents = <&xtal>;
-				resets = <&reset RESET_SD_EMMC_A>;
-				power-domains = <&pwrc PWRC_SD_EMMC_ID>;
-				status = "disabled";
-			};
-		};
-
-		usb: usb@fe004400 {
-			status = "disabled";
-			compatible = "amlogic,meson-a1-usb-ctrl";
-			reg = <0x0 0xfe004400 0x0 0xa0>;
-			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-
-			clocks = <&clkc_periphs CLKID_USB_CTRL>,
-				 <&clkc_periphs CLKID_USB_BUS>,
-				 <&clkc_periphs CLKID_USB_CTRL_IN>;
-			clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
-			resets = <&reset RESET_USBCTRL>;
-			reset-name = "usb_ctrl";
-
-			dr_mode = "otg";
-
-			phys = <&usb2_phy1>;
-			phy-names = "usb2-phy1";
-
-			dwc3: usb@ff400000 {
-				compatible = "snps,dwc3";
-				reg = <0x0 0xff400000 0x0 0x100000>;
-				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-				dr_mode = "host";
-				snps,dis_u2_susphy_quirk;
-				snps,quirk-frame-length-adjustment = <0x20>;
-				snps,parkmode-disable-ss-quirk;
-			};
-
-			dwc2: usb@ff500000 {
-				compatible = "amlogic,meson-a1-usb", "snps,dwc2";
-				reg = <0x0 0xff500000 0x0 0x40000>;
-				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb2_phy1>;
-				phy-names = "usb2-phy";
-				clocks = <&clkc_periphs CLKID_USB_PHY>;
-				clock-names = "otg";
-				dr_mode = "peripheral";
-				g-rx-fifo-size = <192>;
-				g-np-tx-fifo-size = <128>;
-				g-tx-fifo-size = <128 128 16 16 16>;
-			};
-		};
-
-		gic: interrupt-controller@ff901000 {
-			compatible = "arm,gic-400";
-			reg = <0x0 0xff901000 0x0 0x1000>,
-			      <0x0 0xff902000 0x0 0x2000>,
-			      <0x0 0xff904000 0x0 0x2000>,
-			      <0x0 0xff906000 0x0 0x2000>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9
-				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	xtal: xtal-clk {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "xtal";
-		#clock-cells = <0>;
-	};
-};

arch/arm/dts/mt7629.dtsi

@@ -314,8 +314,10 @@
 				"sgmii2_cdr_ref", "sgmii2_cdr_fb",
 				"sgmii_ck", "eth2pll";
 		assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
-				  <&topckgen CLK_TOP_F10M_REF_SEL>;
+				  <&topckgen CLK_TOP_F10M_REF_SEL>,
+				  <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
 		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
+					 <&topckgen CLK_TOP_SYSPLL4_D16>,
 					 <&topckgen CLK_TOP_SGMIIPLL_D2>;
 		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 		resets = <&ethsys ETHSYS_FE_RST>;

arch/arm/dts/r8a779g0-u-boot.dtsi

@@ -7,11 +7,184 @@
 
 #include "r8a779x-u-boot.dtsi"
 
-&rpc {
-	bank-width = <2>;
-	num-cs = <1>;
+/ {
+	binman: binman {
+		multiple-images;
+
+		section {
+			filename = "flash.bin";
+			pad-byte = <0xff>;
+
+			/* Offset 0x0000 set to 0x0000_0000 */
+			fill@0 {
+				offset = <0x0>;
+				size = <0x4>;
+				fill-byte = [00];
+			};
+
+			/* Offset 0x300c set to 0x0000_0000 */
+			fill@300c {
+				offset = <0x300c>;
+				size = <0x4>;
+				fill-byte = [00];
+			};
+
+			/* Offset 0x3154 set to 0xeb21_0000 */
+			fill@3154 {
+				offset = <0x3154>;
+				size = <0x2>;
+				fill-byte = [00];
+			};
+
+			fill@3156 {
+				offset = <0x3156>;
+				size = <0x1>;
+				fill-byte = [21];
+			};
+
+			fill@3157 {
+				offset = <0x3157>;
+				size = <0x1>;
+				fill-byte = [eb];
+			};
+
+			/* Offset 0x3264 set to 0x0003_b000 */
+			fill@3264 {
+				offset = <0x3264>;
+				size = <0x1>;
+				fill-byte = [00];
+			};
+
+			fill@3265 {
+				offset = <0x3265>;
+				size = <0x1>;
+				fill-byte = [b0];
+			};
+
+			fill@3266 {
+				offset = <0x3266>;
+				size = <0x1>;
+				fill-byte = [03];
+			};
+
+			fill@3267 {
+				offset = <0x3267>;
+				size = <0x1>;
+				fill-byte = [00];
+			};
+
+			u-boot-spl {
+				offset = <0x40000>;
+				align-end = <4>;
+			};
+
+			u-boot {
+				offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+				filename = "u-boot.itb";
+
+				fit {
+					description = "U-Boot mainline";
+					fit,fdt-list = "of-list";
+					#address-cells = <1>;
+
+					images {
+						uboot {
+							arch = "arm64";
+							compression = "none";
+							description = "U-Boot (64-bit)";
+							type = "standalone";
+							/*
+							 * This is in DRAM. We cannot
+							 * use TEXT_BASE here because
+							 * this system uses PIE build
+							 * and TEXT_BASE=0x0 .
+							 */
+							entry = <0x44100000>;
+							load = <0x44100000>;
+
+							uboot-blob {
+								filename = "u-boot-nodtb.bin";
+								type = "blob-ext";
+							};
+						};
+
+						@fdt-SEQ {
+							compression = "none";
+							description = "NAME";
+							type = "flat_dt";
+
+							uboot-fdt-blob {
+								filename = "u-boot.dtb";
+								type = "blob-ext";
+							};
+						};
+					};
+
+					configurations {
+						default = "@config-DEFAULT-SEQ";
+
+						@config-SEQ {
+							description = "NAME";
+							fdt = "fdt-SEQ";
+							firmware = "uboot";
+						};
+					};
+				};
+			};
+		};
+	};
+};
+
+&cpg {
+	bootph-all;
 };
 
 &extalr_clk {
 	bootph-all;
 };
+
+&hscif0 {
+	bootph-all;
+};
+
+&hscif0_pins {
+	bootph-all;
+};
+
+&pfc {
+	bootph-all;
+};
+
+&rpc {
+	bank-width = <2>;
+	num-cs = <1>;
+};
+
+&rst {
+	bootph-all;
+};
+
+&soc {
+	apmu@e6170000 {	/* Remoteproc */
+		compatible = "renesas,r8a779g0-cr52";
+		reg = <0 0xe6170000 0 0x80000>;
+		power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+		status = "okay";
+	};
+
+	ram@e6780000 {	/* DBSC5 */
+		compatible = "renesas,r8a779g0-dbsc";
+		reg = <0 0xe6780000 0 0x80000>;
+		power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+		status = "okay";
+		bootph-all;
+	};
+
+	ram@ffec0000 {	/* RT-VRAM */
+		compatible = "renesas,r8a779g0-rtvram";
+		reg = <0 0xffec0000 0 0xf000>;
+		power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+		status = "okay";
+		bootph-all;
+	};
+};

arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi

@@ -22,8 +22,14 @@
 };
 
 &rpc {
+	bootph-all;
 	flash@0 {
+		bootph-all;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <1>;
 	};
 };
+
+&qspi0_pins {
+	bootph-all;
+};

arch/arm/dts/zynqmp-binman-mini.dts

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-u-boot.dtsi"

arch/arm/dts/zynqmp-binman-som.dts

@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SOMs (k24/k26)
+ *
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <config.h>
+
+/dts-v1/;
+/ {
+	binman: binman {
+		multiple-images;
+		fit-dtb.blob {
+			filename = "fit-dtb.blob";
+			pad-byte = <0>;
+			fit {
+				fit,align = <0x8>;
+				fit,external-offset = <0x0>;
+				description = "DTBs for SOMs+CCs";
+				fit,fdt-list-val = "zynqmp-smk-k26-revA", "zynqmp-smk-k26-revA-sck-kr-g-revA",
+						"zynqmp-smk-k26-revA-sck-kr-g-revB", "zynqmp-smk-k26-revA-sck-kv-g-revA",
+						"zynqmp-smk-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kv-g-revA",
+						"zynqmp-sm-k26-revA-sck-kv-g-revB", "zynqmp-sm-k26-revA-sck-kr-g-revB",
+						"zynqmp-smk-k24-revA-sck-kd-g-revA", "zynqmp-smk-k24-revA-sck-kv-g-revB",
+						"zynqmp-smk-k24-revA-sck-kr-g-revB", "zynqmp-sm-k24-revA-sck-kd-g-revA",
+						"zynqmp-sm-k24-revA-sck-kv-g-revB", "zynqmp-sm-k24-revA-sck-kr-g-revB";
+
+				images {
+					@fdt-SEQ {
+						description = "NAME";
+						type = "flat_dt";
+						arch = "arm64";
+						compression = "none";
+						hash-1 {
+							algo = "md5";
+						};
+					};
+				};
+				configurations {
+					default = "conf-1";
+					conf-1 {
+						description = "SOM itself";
+						fdt = "fdt-1";
+					};
+					conf-2 {
+						description = "zynqmp-smk-k26-.*-sck-kr-g-revA";
+						fdt = "fdt-2";
+					};
+					conf-3 {
+						description = "zynqmp-smk-k26-.*-sck-kr-g-.*";
+						fdt = "fdt-3";
+					};
+					conf-4 {
+						description = "zynqmp-smk-k26-.*-sck-kv-g-rev[AZ]";
+						fdt = "fdt-4";
+					};
+					conf-5 {
+						description = "zynqmp-smk-k26-.*-sck-kv-g-.*";
+						fdt = "fdt-5";
+					};
+					conf-6 {
+						description = "zynqmp-sm-k26-.*-sck-kv-g-rev[AZ]";
+						fdt = "fdt-6";
+					};
+					conf-7 {
+						description = "zynqmp-sm-k26-.*-sck-kv-g-.*";
+						fdt = "fdt-7";
+					};
+					conf-8 {
+						description = "zynqmp-sm-k26-.*-sck-kr-g-.*";
+						fdt = "fdt-8";
+					};
+					conf-9 {
+						description = "zynqmp-smk-k24-.*-sck-kd-g-.*";
+						fdt = "fdt-9";
+					};
+					conf-10 {
+						description = "zynqmp-smk-k24-.*-sck-kv-g-.*";
+						fdt = "fdt-10";
+					};
+					conf-11 {
+						description = "zynqmp-smk-k24-.*-sck-kr-g-.*";
+						fdt = "fdt-11";
+					};
+					conf-12 {
+						description = "zynqmp-sm-k24-.*-sck-kd-g-.*";
+						fdt = "fdt-12";
+					};
+					conf-13 {
+						description = "zynqmp-sm-k24-.*-sck-kv-g-.*";
+						fdt = "fdt-13";
+					};
+					conf-14 {
+						description = "zynqmp-sm-k24-.*-sck-kr-g-.*";
+						fdt = "fdt-14";
+					};
+				};
+			};
+		};
+
+		/* u-boot.itb generation in a static way */
+		itb {
+			filename = "u-boot.itb";
+			pad-byte = <0>;
+
+			fit {
+				description = "Configuration for Xilinx ZynqMP SoC";
+				fit,align = <0x8>;
+				fit,external-offset = <0x0>;
+				images {
+					uboot {
+						description = "U-Boot (64-bit)";
+						type = "firmware";
+						os = "u-boot";
+						arch = "arm64";
+						compression = "none";
+						load = /bits/ 64 <CONFIG_TEXT_BASE>;
+						entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+						hash {
+							algo = "md5";
+						};
+						u-boot-nodtb {
+						};
+					};
+					atf {
+						description = "Trusted Firmware-A";
+						type = "firmware";
+						os = "arm-trusted-firmware";
+						arch = "arm64";
+						compression = "none";
+						load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						hash {
+							algo = "md5";
+						};
+						atf-bl31 {
+							optional;
+						};
+					};
+					tee {
+						description = "OP-TEE";
+						type = "tee";
+						arch = "arm64";
+						compression = "none";
+						os = "tee";
+						load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						tee-os {
+							optional;
+						};
+					};
+					fdt {
+						description = "Multi DTB fit image";
+						type = "flat_dt";
+						arch = "arm64";
+						compression = "none";
+						load = <0x0 0x100000>;
+						hash {
+							algo = "md5";
+						};
+						fdt-blob {
+							filename = "fit-dtb.blob";
+							type = "blob-ext";
+						};
+					};
+				};
+				configurations {
+					default = "conf-1";
+					conf-1 {
+						description = "Multi DTB with TF-A/TEE";
+						firmware = "atf";
+						loadables = "tee", "uboot", "fdt";
+					};
+				};
+			};
+		};
+
+		/* boot.bin generated with version string inside */
+		bootimage {
+			filename = "boot.bin";
+			pad-byte = <0>;
+
+			blob-ext@1 {
+				offset = <0x0>;
+				filename = "spl/boot.bin";
+			};
+			/* Optional version string at offset 0x70 */
+			blob-ext@2 {
+				offset = <0x70>;
+				filename = "version.bin";
+				overlap;
+				optional;
+			};
+			/* Optional version string at offset 0x94 */
+			blob-ext@3 {
+				offset = <0x94>;
+				filename = "version.bin";
+				overlap;
+				optional;
+			};
+		};
+
+#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS
+		/* Full QSPI image for recovery app */
+		image {
+			filename = "qspi.bin";
+			pad-byte = <0>;
+
+			blob-ext@1 {
+				offset = <0x0>;
+				filename = "boot.bin";
+			};
+			blob-ext@2 {
+				offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+				filename = "u-boot.itb";
+			};
+			fdtmap {
+			};
+		};
+#endif
+	};
+};

arch/arm/dts/zynqmp-binman.dts

@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP platforms
+ *
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include <config.h>
+
+/dts-v1/;
+/ {
+	binman: binman {
+		multiple-images;
+
+		/* u-boot.itb generation in a static way */
+		itb {
+			filename = "u-boot.itb";
+			pad-byte = <0>;
+
+			fit {
+				description = "Configuration for Xilinx ZynqMP SoC";
+				fit,align = <0x8>;
+				fit,external-offset = <0x0>;
+				fit,fdt-list = "of-list";
+				images {
+					uboot {
+						description = "U-Boot (64-bit)";
+						type = "firmware";
+						os = "u-boot";
+						arch = "arm64";
+						compression = "none";
+						load = /bits/ 64 <CONFIG_TEXT_BASE>;
+						entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+						hash {
+							algo = "md5";
+						};
+						u-boot-nodtb {
+						};
+					};
+					atf {
+						description = "Trusted Firmware-A";
+						type = "firmware";
+						os = "arm-trusted-firmware";
+						arch = "arm64";
+						compression = "none";
+						load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						hash {
+							algo = "md5";
+						};
+						atf-bl31 {
+							optional;
+						};
+					};
+					tee {
+						description = "OP-TEE";
+						type = "tee";
+						arch = "arm64";
+						compression = "none";
+						os = "tee";
+						load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						tee-os {
+							optional;
+						};
+					};
+					@fdt-SEQ {
+						description = "NAME";
+						type = "flat_dt";
+						arch = "arm64";
+						compression = "none";
+						load = <0x0 0x100000>;
+						hash-1 {
+							algo = "md5";
+						};
+					};
+				};
+				configurations {
+					default = "@conf-DEFAULT-SEQ";
+					@conf-SEQ {
+						description = "NAME";
+						firmware = "atf";
+						loadables = "tee", "uboot";
+						fdt = "fdt-SEQ";
+					};
+				};
+			};
+		};
+
+		itb-single {
+			filename = "u-boot-single.itb";
+			pad-byte = <0>;
+
+			fit {
+				description = "Configuration for Xilinx ZynqMP SoC";
+				fit,align = <0x8>;
+				fit,external-offset = <0x0>;
+				fit,fdt-list = "of-list";
+				images {
+					uboot {
+						description = "U-Boot (64-bit)";
+						type = "firmware";
+						os = "u-boot";
+						arch = "arm64";
+						compression = "none";
+						load = /bits/ 64 <CONFIG_TEXT_BASE>;
+						entry = /bits/ 64 <CONFIG_TEXT_BASE>;
+						hash {
+							algo = "md5";
+						};
+						u-boot-nodtb {
+						};
+					};
+					atf {
+						description = "Trusted Firmware-A";
+						type = "firmware";
+						os = "arm-trusted-firmware";
+						arch = "arm64";
+						compression = "none";
+						load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						hash {
+							algo = "md5";
+						};
+						atf-bl31 {
+							optional;
+						};
+					};
+					tee {
+						description = "OP-TEE";
+						type = "tee";
+						arch = "arm64";
+						compression = "none";
+						os = "tee";
+						load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>;
+						tee-os {
+							optional;
+						};
+					};
+					fdt {
+						description = "DT";
+						type = "flat_dt";
+						arch = "arm64";
+						compression = "none";
+						load = <0x0 0x100000>;
+						uboot-fdt-blob {
+							filename = "u-boot.dtb";
+							type = "blob-ext";
+						};
+						hash-1 {
+							algo = "md5";
+						};
+
+					};
+				};
+				configurations {
+					default = "conf-1";
+					conf-1 {
+						description = "Single DT";
+						firmware = "atf";
+						loadables = "tee", "uboot";
+						fdt = "fdt";
+					};
+				};
+			};
+		};
+
+#ifdef CONFIG_SYS_SPI_U_BOOT_OFFS
+		/* QSPI image for testing QSPI boot mode */
+		image {
+			filename = "qspi.bin";
+			pad-byte = <0>;
+
+			blob-ext@1 {
+				offset = <0x0>;
+				filename = "spl/boot.bin";
+			};
+			blob-ext@2 {
+				offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+				filename = "u-boot.itb";
+			};
+			fdtmap {
+			};
+		};
+
+		image-single {
+			filename = "qspi-single.bin";
+			pad-byte = <0>;
+
+			blob-ext@1 {
+				offset = <0x0>;
+				filename = "spl/boot.bin";
+			};
+			blob-ext@2 {
+				offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+				filename = "u-boot-single.itb";
+			};
+			fdtmap {
+			};
+		};
+#endif
+	};
+};

arch/arm/dts/zynqmp-clk-ccf.dtsi

@@ -70,6 +70,22 @@
 	clocks = <&zynqmp_clk ACPU>;
 };
 
+&cpu0_debug {
+	clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu1_debug {
+	clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu2_debug {
+	clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu3_debug {
+	clocks = <&zynqmp_clk DBF_FPD>;
+};
+
 &fpd_dma_chan1 {
 	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 };

arch/arm/dts/zynqmp-sck-kd-g-revA.dtso

@@ -80,7 +80,10 @@
 				  "", "";
 	};
 
-	/* usb5744@2d */
+	hub: usb-hub@2d { /* u36 */
+		compatible = "microchip,usb5744";
+		reg = <0x2d>;
+	};
 };
 
 /* USB 3.0 */
@@ -99,18 +102,6 @@
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
-#if 0
-	usbhub0: usb-hub { /* u36 */
-		i2c-bus = <&i2c1>;
-		compatible = "microchip,usb5744";
-		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
-	};
-
-	usb2244: usb-sd { /* u41 */
-		compatible = "microchip,usb2244";
-		reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_0 {
@@ -118,6 +109,26 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub_3_0>;
+		i2c-bus = <&hub>;
+		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub_2_0>;
+		i2c-bus = <&hub>;
+		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &gem1 { /* mdio mio50/51 */

arch/arm/dts/zynqmp-sck-kr-g-revA.dtso

@@ -105,11 +105,19 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0>;
+			hub_1: usb-hub@2d {
+				compatible = "microchip,usb5744";
+				reg = <0x2d>;
+			};
 		};
 		usbhub_i2c1: i2c@1 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <1>;
+			hub_2: usb-hub@2d {
+				compatible = "microchip,usb5744";
+				reg = <0x2d>;
+			};
 		};
 		/* Bus 2/3 are not connected */
 	};
@@ -145,18 +153,6 @@
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
-#if 0
-	usbhub0: usb-hub { /* u43 */
-		i2c-bus = <&usbhub_i2c0>;
-		compatible = "microchip,usb5744";
-		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
-	};
-
-	usb2244: usb-sd { /* u38 */
-		compatible = "microchip,usb2244";
-		reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_0 {
@@ -164,6 +160,26 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub_3_0>;
+		i2c-bus = <&hub_1>;
+		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub_2_0>;
+		i2c-bus = <&hub_1>;
+		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &usb1 { /* mio64 - mio75 */
@@ -174,13 +190,6 @@
 	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
 	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
-#if 0
-	usbhub1: usb-hub { /* u84 */
-		i2c-bus = <&usbhub_i2c1>;
-		compatible = "microchip,usb5744";
-		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_1 {
@@ -188,6 +197,26 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub1_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub1_3_0>;
+		i2c-bus = <&hub_2>;
+		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub1_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub1_2_0>;
+		i2c-bus = <&hub_2>;
+		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &gem0 { /* mdio mio50/51 */

arch/arm/dts/zynqmp-sck-kr-g-revB.dtso

@@ -117,11 +117,19 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0>;
+			hub_1: usb-hub@2d {
+				compatible = "microchip,usb5744";
+				reg = <0x2d>;
+			};
 		};
 		usbhub_i2c1: i2c@1 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <1>;
+			hub_2: usb-hub@2d {
+				compatible = "microchip,usb5744";
+				reg = <0x2d>;
+			};
 		};
 		/* Bus 2/3 are not connected */
 	};
@@ -165,18 +173,6 @@
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 	reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
-#if 0
-	usbhub0: usb-hub { /* u43 */
-		i2c-bus = <&usbhub_i2c0>;
-		compatible = "microchip,usb5744";
-		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
-	};
-
-	usb2244: usb-sd { /* u38 */
-		compatible = "microchip,usb2244";
-		reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_0 {
@@ -184,6 +180,26 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub_3_0>;
+		i2c-bus = <&hub_1>;
+		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub_2_0>;
+		i2c-bus = <&hub_1>;
+		reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &usb1 { /* mio64 - mio75 */
@@ -194,14 +210,6 @@
 	phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
 	reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
 	assigned-clock-rates = <250000000>, <20000000>;
-
-#if 0
-	usbhub1: usb-hub { /* u84 */
-		i2c-bus = <&usbhub_i2c1>;
-		compatible = "microchip,usb5744";
-		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_1 {
@@ -209,6 +217,26 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub1_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub1_3_0>;
+		i2c-bus = <&hub_2>;
+		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub1_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub1_2_0>;
+		i2c-bus = <&hub_2>;
+		reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &gem0 { /* mdio mio50/51 */

arch/arm/dts/zynqmp-sck-kv-g-revA.dtso

@@ -129,12 +129,6 @@
 	pinctrl-0 = <&pinctrl_usb0_default>;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
-#if 0
-	usbhub: usb5744 { /* u43 */
-		compatible = "microchip,usb5744";
-		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_0 {
@@ -142,6 +136,24 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub_3_0>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub_2_0>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &sdhci1 { /* on CC with tuned parameters */

arch/arm/dts/zynqmp-sck-kv-g-revB.dtso

@@ -92,7 +92,10 @@
 		label = "ina260-u14";
 		reg = <0x40>;
 	};
-	/* u43 - 0x2d - USB hub */
+	hub: usb-hub@2d {
+		compatible = "microchip,usb5744";
+		reg = <0x2d>;
+	};
 	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
 };
 
@@ -131,14 +134,6 @@
 	phy-names = "usb3-phy";
 	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
 	assigned-clock-rates = <250000000>, <20000000>;
-#if 0
-	usb5744: usb-hub { /* u43 */
-		status = "okay";
-		compatible = "microchip,usb5744";
-		i2c-bus = <&i2c1>;
-		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
-	};
-#endif
 };
 
 &dwc3_0 {
@@ -146,6 +141,26 @@
 	dr_mode = "host";
 	snps,usb3_lpm_capable;
 	maximum-speed = "super-speed";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* 2.0 hub on port 1 */
+	hub_2_0: hub@1 {
+		compatible = "usb424,2744";
+		reg = <1>;
+		peer-hub = <&hub_3_0>;
+		i2c-bus = <&hub>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+	};
+
+	/* 3.0 hub on port 2 */
+	hub_3_0: hub@2 {
+		compatible = "usb424,5744";
+		reg = <2>;
+		peer-hub = <&hub_2_0>;
+		i2c-bus = <&hub>;
+		reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &sdhci1 { /* on CC with tuned parameters */

arch/arm/dts/zynqmp-sm-k26-revA.dts

@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */

arch/arm/dts/zynqmp-smk-k26-revA.dts

@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
  *
  * (C) Copyright 2020 - 2021, Xilinx, Inc.
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */

arch/arm/dts/zynqmp-u-boot.dtsi

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2024, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/ {
+	binman: binman {
+	};
+};

arch/arm/dts/zynqmp-zcu102-revA.dts

@@ -960,6 +960,7 @@
 
 &pcie {
 	status = "okay";
+	phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
 };
 
 &psgtr {

arch/arm/dts/zynqmp-zcu1275-revA.dts

@@ -15,8 +15,7 @@
 
 / {
 	model = "ZynqMP ZCU1275 RevA";
-	compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
-		     "xlnx,zynqmp";
+	compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
 
 	aliases {
 		serial0 = &uart0;

arch/arm/dts/zynqmp.dtsi

@@ -168,8 +168,8 @@
 		bootph-all;
 	};
 
-	pmu: pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
@@ -441,6 +441,34 @@
 			};
 		};
 
+		cpu0_debug: debug@fec10000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x0 0xfec10000 0x0 0x1000>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu0>;
+		};
+
+		cpu1_debug: debug@fed10000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x0 0xfed10000 0x0 0x1000>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu1>;
+		};
+
+		cpu2_debug: debug@fee10000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x0 0xfee10000 0x0 0x1000>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu2>;
+		};
+
+		cpu3_debug: debug@fef10000 {
+			compatible = "arm,coresight-cpu-debug", "arm,primecell";
+			reg = <0x0 0xfef10000 0x0 0x1000>;
+			clock-names = "apb_pclk";
+			cpu = <&cpu3>;
+		};
+
 		/* GDMA */
 		fpd_dma_chan1: dma-controller@fd500000 {
 			status = "disabled";
@@ -885,7 +913,6 @@
 			power-domains = <&zynqmp_firmware PD_SATA>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
 			/* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
-			/* dma-coherent; */
 		};
 
 		sdhci0: mmc@ff160000 {
@@ -1065,9 +1092,9 @@
 					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "ref";
 				/* iommus = <&smmu 0x860>; */
 				snps,quirk-frame-length-adjustment = <0x20>;
-				clock-names = "ref";
 				snps,resume-hs-terminations;
 				/* dma-coherent; */
 			};
@@ -1097,9 +1124,9 @@
 					     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "ref";
 				/* iommus = <&smmu 0x861>; */
 				snps,quirk-frame-length-adjustment = <0x20>;
-				clock-names = "ref";
 				snps,resume-hs-terminations;
 				/* dma-coherent; */
 			};
@@ -1176,11 +1203,14 @@
 				      "dp_vtc_pixel_clk_in";
 			power-domains = <&zynqmp_firmware PD_DP>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
-			dma-names = "vid0", "vid1", "vid2", "gfx0";
+			dma-names = "vid0", "vid1", "vid2", "gfx0",
+				    "aud0", "aud1";
 			dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
 			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
 			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
-			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>,
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>,
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>;
 
 			ports {
 				#address-cells = <1>;

arch/arm/include/asm/arch-imx/cpu.h

@@ -71,6 +71,11 @@
 #define MXC_CPU_IMX9302		0xC9 /* dummy ID */
 #define MXC_CPU_IMX9301		0xCA /* dummy ID */
 
+#define MXC_CPU_IMX91		0xCB /* dummy ID */
+#define MXC_CPU_IMX9121		0xCC /* dummy ID */
+#define MXC_CPU_IMX9111		0xCD /* dummy ID */
+#define MXC_CPU_IMX9101		0xCE /* dummy ID */
+
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
 #define MXC_SOC_IMX8M		0x80

arch/arm/include/asm/arch-imx8m/ddr.h

@@ -747,7 +747,4 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
 #define dwc_ddrphy_apb_rd(addr) \
 	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
 
-extern struct dram_cfg_param ddrphy_trained_csr[];
-extern uint32_t ddrphy_trained_csr_num;
-
 #endif

arch/arm/include/asm/arch-imx9/clock.h

@@ -205,10 +205,17 @@ struct clk_root_map {
 	u32 mux_type;
 };
 
+enum clk_soc {
+	CLK_SOC_ALL = 0,
+	CLK_SOC_IMX93 = 1,
+	CLK_SOC_IMX91 = 2,
+};
+
 struct imx_clk_setting {
 	u32 clk_root;
 	enum ccm_clk_src src;
 	u32 div;
+	enum clk_soc soc;
 };
 
 int clock_init_early(void);

arch/arm/include/asm/arch-imx9/ddr.h

@@ -141,7 +141,4 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
 #define dwc_ddrphy_apb_rd(addr) \
 	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
 
-extern struct dram_cfg_param ddrphy_trained_csr[];
-extern u32 ddrphy_trained_csr_num;
-
 #endif

arch/arm/include/asm/arch-imx9/gpio.h

@@ -6,6 +6,8 @@
 #ifndef __ASM_ARCH_IMX9_GPIO_H
 #define __ASM_ARCH_IMX9_GPIO_H
 
+#include <linux/types.h>
+
 struct gpio_regs {
 	u32 gpio_pdor;
 	u32 gpio_psor;

arch/arm/include/asm/arch-imx9/imx91_pins.h

@@ -0,0 +1,770 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX91_PINS_H__
+#define __ASM_ARCH_IMX91_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	MX91_PAD_DAP_TDI__JTAG_MUX_TDI                                                  = IOMUX_PAD(0x01B0, 0x0000, 0x00, 0x03D8, 0x00, 0x00),
+	MX91_PAD_DAP_TDI__MQS2_LEFT                                                     = IOMUX_PAD(0x01B0, 0x0000, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDI__CAN2_TX                                                       = IOMUX_PAD(0x01B0, 0x0000, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30                                              = IOMUX_PAD(0x01B0, 0x0000, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDI__GPIO3_IO28                                                    = IOMUX_PAD(0x01B0, 0x0000, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDI__LPUART5_RX                                                    = IOMUX_PAD(0x01B0, 0x0000, 0x06, 0x0488, 0x00, 0x00),
+
+	MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                                            = IOMUX_PAD(0x01B4, 0x0004, 0x00, 0x03DC, 0x00, 0x00),
+	MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                                        = IOMUX_PAD(0x01B4, 0x0004, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29                                              = IOMUX_PAD(0x01B4, 0x0004, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                                           = IOMUX_PAD(0x01B4, 0x0004, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                                           = IOMUX_PAD(0x01B8, 0x0008, 0x00, 0x03D4, 0x00, 0x00),
+	MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                                       = IOMUX_PAD(0x01B8, 0x0008, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                                             = IOMUX_PAD(0x01B8, 0x0008, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                                          = IOMUX_PAD(0x01B8, 0x0008, 0x06, 0x0484, 0x00, 0x00),
+
+	MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                                         = IOMUX_PAD(0x01BC, 0x000C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                                           = IOMUX_PAD(0x01BC, 0x000C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX                                              = IOMUX_PAD(0x01BC, 0x000C, 0x03, 0x0364, 0x00, 0x00),
+	MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31                                     = IOMUX_PAD(0x01BC, 0x000C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                                           = IOMUX_PAD(0x01BC, 0x000C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX                                           = IOMUX_PAD(0x01BC, 0x000C, 0x06, 0x048C, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO00__GPIO2_IO0                                                   = IOMUX_PAD(0x01C0, 0x0010, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO00__LPI2C3_SDA                                                  = IOMUX_PAD(0x01C0, 0x0010, 0x01, 0x03F4, 0x00, 0x00),
+	MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                                            = IOMUX_PAD(0x01C0, 0x0010, 0x02, 0x04BC, 0x00, 0x00),
+	MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                                           = IOMUX_PAD(0x01C0, 0x0010, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO00__LPSPI6_PCS0                                                 = IOMUX_PAD(0x01C0, 0x0010, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO00__LPUART5_TX                                                  = IOMUX_PAD(0x01C0, 0x0010, 0x05, 0x048C, 0x01, 0x00),
+	MX91_PAD_GPIO_IO00__LPI2C5_SDA                                                  = IOMUX_PAD(0x01C0, 0x0010, 0x06, 0x0404, 0x00, 0x00),
+	MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0                                             = IOMUX_PAD(0x01C0, 0x0010, 0x07, 0x036C, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO01__GPIO2_IO1                                                   = IOMUX_PAD(0x01C4, 0x0014, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO01__LPI2C3_SCL                                                  = IOMUX_PAD(0x01C4, 0x0014, 0x01, 0x03F0, 0x00, 0x00),
+	MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0                                          = IOMUX_PAD(0x01C4, 0x0014, 0x02, 0x0490, 0x00, 0x00),
+	MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                                            = IOMUX_PAD(0x01C4, 0x0014, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO01__LPSPI6_SIN                                                  = IOMUX_PAD(0x01C4, 0x0014, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO01__LPUART5_RX                                                  = IOMUX_PAD(0x01C4, 0x0014, 0x05, 0x0488, 0x01, 0x00),
+	MX91_PAD_GPIO_IO01__LPI2C5_SCL                                                  = IOMUX_PAD(0x01C4, 0x0014, 0x06, 0x0400, 0x00, 0x00),
+	MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1                                             = IOMUX_PAD(0x01C4, 0x0014, 0x07, 0x0370, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO02__GPIO2_IO2                                                   = IOMUX_PAD(0x01C8, 0x0018, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO02__LPI2C4_SDA                                                  = IOMUX_PAD(0x01C8, 0x0018, 0x01, 0x03FC, 0x00, 0x00),
+	MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                                          = IOMUX_PAD(0x01C8, 0x0018, 0x02, 0x04C0, 0x00, 0x00),
+	MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                                         = IOMUX_PAD(0x01C8, 0x0018, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO02__LPSPI6_SOUT                                                 = IOMUX_PAD(0x01C8, 0x0018, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO02__LPUART5_CTS_B                                               = IOMUX_PAD(0x01C8, 0x0018, 0x05, 0x0484, 0x01, 0x00),
+	MX91_PAD_GPIO_IO02__LPI2C6_SDA                                                  = IOMUX_PAD(0x01C8, 0x0018, 0x06, 0x040C, 0x00, 0x00),
+	MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2                                             = IOMUX_PAD(0x01C8, 0x0018, 0x07, 0x0374, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO03__GPIO2_IO3                                                   = IOMUX_PAD(0x01CC, 0x001C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__LPI2C4_SCL                                                  = IOMUX_PAD(0x01CC, 0x001C, 0x01, 0x03F8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                                          = IOMUX_PAD(0x01CC, 0x001C, 0x02, 0x04B8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                                         = IOMUX_PAD(0x01CC, 0x001C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__LPSPI6_SCK                                                  = IOMUX_PAD(0x01CC, 0x001C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__LPUART5_RTS_B                                               = IOMUX_PAD(0x01CC, 0x001C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__LPI2C6_SCL                                                  = IOMUX_PAD(0x01CC, 0x001C, 0x06, 0x0408, 0x00, 0x00),
+	MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3                                             = IOMUX_PAD(0x01CC, 0x001C, 0x07, 0x0378, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO04__GPIO2_IO4                                                   = IOMUX_PAD(0x01D0, 0x0020, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO04__TPM3_CH0                                                    = IOMUX_PAD(0x01D0, 0x0020, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO04__PDM_CLK                                                     = IOMUX_PAD(0x01D0, 0x0020, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0                                         = IOMUX_PAD(0x01D0, 0x0020, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO04__LPSPI7_PCS0                                                 = IOMUX_PAD(0x01D0, 0x0020, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO04__LPUART6_TX                                                  = IOMUX_PAD(0x01D0, 0x0020, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO04__LPI2C6_SDA                                                  = IOMUX_PAD(0x01D0, 0x0020, 0x06, 0x040C, 0x01, 0x00),
+	MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4                                             = IOMUX_PAD(0x01D0, 0x0020, 0x07, 0x037C, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO05__GPIO2_IO5                                                   = IOMUX_PAD(0x01D4, 0x0024, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO05__TPM4_CH0                                                    = IOMUX_PAD(0x01D4, 0x0024, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0                                             = IOMUX_PAD(0x01D4, 0x0024, 0x02, 0x04C4, 0x00, 0x00),
+	MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1                                         = IOMUX_PAD(0x01D4, 0x0024, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO05__LPSPI7_SIN                                                  = IOMUX_PAD(0x01D4, 0x0024, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO05__LPUART6_RX                                                  = IOMUX_PAD(0x01D4, 0x0024, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO05__LPI2C6_SCL                                                  = IOMUX_PAD(0x01D4, 0x0024, 0x06, 0x0408, 0x01, 0x00),
+	MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5                                             = IOMUX_PAD(0x01D4, 0x0024, 0x07, 0x0380, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO06__GPIO2_IO6                                                   = IOMUX_PAD(0x01D8, 0x0028, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__TPM5_CH0                                                    = IOMUX_PAD(0x01D8, 0x0028, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1                                             = IOMUX_PAD(0x01D8, 0x0028, 0x02, 0x04C8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2                                         = IOMUX_PAD(0x01D8, 0x0028, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__LPSPI7_SOUT                                                 = IOMUX_PAD(0x01D8, 0x0028, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__LPUART6_CTS_B                                               = IOMUX_PAD(0x01D8, 0x0028, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__LPI2C7_SDA                                                  = IOMUX_PAD(0x01D8, 0x0028, 0x06, 0x0414, 0x00, 0x00),
+	MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6                                             = IOMUX_PAD(0x01D8, 0x0028, 0x07, 0x0384, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO07__GPIO2_IO7                                                   = IOMUX_PAD(0x01DC, 0x002C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__LPSPI3_PCS1                                                 = IOMUX_PAD(0x01DC, 0x002C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1                                          = IOMUX_PAD(0x01DC, 0x002C, 0x02, 0x0494, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3                                         = IOMUX_PAD(0x01DC, 0x002C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__LPSPI7_SCK                                                  = IOMUX_PAD(0x01DC, 0x002C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__LPUART6_RTS_B                                               = IOMUX_PAD(0x01DC, 0x002C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__LPI2C7_SCL                                                  = IOMUX_PAD(0x01DC, 0x002C, 0x06, 0x0410, 0x00, 0x00),
+	MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7                                             = IOMUX_PAD(0x01DC, 0x002C, 0x07, 0x0388, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO08__GPIO2_IO8                                                   = IOMUX_PAD(0x01E0, 0x0030, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO08__LPSPI3_PCS0                                                 = IOMUX_PAD(0x01E0, 0x0030, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2                                          = IOMUX_PAD(0x01E0, 0x0030, 0x02, 0x0498, 0x00, 0x00),
+	MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4                                         = IOMUX_PAD(0x01E0, 0x0030, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO08__TPM6_CH0                                                    = IOMUX_PAD(0x01E0, 0x0030, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO08__LPUART7_TX                                                  = IOMUX_PAD(0x01E0, 0x0030, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO08__LPI2C7_SDA                                                  = IOMUX_PAD(0x01E0, 0x0030, 0x06, 0x0414, 0x01, 0x00),
+	MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8                                             = IOMUX_PAD(0x01E0, 0x0030, 0x07, 0x038C, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO09__GPIO2_IO9                                                   = IOMUX_PAD(0x01E4, 0x0034, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO09__LPSPI3_SIN                                                  = IOMUX_PAD(0x01E4, 0x0034, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3                                          = IOMUX_PAD(0x01E4, 0x0034, 0x02, 0x049C, 0x00, 0x00),
+	MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5                                         = IOMUX_PAD(0x01E4, 0x0034, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO09__TPM3_EXTCLK                                                 = IOMUX_PAD(0x01E4, 0x0034, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO09__LPUART7_RX                                                  = IOMUX_PAD(0x01E4, 0x0034, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO09__LPI2C7_SCL                                                  = IOMUX_PAD(0x01E4, 0x0034, 0x06, 0x0410, 0x01, 0x00),
+	MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9                                             = IOMUX_PAD(0x01E4, 0x0034, 0x07, 0x0390, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO10__GPIO2_IO10                                                  = IOMUX_PAD(0x01E8, 0x0038, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__LPSPI3_SOUT                                                 = IOMUX_PAD(0x01E8, 0x0038, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4                                          = IOMUX_PAD(0x01E8, 0x0038, 0x02, 0x04A0, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6                                         = IOMUX_PAD(0x01E8, 0x0038, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__TPM4_EXTCLK                                                 = IOMUX_PAD(0x01E8, 0x0038, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__LPUART7_CTS_B                                               = IOMUX_PAD(0x01E8, 0x0038, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__LPI2C8_SDA                                                  = IOMUX_PAD(0x01E8, 0x0038, 0x06, 0x041C, 0x00, 0x00),
+	MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                                            = IOMUX_PAD(0x01E8, 0x0038, 0x07, 0x0394, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO11__GPIO2_IO11                                                  = IOMUX_PAD(0x01EC, 0x003C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__LPSPI3_SCK                                                  = IOMUX_PAD(0x01EC, 0x003C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5                                          = IOMUX_PAD(0x01EC, 0x003C, 0x02, 0x04A4, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7                                         = IOMUX_PAD(0x01EC, 0x003C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__TPM5_EXTCLK                                                 = IOMUX_PAD(0x01EC, 0x003C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__LPUART7_RTS_B                                               = IOMUX_PAD(0x01EC, 0x003C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__LPI2C8_SCL                                                  = IOMUX_PAD(0x01EC, 0x003C, 0x06, 0x0418, 0x00, 0x00),
+	MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                                            = IOMUX_PAD(0x01EC, 0x003C, 0x07, 0x0398, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO12__GPIO2_IO12                                                  = IOMUX_PAD(0x01F0, 0x0040, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO12__TPM3_CH2                                                    = IOMUX_PAD(0x01F0, 0x0040, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2                                             = IOMUX_PAD(0x01F0, 0x0040, 0x02, 0x04CC, 0x00, 0x00),
+	MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8                                         = IOMUX_PAD(0x01F0, 0x0040, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO12__LPSPI8_PCS0                                                 = IOMUX_PAD(0x01F0, 0x0040, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO12__LPUART8_TX                                                  = IOMUX_PAD(0x01F0, 0x0040, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO12__LPI2C8_SDA                                                  = IOMUX_PAD(0x01F0, 0x0040, 0x06, 0x041C, 0x01, 0x00),
+	MX91_PAD_GPIO_IO12__SAI3_RX_SYNC                                                = IOMUX_PAD(0x01F0, 0x0040, 0x07, 0x04DC, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO13__GPIO2_IO13                                                  = IOMUX_PAD(0x01F4, 0x0044, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO13__TPM4_CH2                                                    = IOMUX_PAD(0x01F4, 0x0044, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3                                             = IOMUX_PAD(0x01F4, 0x0044, 0x02, 0x04D0, 0x00, 0x00),
+	MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9                                         = IOMUX_PAD(0x01F4, 0x0044, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO13__LPSPI8_SIN                                                  = IOMUX_PAD(0x01F4, 0x0044, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO13__LPUART8_RX                                                  = IOMUX_PAD(0x01F4, 0x0044, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO13__LPI2C8_SCL                                                  = IOMUX_PAD(0x01F4, 0x0044, 0x06, 0x0418, 0x01, 0x00),
+	MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                                            = IOMUX_PAD(0x01F4, 0x0044, 0x07, 0x039C, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO14__GPIO2_IO14                                                  = IOMUX_PAD(0x01F8, 0x0048, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__LPUART3_TX                                                  = IOMUX_PAD(0x01F8, 0x0048, 0x01, 0x0474, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6                                          = IOMUX_PAD(0x01F8, 0x0048, 0x02, 0x04A8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                                        = IOMUX_PAD(0x01F8, 0x0048, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__LPSPI8_SOUT                                                 = IOMUX_PAD(0x01F8, 0x0048, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__LPUART8_CTS_B                                               = IOMUX_PAD(0x01F8, 0x0048, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__LPUART4_TX                                                  = IOMUX_PAD(0x01F8, 0x0048, 0x06, 0x0480, 0x00, 0x00),
+	MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                                            = IOMUX_PAD(0x01F8, 0x0048, 0x07, 0x03A0, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO15__GPIO2_IO15                                                  = IOMUX_PAD(0x01FC, 0x004C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__LPUART3_RX                                                  = IOMUX_PAD(0x01FC, 0x004C, 0x01, 0x0470, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7                                          = IOMUX_PAD(0x01FC, 0x004C, 0x02, 0x04AC, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                                        = IOMUX_PAD(0x01FC, 0x004C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__LPSPI8_SCK                                                  = IOMUX_PAD(0x01FC, 0x004C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__LPUART8_RTS_B                                               = IOMUX_PAD(0x01FC, 0x004C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__LPUART4_RX                                                  = IOMUX_PAD(0x01FC, 0x004C, 0x06, 0x047C, 0x00, 0x00),
+	MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                                            = IOMUX_PAD(0x01FC, 0x004C, 0x07, 0x03A4, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO16__GPIO2_IO16                                                  = IOMUX_PAD(0x0200, 0x0050, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO16__SAI3_TX_BCLK                                                = IOMUX_PAD(0x0200, 0x0050, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2                                             = IOMUX_PAD(0x0200, 0x0050, 0x02, 0x04CC, 0x01, 0x00),
+	MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                                        = IOMUX_PAD(0x0200, 0x0050, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO16__LPUART3_CTS_B                                               = IOMUX_PAD(0x0200, 0x0050, 0x04, 0x046C, 0x00, 0x00),
+	MX91_PAD_GPIO_IO16__LPSPI4_PCS2                                                 = IOMUX_PAD(0x0200, 0x0050, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO16__LPUART4_CTS_B                                               = IOMUX_PAD(0x0200, 0x0050, 0x06, 0x0478, 0x00, 0x00),
+	MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                                            = IOMUX_PAD(0x0200, 0x0050, 0x07, 0x03A8, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO17__GPIO2_IO17                                                  = IOMUX_PAD(0x0204, 0x0054, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__SAI3_MCLK                                                   = IOMUX_PAD(0x0204, 0x0054, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8                                          = IOMUX_PAD(0x0204, 0x0054, 0x02, 0x04B0, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13                                        = IOMUX_PAD(0x0204, 0x0054, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__LPUART3_RTS_B                                               = IOMUX_PAD(0x0204, 0x0054, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__LPSPI4_PCS1                                                 = IOMUX_PAD(0x0204, 0x0054, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__LPUART4_RTS_B                                               = IOMUX_PAD(0x0204, 0x0054, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                                            = IOMUX_PAD(0x0204, 0x0054, 0x07, 0x03AC, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO18__GPIO2_IO18                                                  = IOMUX_PAD(0x0208, 0x0058, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__SAI3_RX_BCLK                                                = IOMUX_PAD(0x0208, 0x0058, 0x01, 0x04D8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9                                          = IOMUX_PAD(0x0208, 0x0058, 0x02, 0x04B4, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                                        = IOMUX_PAD(0x0208, 0x0058, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__LPSPI5_PCS0                                                 = IOMUX_PAD(0x0208, 0x0058, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__LPSPI4_PCS0                                                 = IOMUX_PAD(0x0208, 0x0058, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__TPM5_CH2                                                    = IOMUX_PAD(0x0208, 0x0058, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                                            = IOMUX_PAD(0x0208, 0x0058, 0x07, 0x03B0, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO19__GPIO2_IO19                                                  = IOMUX_PAD(0x020C, 0x005C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO19__SAI3_RX_SYNC                                                = IOMUX_PAD(0x020C, 0x005C, 0x01, 0x04DC, 0x01, 0x00),
+	MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3                                             = IOMUX_PAD(0x020C, 0x005C, 0x02, 0x04D0, 0x01, 0x00),
+	MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                                        = IOMUX_PAD(0x020C, 0x005C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO19__LPSPI5_SIN                                                  = IOMUX_PAD(0x020C, 0x005C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO19__LPSPI4_SIN                                                  = IOMUX_PAD(0x020C, 0x005C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO19__TPM6_CH2                                                    = IOMUX_PAD(0x020C, 0x005C, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO19__SAI3_TX_DATA0                                               = IOMUX_PAD(0x020C, 0x005C, 0x07, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO20__GPIO2_IO20                                                  = IOMUX_PAD(0x0210, 0x0060, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO20__SAI3_RX_DATA0                                               = IOMUX_PAD(0x0210, 0x0060, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0                                             = IOMUX_PAD(0x0210, 0x0060, 0x02, 0x04C4, 0x01, 0x00),
+	MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                                        = IOMUX_PAD(0x0210, 0x0060, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO20__LPSPI5_SOUT                                                 = IOMUX_PAD(0x0210, 0x0060, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO20__LPSPI4_SOUT                                                 = IOMUX_PAD(0x0210, 0x0060, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO20__TPM3_CH1                                                    = IOMUX_PAD(0x0210, 0x0060, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20                                            = IOMUX_PAD(0x0210, 0x0060, 0x07, 0x03B4, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO21__GPIO2_IO21                                                  = IOMUX_PAD(0x0214, 0x0064, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__SAI3_TX_DATA0                                               = IOMUX_PAD(0x0214, 0x0064, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__PDM_CLK                                                     = IOMUX_PAD(0x0214, 0x0064, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17                                        = IOMUX_PAD(0x0214, 0x0064, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__LPSPI5_SCK                                                  = IOMUX_PAD(0x0214, 0x0064, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__LPSPI4_SCK                                                  = IOMUX_PAD(0x0214, 0x0064, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__TPM4_CH1                                                    = IOMUX_PAD(0x0214, 0x0064, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO21__SAI3_RX_BCLK                                                = IOMUX_PAD(0x0214, 0x0064, 0x07, 0x04D8, 0x01, 0x00),
+
+	MX91_PAD_GPIO_IO22__GPIO2_IO22                                                  = IOMUX_PAD(0x0218, 0x0068, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO22__USDHC3_CLK                                                  = IOMUX_PAD(0x0218, 0x0068, 0x01, 0x04E8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO22__SPDIF_IN                                                    = IOMUX_PAD(0x0218, 0x0068, 0x02, 0x04E4, 0x00, 0x00),
+	MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                                        = IOMUX_PAD(0x0218, 0x0068, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO22__TPM5_CH1                                                    = IOMUX_PAD(0x0218, 0x0068, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO22__TPM6_EXTCLK                                                 = IOMUX_PAD(0x0218, 0x0068, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO22__LPI2C5_SDA                                                  = IOMUX_PAD(0x0218, 0x0068, 0x06, 0x0404, 0x01, 0x00),
+	MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                                            = IOMUX_PAD(0x0218, 0x0068, 0x07, 0x03B8, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO23__GPIO2_IO23                                                  = IOMUX_PAD(0x021C, 0x006C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO23__USDHC3_CMD                                                  = IOMUX_PAD(0x021C, 0x006C, 0x01, 0x04EC, 0x00, 0x00),
+	MX91_PAD_GPIO_IO23__SPDIF_OUT                                                   = IOMUX_PAD(0x021C, 0x006C, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                                        = IOMUX_PAD(0x021C, 0x006C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO23__TPM6_CH1                                                    = IOMUX_PAD(0x021C, 0x006C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO23__LPI2C5_SCL                                                  = IOMUX_PAD(0x021C, 0x006C, 0x06, 0x0400, 0x01, 0x00),
+	MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                                            = IOMUX_PAD(0x021C, 0x006C, 0x07, 0x03BC, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO24__GPIO2_IO24                                                  = IOMUX_PAD(0x0220, 0x0070, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO24__USDHC3_DATA0                                                = IOMUX_PAD(0x0220, 0x0070, 0x01, 0x04F0, 0x00, 0x00),
+	MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                                        = IOMUX_PAD(0x0220, 0x0070, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO24__TPM3_CH3                                                    = IOMUX_PAD(0x0220, 0x0070, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO24__JTAG_MUX_TDO                                                = IOMUX_PAD(0x0220, 0x0070, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO24__LPSPI6_PCS1                                                 = IOMUX_PAD(0x0220, 0x0070, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                                            = IOMUX_PAD(0x0220, 0x0070, 0x07, 0x03C0, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO25__GPIO2_IO25                                                  = IOMUX_PAD(0x0224, 0x0074, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO25__USDHC3_DATA1                                                = IOMUX_PAD(0x0224, 0x0074, 0x01, 0x04F4, 0x00, 0x00),
+	MX91_PAD_GPIO_IO25__CAN2_TX                                                     = IOMUX_PAD(0x0224, 0x0074, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                                        = IOMUX_PAD(0x0224, 0x0074, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO25__TPM4_CH3                                                    = IOMUX_PAD(0x0224, 0x0074, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO25__JTAG_MUX_TCK                                                = IOMUX_PAD(0x0224, 0x0074, 0x05, 0x03D4, 0x01, 0x00),
+	MX91_PAD_GPIO_IO25__LPSPI7_PCS1                                                 = IOMUX_PAD(0x0224, 0x0074, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                                            = IOMUX_PAD(0x0224, 0x0074, 0x07, 0x03C4, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO26__GPIO2_IO26                                                  = IOMUX_PAD(0x0228, 0x0078, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO26__USDHC3_DATA2                                                = IOMUX_PAD(0x0228, 0x0078, 0x01, 0x04F8, 0x00, 0x00),
+	MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1                                             = IOMUX_PAD(0x0228, 0x0078, 0x02, 0x04C8, 0x01, 0x00),
+	MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                                        = IOMUX_PAD(0x0228, 0x0078, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO26__TPM5_CH3                                                    = IOMUX_PAD(0x0228, 0x0078, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO26__JTAG_MUX_TDI                                                = IOMUX_PAD(0x0228, 0x0078, 0x05, 0x03D8, 0x01, 0x00),
+	MX91_PAD_GPIO_IO26__LPSPI8_PCS1                                                 = IOMUX_PAD(0x0228, 0x0078, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO26__SAI3_TX_SYNC                                                = IOMUX_PAD(0x0228, 0x0078, 0x07, 0x04E0, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO27__GPIO2_IO27                                                  = IOMUX_PAD(0x022C, 0x007C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO27__USDHC3_DATA3                                                = IOMUX_PAD(0x022C, 0x007C, 0x01, 0x04FC, 0x00, 0x00),
+	MX91_PAD_GPIO_IO27__CAN2_RX                                                     = IOMUX_PAD(0x022C, 0x007C, 0x02, 0x0364, 0x01, 0x00),
+	MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                                        = IOMUX_PAD(0x022C, 0x007C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO27__TPM6_CH3                                                    = IOMUX_PAD(0x022C, 0x007C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO27__JTAG_MUX_TMS                                                = IOMUX_PAD(0x022C, 0x007C, 0x05, 0x03DC, 0x01, 0x00),
+	MX91_PAD_GPIO_IO27__LPSPI5_PCS1                                                 = IOMUX_PAD(0x022C, 0x007C, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                                            = IOMUX_PAD(0x022C, 0x007C, 0x07, 0x03C8, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO28__GPIO2_IO28                                                  = IOMUX_PAD(0x0230, 0x0080, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO28__LPI2C3_SDA                                                  = IOMUX_PAD(0x0230, 0x0080, 0x01, 0x03F4, 0x01, 0x00),
+	MX91_PAD_GPIO_IO28__CAN1_TX                                                     = IOMUX_PAD(0x0230, 0x0080, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                                            = IOMUX_PAD(0x0230, 0x0080, 0x07, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_GPIO_IO29__GPIO2_IO29                                                  = IOMUX_PAD(0x0234, 0x0084, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_GPIO_IO29__LPI2C3_SCL                                                  = IOMUX_PAD(0x0234, 0x0084, 0x01, 0x03F0, 0x01, 0x00),
+	MX91_PAD_GPIO_IO29__CAN1_RX                                                     = IOMUX_PAD(0x0234, 0x0084, 0x02, 0x0360, 0x00, 0x00),
+	MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                                            = IOMUX_PAD(0x0234, 0x0084, 0x07, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                                          = IOMUX_PAD(0x0238, 0x0088, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                                            = IOMUX_PAD(0x0238, 0x0088, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO1__GPIO3_IO26                                                  = IOMUX_PAD(0x0238, 0x0088, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_CCM_CLKO2__GPIO3_IO27                                                  = IOMUX_PAD(0x023C, 0x008C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2                                          = IOMUX_PAD(0x023C, 0x008C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                                            = IOMUX_PAD(0x023C, 0x008C, 0x04, 0x03C8, 0x01, 0x00),
+
+	MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                                          = IOMUX_PAD(0x0240, 0x0090, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                                            = IOMUX_PAD(0x0240, 0x0090, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO3__GPIO4_IO28                                                  = IOMUX_PAD(0x0240, 0x0090, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                                          = IOMUX_PAD(0x0244, 0x0094, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                                            = IOMUX_PAD(0x0244, 0x0094, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_CCM_CLKO4__GPIO4_IO29                                                  = IOMUX_PAD(0x0244, 0x0094, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET1_MDC__ENET1_MDC                                                   = IOMUX_PAD(0x0248, 0x0098, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDC__LPUART3_DCB_B                                               = IOMUX_PAD(0x0248, 0x0098, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDC__I3C2_SCL                                                    = IOMUX_PAD(0x0248, 0x0098, 0x02, 0x03CC, 0x00, 0x00),
+	MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                                             = IOMUX_PAD(0x0248, 0x0098, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0                                             = IOMUX_PAD(0x0248, 0x0098, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDC__GPIO4_IO0                                                   = IOMUX_PAD(0x0248, 0x0098, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDC__LPI2C1_SCL                                                  = IOMUX_PAD(0x0248, 0x0098, 0x06, 0x03E0, 0x00, 0x00),
+
+	MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO                                              = IOMUX_PAD(0x024C, 0x009C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDIO__LPUART3_RIN_B                                              = IOMUX_PAD(0x024C, 0x009C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDIO__I3C2_SDA                                                   = IOMUX_PAD(0x024C, 0x009C, 0x02, 0x03D0, 0x00, 0x00),
+	MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                                           = IOMUX_PAD(0x024C, 0x009C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1                                            = IOMUX_PAD(0x024C, 0x009C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDIO__GPIO4_IO1                                                  = IOMUX_PAD(0x024C, 0x009C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_MDIO__LPI2C1_SDA                                                 = IOMUX_PAD(0x024C, 0x009C, 0x06, 0x03E4, 0x00, 0x00),
+
+	MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                                          = IOMUX_PAD(0x0250, 0x00A0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD3__CAN2_TX                                                     = IOMUX_PAD(0x0250, 0x00A0, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                                             = IOMUX_PAD(0x0250, 0x00A0, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2                                             = IOMUX_PAD(0x0250, 0x00A0, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD3__GPIO4_IO3                                                   = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD3__LPI2C2_SCL                                                  = IOMUX_PAD(0x0250, 0x00A0, 0x06, 0x03E8, 0x00, 0x00),
+
+	MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                                          = IOMUX_PAD(0x0254, 0x00A4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK                                 = IOMUX_PAD(0x0254, 0x00A4, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD2__CAN2_RX                                                     = IOMUX_PAD(0x0254, 0x00A4, 0x02, 0x0364, 0x02, 0x00),
+	MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2                                             = IOMUX_PAD(0x0254, 0x00A4, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3                                             = IOMUX_PAD(0x0254, 0x00A4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD2__GPIO4_IO3                                                   = IOMUX_PAD(0x0254, 0x00A4, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD2__LPI2C2_SDA                                                  = IOMUX_PAD(0x0254, 0x00A4, 0x06, 0x03EC, 0x00, 0x00),
+
+	MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1                                             = IOMUX_PAD(0x0258, 0x00A8, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD1__LPUART3_RTS_B                                               = IOMUX_PAD(0x0258, 0x00A8, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD1__I3C2_PUR                                                    = IOMUX_PAD(0x0258, 0x00A8, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1                                             = IOMUX_PAD(0x0258, 0x00A8, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4                                             = IOMUX_PAD(0x0258, 0x00A8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD1__GPIO4_IO4                                                   = IOMUX_PAD(0x0258, 0x00A8, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD1__I3C2_PUR_B                                                  = IOMUX_PAD(0x0258, 0x00A8, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                                          = IOMUX_PAD(0x025C, 0x00AC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD0__LPUART3_TX                                                  = IOMUX_PAD(0x025C, 0x00AC, 0x01, 0x0474, 0x01, 0x00),
+	MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5                                             = IOMUX_PAD(0x025C, 0x00AC, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD0__GPIO4_IO5                                                   = IOMUX_PAD(0x025C, 0x00AC, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL                                    = IOMUX_PAD(0x0260, 0x00B0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B                                            = IOMUX_PAD(0x0260, 0x00B0, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6                                          = IOMUX_PAD(0x0260, 0x00B0, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TX_CTL__GPIO4_IO6                                                = IOMUX_PAD(0x0260, 0x00B0, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK                                               = IOMUX_PAD(0x0260, 0x00B0, 0x02, 0x043C, 0x00, 0x00),
+
+	MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK                          = IOMUX_PAD(0x0264, 0x00B4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER                                              = IOMUX_PAD(0x0264, 0x00B4, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7                                             = IOMUX_PAD(0x0264, 0x00B4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TXC__GPIO4_IO7                                                   = IOMUX_PAD(0x0264, 0x00B4, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TXC__LPSPI2_SIN                                                  = IOMUX_PAD(0x0264, 0x00B4, 0x02, 0x0440, 0x00, 0x00),
+
+	MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL                                    = IOMUX_PAD(0x0268, 0x00B8, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B                                            = IOMUX_PAD(0x0268, 0x00B8, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2                                         = IOMUX_PAD(0x0268, 0x00B8, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8                                          = IOMUX_PAD(0x0268, 0x00B8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RX_CTL__GPIO4_IO8                                                = IOMUX_PAD(0x0268, 0x00B8, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0                                              = IOMUX_PAD(0x0268, 0x00B8, 0x02, 0x0434, 0x00, 0x00),
+
+	MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC                                          = IOMUX_PAD(0x026C, 0x00BC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER                                              = IOMUX_PAD(0x026C, 0x00BC, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9                                             = IOMUX_PAD(0x026C, 0x00BC, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RXC__GPIO4_IO9                                                   = IOMUX_PAD(0x026C, 0x00BC, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RXC__LPSPI2_SOUT                                                 = IOMUX_PAD(0x026C, 0x00BC, 0x02, 0x0444, 0x00, 0x00),
+
+	MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                                          = IOMUX_PAD(0x0270, 0x00C0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD0__LPUART3_RX                                                  = IOMUX_PAD(0x0270, 0x00C0, 0x01, 0x0470, 0x01, 0x00),
+	MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                                            = IOMUX_PAD(0x0270, 0x00C0, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD0__GPIO4_IO10                                                  = IOMUX_PAD(0x0270, 0x00C0, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                                          = IOMUX_PAD(0x0274, 0x00C4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD1__LPUART3_CTS_B                                               = IOMUX_PAD(0x0274, 0x00C4, 0x01, 0x046C, 0x01, 0x00),
+	MX91_PAD_ENET1_RD1__LPTMR2_ALT1                                                 = IOMUX_PAD(0x0274, 0x00C4, 0x03, 0x0448, 0x00, 0x00),
+	MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                                            = IOMUX_PAD(0x0274, 0x00C4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD1__GPIO4_IO11                                                  = IOMUX_PAD(0x0274, 0x00C4, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                                          = IOMUX_PAD(0x0278, 0x00C8, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD2__LPTMR2_ALT2                                                 = IOMUX_PAD(0x0278, 0x00C8, 0x03, 0x044C, 0x00, 0x00),
+	MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                                            = IOMUX_PAD(0x0278, 0x00C8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD2__GPIO4_IO12                                                  = IOMUX_PAD(0x0278, 0x00C8, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                                          = IOMUX_PAD(0x027C, 0x00CC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER                                     = IOMUX_PAD(0x027C, 0x00CC, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD3__LPTMR2_ALT3                                                 = IOMUX_PAD(0x027C, 0x00CC, 0x03, 0x0450, 0x00, 0x00),
+	MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                                            = IOMUX_PAD(0x027C, 0x00CC, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_RD3__GPIO4_IO13                                                  = IOMUX_PAD(0x027C, 0x00CC, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET2_MDC__ENET2_MDC                                                   = IOMUX_PAD(0x0280, 0x00D0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDC__LPUART4_DCB_B                                               = IOMUX_PAD(0x0280, 0x00D0, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDC__SAI2_RX_SYNC                                                = IOMUX_PAD(0x0280, 0x00D0, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14                                            = IOMUX_PAD(0x0280, 0x00D0, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDC__GPIO4_IO14                                                  = IOMUX_PAD(0x0280, 0x00D0, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK                                            = IOMUX_PAD(0x0280, 0x00D0, 0x06, 0x04BC, 0x01, 0x00),
+
+	MX91_PAD_ENET2_MDIO__ENET2_MDIO                                                 = IOMUX_PAD(0x0284, 0x00D4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDIO__LPUART4_RIN_B                                              = IOMUX_PAD(0x0284, 0x00D4, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK                                               = IOMUX_PAD(0x0284, 0x00D4, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15                                           = IOMUX_PAD(0x0284, 0x00D4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDIO__GPIO4_IO15                                                 = IOMUX_PAD(0x0284, 0x00D4, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0                                         = IOMUX_PAD(0x0284, 0x00D4, 0x06, 0x0490, 0x01, 0x00),
+
+	MX91_PAD_ENET2_TD3__SAI2_RX_DATA0                                               = IOMUX_PAD(0x0288, 0x00D8, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16                                            = IOMUX_PAD(0x0288, 0x00D8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD3__GPIO4_IO16                                                  = IOMUX_PAD(0x0288, 0x00D8, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC                                          = IOMUX_PAD(0x0288, 0x00D8, 0x06, 0x04C0, 0x01, 0x00),
+	MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3                                             = IOMUX_PAD(0x0288, 0x00D8, 0x00, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2                                             = IOMUX_PAD(0x028C, 0x00DC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD2__ENET2_TX_CLK2                                               = IOMUX_PAD(0x028C, 0x00DC, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17                                            = IOMUX_PAD(0x028C, 0x00DC, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD2__GPIO4_IO17                                                  = IOMUX_PAD(0x028C, 0x00DC, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC                                          = IOMUX_PAD(0x028C, 0x00DC, 0x06, 0x04B8, 0x01, 0x00),
+
+	MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1                                             = IOMUX_PAD(0x0290, 0x00E0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD1__LPUART4_RTS_B                                               = IOMUX_PAD(0x0290, 0x00E0, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                                            = IOMUX_PAD(0x0290, 0x00E0, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD1__GPIO4_IO18                                                  = IOMUX_PAD(0x0290, 0x00E0, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1                                          = IOMUX_PAD(0x0290, 0x00E0, 0x06, 0x0494, 0x01, 0x00),
+
+	MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0                                             = IOMUX_PAD(0x0294, 0x00E4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD0__LPUART4_TX                                                  = IOMUX_PAD(0x0294, 0x00E4, 0x01, 0x0480, 0x01, 0x00),
+	MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                                            = IOMUX_PAD(0x0294, 0x00E4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD0__GPIO4_IO19                                                  = IOMUX_PAD(0x0294, 0x00E4, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2                                          = IOMUX_PAD(0x0294, 0x00E4, 0x06, 0x0498, 0x01, 0x00),
+
+	MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL                                       = IOMUX_PAD(0x0298, 0x00E8, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B                                            = IOMUX_PAD(0x0298, 0x00E8, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC                                             = IOMUX_PAD(0x0298, 0x00E8, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20                                         = IOMUX_PAD(0x0298, 0x00E8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TX_CTL__GPIO4_IO20                                               = IOMUX_PAD(0x0298, 0x00E8, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3                                       = IOMUX_PAD(0x0298, 0x00E8, 0x06, 0x049C, 0x01, 0x00),
+
+	MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC                                             = IOMUX_PAD(0x029C, 0x00EC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TXC__ENET2_TX_ER                                                 = IOMUX_PAD(0x029C, 0x00EC, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TXC__SAI2_TX_BCLK                                                = IOMUX_PAD(0x029C, 0x00EC, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21                                            = IOMUX_PAD(0x029C, 0x00EC, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TXC__GPIO4_IO21                                                  = IOMUX_PAD(0x029C, 0x00EC, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4                                          = IOMUX_PAD(0x029C, 0x00EC, 0x06, 0x04A0, 0x01, 0x00),
+
+	MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL                                       = IOMUX_PAD(0x02A0, 0x00F0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B                                            = IOMUX_PAD(0x02A0, 0x00F0, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0                                            = IOMUX_PAD(0x02A0, 0x00F0, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22                                         = IOMUX_PAD(0x02A0, 0x00F0, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RX_CTL__GPIO4_IO22                                               = IOMUX_PAD(0x02A0, 0x00F0, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5                                       = IOMUX_PAD(0x02A0, 0x00F0, 0x06, 0x04A4, 0x01, 0x00),
+
+	MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC                                             = IOMUX_PAD(0x02A4, 0x00F4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RXC__ENET2_RX_ER                                                 = IOMUX_PAD(0x02A4, 0x00F4, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                                            = IOMUX_PAD(0x02A4, 0x00F4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RXC__GPIO4_IO23                                                  = IOMUX_PAD(0x02A4, 0x00F4, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6                                          = IOMUX_PAD(0x02A4, 0x00F4, 0x06, 0x04A8, 0x01, 0x00),
+
+	MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0                                             = IOMUX_PAD(0x02A8, 0x00F8, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD0__LPUART4_RX                                                  = IOMUX_PAD(0x02A8, 0x00F8, 0x01, 0x047C, 0x01, 0x00),
+	MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                                            = IOMUX_PAD(0x02A8, 0x00F8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD0__GPIO4_IO24                                                  = IOMUX_PAD(0x02A8, 0x00F8, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7                                          = IOMUX_PAD(0x02A8, 0x00F8, 0x06, 0x04AC, 0x01, 0x00),
+
+	MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1                                             = IOMUX_PAD(0x02AC, 0x00FC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD1__SPDIF_IN                                                    = IOMUX_PAD(0x02AC, 0x00FC, 0x01, 0x04E4, 0x01, 0x00),
+	MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                                            = IOMUX_PAD(0x02AC, 0x00FC, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD1__GPIO4_IO25                                                  = IOMUX_PAD(0x02AC, 0x00FC, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8                                          = IOMUX_PAD(0x02AC, 0x00FC, 0x06, 0x04B0, 0x01, 0x00),
+
+	MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2                                             = IOMUX_PAD(0x02B0, 0x0100, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD2__LPUART4_CTS_B                                               = IOMUX_PAD(0x02B0, 0x0100, 0x01, 0x0478, 0x01, 0x00),
+	MX91_PAD_ENET2_RD2__SAI2_MCLK                                                   = IOMUX_PAD(0x02B0, 0x0100, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD2__MQS2_RIGHT                                                  = IOMUX_PAD(0x02B0, 0x0100, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                                            = IOMUX_PAD(0x02B0, 0x0100, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD2__GPIO4_IO26                                                  = IOMUX_PAD(0x02B0, 0x0100, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9                                          = IOMUX_PAD(0x02B0, 0x0100, 0x06, 0x04B4, 0x01, 0x00),
+
+	MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3                                             = IOMUX_PAD(0x02B4, 0x0104, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD3__SPDIF_OUT                                                   = IOMUX_PAD(0x02B4, 0x0104, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD3__SPDIF_IN                                                    = IOMUX_PAD(0x02B4, 0x0104, 0x02, 0x04E4, 0x02, 0x00),
+	MX91_PAD_ENET2_RD3__MQS2_LEFT                                                   = IOMUX_PAD(0x02B4, 0x0104, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                                            = IOMUX_PAD(0x02B4, 0x0104, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET2_RD3__GPIO4_IO27                                                  = IOMUX_PAD(0x02B4, 0x0104, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8                                               = IOMUX_PAD(0x02B8, 0x0108, 0x04, 0x038C, 0x01, 0x00),
+	MX91_PAD_SD1_CLK__GPIO3_IO8                                                     = IOMUX_PAD(0x02B8, 0x0108, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_CLK__USDHC1_CLK                                                    = IOMUX_PAD(0x02B8, 0x0108, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_CLK__LPSPI2_SCK                                                    = IOMUX_PAD(0x02B8, 0x0108, 0x03, 0x043C, 0x01, 0x00),
+
+	MX91_PAD_SD1_CMD__USDHC1_CMD                                                    = IOMUX_PAD(0x02BC, 0x010C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9                                               = IOMUX_PAD(0x02BC, 0x010C, 0x04, 0x0390, 0x01, 0x00),
+	MX91_PAD_SD1_CMD__GPIO3_IO9                                                     = IOMUX_PAD(0x02BC, 0x010C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_CMD__LPSPI2_SIN                                                    = IOMUX_PAD(0x02BC, 0x010C, 0x03, 0x0440, 0x01, 0x00),
+
+	MX91_PAD_SD1_DATA0__USDHC1_DATA0                                                = IOMUX_PAD(0x02C0, 0x0110, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10                                            = IOMUX_PAD(0x02C0, 0x0110, 0x04, 0x0394, 0x01, 0x00),
+	MX91_PAD_SD1_DATA0__GPIO3_IO10                                                  = IOMUX_PAD(0x02C0, 0x0110, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA0__LPSPI2_PCS0                                                 = IOMUX_PAD(0x02C0, 0x0110, 0x03, 0x0434, 0x01, 0x00),
+
+	MX91_PAD_SD1_DATA1__USDHC1_DATA1                                                = IOMUX_PAD(0x02C4, 0x0114, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11                                            = IOMUX_PAD(0x02C4, 0x0114, 0x04, 0x0398, 0x01, 0x00),
+	MX91_PAD_SD1_DATA1__GPIO3_IO11                                                  = IOMUX_PAD(0x02C4, 0x0114, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT                                       = IOMUX_PAD(0x02C4, 0x0114, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA1__LPSPI2_SOUT                                                 = IOMUX_PAD(0x02C4, 0x0114, 0x03, 0x0444, 0x01, 0x00),
+
+	MX91_PAD_SD1_DATA2__USDHC1_DATA2                                                = IOMUX_PAD(0x02C8, 0x0118, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12                                            = IOMUX_PAD(0x02C8, 0x0118, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA2__GPIO3_IO12                                                  = IOMUX_PAD(0x02C8, 0x0118, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY                                     = IOMUX_PAD(0x02C8, 0x0118, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA2__LPSPI2_PCS1                                                 = IOMUX_PAD(0x02C8, 0x0118, 0x03, 0x0438, 0x00, 0x00),
+
+	MX91_PAD_SD1_DATA3__USDHC1_DATA3                                                = IOMUX_PAD(0x02CC, 0x011C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                                            = IOMUX_PAD(0x02CC, 0x011C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13                                            = IOMUX_PAD(0x02CC, 0x011C, 0x04, 0x039C, 0x01, 0x00),
+	MX91_PAD_SD1_DATA3__GPIO3_IO13                                                  = IOMUX_PAD(0x02CC, 0x011C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA3__LPSPI1_PCS1                                                 = IOMUX_PAD(0x02CC, 0x011C, 0x03, 0x0424, 0x00, 0x00),
+
+	MX91_PAD_SD1_DATA4__USDHC1_DATA4                                                = IOMUX_PAD(0x02D0, 0x0120, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4                                            = IOMUX_PAD(0x02D0, 0x0120, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14                                            = IOMUX_PAD(0x02D0, 0x0120, 0x04, 0x03A0, 0x01, 0x00),
+	MX91_PAD_SD1_DATA4__GPIO3_IO14                                                  = IOMUX_PAD(0x02D0, 0x0120, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA4__LPSPI1_PCS0                                                 = IOMUX_PAD(0x02D0, 0x0120, 0x03, 0x0420, 0x00, 0x00),
+
+	MX91_PAD_SD1_DATA5__USDHC1_DATA5                                                = IOMUX_PAD(0x02D4, 0x0124, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5                                            = IOMUX_PAD(0x02D4, 0x0124, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA5__USDHC1_RESET_B                                              = IOMUX_PAD(0x02D4, 0x0124, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15                                            = IOMUX_PAD(0x02D4, 0x0124, 0x04, 0x03A4, 0x01, 0x00),
+	MX91_PAD_SD1_DATA5__GPIO3_IO15                                                  = IOMUX_PAD(0x02D4, 0x0124, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA5__LPSPI1_SIN                                                  = IOMUX_PAD(0x02D4, 0x0124, 0x03, 0x042C, 0x00, 0x00),
+
+	MX91_PAD_SD1_DATA6__USDHC1_DATA6                                                = IOMUX_PAD(0x02D8, 0x0128, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6                                            = IOMUX_PAD(0x02D8, 0x0128, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA6__USDHC1_CD_B                                                 = IOMUX_PAD(0x02D8, 0x0128, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16                                            = IOMUX_PAD(0x02D8, 0x0128, 0x04, 0x03A8, 0x01, 0x00),
+	MX91_PAD_SD1_DATA6__GPIO3_IO16                                                  = IOMUX_PAD(0x02D8, 0x0128, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA6__LPSPI1_SCK                                                  = IOMUX_PAD(0x02D8, 0x0128, 0x03, 0x0428, 0x00, 0x00),
+
+	MX91_PAD_SD1_DATA7__USDHC1_DATA7                                                = IOMUX_PAD(0x02DC, 0x012C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7                                            = IOMUX_PAD(0x02DC, 0x012C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA7__USDHC1_WP                                                   = IOMUX_PAD(0x02DC, 0x012C, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17                                            = IOMUX_PAD(0x02DC, 0x012C, 0x04, 0x03AC, 0x01, 0x00),
+	MX91_PAD_SD1_DATA7__GPIO3_IO17                                                  = IOMUX_PAD(0x02DC, 0x012C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_DATA7__LPSPI1_SOUT                                                 = IOMUX_PAD(0x02DC, 0x012C, 0x03, 0x0430, 0x00, 0x00),
+
+	MX91_PAD_SD1_STROBE__USDHC1_STROBE                                              = IOMUX_PAD(0x02E0, 0x0130, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS                                             = IOMUX_PAD(0x02E0, 0x0130, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18                                           = IOMUX_PAD(0x02E0, 0x0130, 0x04, 0x03B0, 0x01, 0x00),
+	MX91_PAD_SD1_STROBE__GPIO3_IO18                                                 = IOMUX_PAD(0x02E0, 0x0130, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_VSELECT__USDHC2_VSELECT                                            = IOMUX_PAD(0x02E4, 0x0134, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_VSELECT__USDHC2_WP                                                 = IOMUX_PAD(0x02E4, 0x0134, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_VSELECT__LPTMR2_ALT3                                               = IOMUX_PAD(0x02E4, 0x0134, 0x02, 0x0450, 0x01, 0x00),
+	MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                                          = IOMUX_PAD(0x02E4, 0x0134, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_VSELECT__GPIO3_IO19                                                = IOMUX_PAD(0x02E4, 0x0134, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1                                     = IOMUX_PAD(0x02E4, 0x0134, 0x06, 0x0368, 0x00, 0x00),
+
+	MX91_PAD_SD3_CLK__USDHC3_CLK                                                    = IOMUX_PAD(0x02E8, 0x0138, 0x00, 0x04E8, 0x01, 0x00),
+	MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK                                               = IOMUX_PAD(0x02E8, 0x0138, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_CLK__LPUART1_CTS_B                                                 = IOMUX_PAD(0x02E8, 0x0138, 0x02, 0x0454, 0x00, 0x00),
+	MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20                                              = IOMUX_PAD(0x02E8, 0x0138, 0x04, 0x03B4, 0x01, 0x00),
+	MX91_PAD_SD3_CLK__GPIO3_IO20                                                    = IOMUX_PAD(0x02E8, 0x0138, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD3_CMD__USDHC3_CMD                                                    = IOMUX_PAD(0x02EC, 0x013C, 0x00, 0x04EC, 0x01, 0x00),
+	MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                                              = IOMUX_PAD(0x02EC, 0x013C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_CMD__LPUART1_RTS_B                                                 = IOMUX_PAD(0x02EC, 0x013C, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21                                              = IOMUX_PAD(0x02EC, 0x013C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_CMD__GPIO3_IO21                                                    = IOMUX_PAD(0x02EC, 0x013C, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD3_DATA0__USDHC3_DATA0                                                = IOMUX_PAD(0x02F0, 0x0140, 0x00, 0x04F0, 0x01, 0x00),
+	MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0                                            = IOMUX_PAD(0x02F0, 0x0140, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_DATA0__LPUART2_CTS_B                                               = IOMUX_PAD(0x02F0, 0x0140, 0x02, 0x0460, 0x00, 0x00),
+	MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                                            = IOMUX_PAD(0x02F0, 0x0140, 0x04, 0x03B8, 0x01, 0x00),
+	MX91_PAD_SD3_DATA0__GPIO3_IO22                                                  = IOMUX_PAD(0x02F0, 0x0140, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD3_DATA1__USDHC3_DATA1                                                = IOMUX_PAD(0x02F4, 0x0144, 0x00, 0x04F4, 0x01, 0x00),
+	MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1                                            = IOMUX_PAD(0x02F4, 0x0144, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_DATA1__LPUART2_RTS_B                                               = IOMUX_PAD(0x02F4, 0x0144, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                                            = IOMUX_PAD(0x02F4, 0x0144, 0x04, 0x03BC, 0x01, 0x00),
+	MX91_PAD_SD3_DATA1__GPIO3_IO23                                                  = IOMUX_PAD(0x02F4, 0x0144, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD3_DATA2__USDHC3_DATA2                                                = IOMUX_PAD(0x02F8, 0x0148, 0x00, 0x04F8, 0x01, 0x00),
+	MX91_PAD_SD3_DATA2__LPI2C4_SDA                                                  = IOMUX_PAD(0x02F8, 0x0148, 0x02, 0x03FC, 0x01, 0x00),
+	MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2                                            = IOMUX_PAD(0x02F8, 0x0148, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                                            = IOMUX_PAD(0x02F8, 0x0148, 0x04, 0x03C0, 0x01, 0x00),
+	MX91_PAD_SD3_DATA2__GPIO3_IO24                                                  = IOMUX_PAD(0x02F8, 0x0148, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD3_DATA3__USDHC3_DATA3                                                = IOMUX_PAD(0x02FC, 0x014C, 0x00, 0x04FC, 0x01, 0x00),
+	MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3                                            = IOMUX_PAD(0x02FC, 0x014C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD3_DATA3__LPI2C4_SCL                                                  = IOMUX_PAD(0x02FC, 0x014C, 0x02, 0x03F8, 0x01, 0x00),
+	MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                                            = IOMUX_PAD(0x02FC, 0x014C, 0x04, 0x03C4, 0x01, 0x00),
+	MX91_PAD_SD3_DATA3__GPIO3_IO25                                                  = IOMUX_PAD(0x02FC, 0x014C, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_CD_B__USDHC2_CD_B                                                  = IOMUX_PAD(0x0300, 0x0150, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN                                      = IOMUX_PAD(0x0300, 0x0150, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CD_B__I3C2_SCL                                                     = IOMUX_PAD(0x0300, 0x0150, 0x02, 0x03CC, 0x01, 0x00),
+	MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0                                              = IOMUX_PAD(0x0300, 0x0150, 0x04, 0x036C, 0x01, 0x00),
+	MX91_PAD_SD2_CD_B__GPIO3_IO0                                                    = IOMUX_PAD(0x0300, 0x0150, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CD_B__LPI2C1_SCL                                                   = IOMUX_PAD(0x0300, 0x0150, 0x03, 0x03E0, 0x01, 0x00),
+
+	MX91_PAD_SD2_CLK__USDHC2_CLK                                                    = IOMUX_PAD(0x0304, 0x0154, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT                                      = IOMUX_PAD(0x0304, 0x0154, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CLK__I2C1_SDA                                                      = IOMUX_PAD(0x0304, 0x0154, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CLK__I3C2_SDA                                                      = IOMUX_PAD(0x0304, 0x0154, 0x02, 0x03D0, 0x01, 0x00),
+	MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1                                               = IOMUX_PAD(0x0304, 0x0154, 0x04, 0x0370, 0x01, 0x00),
+	MX91_PAD_SD2_CLK__GPIO3_IO1                                                     = IOMUX_PAD(0x0304, 0x0154, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                                         = IOMUX_PAD(0x0304, 0x0154, 0x06, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CLK__LPI2C1_SDA                                                    = IOMUX_PAD(0x0304, 0x0154, 0x03, 0x03E4, 0x01, 0x00),
+
+	MX91_PAD_SD2_CMD__USDHC2_CMD                                                    = IOMUX_PAD(0x0308, 0x0158, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN                                          = IOMUX_PAD(0x0308, 0x0158, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CMD__I3C2_PUR                                                      = IOMUX_PAD(0x0308, 0x0158, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CMD__I3C2_PUR_B                                                    = IOMUX_PAD(0x0308, 0x0158, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2                                               = IOMUX_PAD(0x0308, 0x0158, 0x04, 0x0374, 0x01, 0x00),
+	MX91_PAD_SD2_CMD__GPIO3_IO2                                                     = IOMUX_PAD(0x0308, 0x0158, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                                         = IOMUX_PAD(0x0308, 0x0158, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_DATA0__USDHC2_DATA0                                                = IOMUX_PAD(0x030C, 0x015C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT                                       = IOMUX_PAD(0x030C, 0x015C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA0__CAN2_TX                                                     = IOMUX_PAD(0x030C, 0x015C, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3                                             = IOMUX_PAD(0x030C, 0x015C, 0x04, 0x0378, 0x01, 0x00),
+	MX91_PAD_SD2_DATA0__GPIO3_IO3                                                   = IOMUX_PAD(0x030C, 0x015C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA0__LPUART1_TX                                                  = IOMUX_PAD(0x030C, 0x015C, 0x03, 0x045C, 0x00, 0x00),
+	MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                                       = IOMUX_PAD(0x030C, 0x015C, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_DATA1__USDHC2_DATA1                                                = IOMUX_PAD(0x0310, 0x0160, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN                                        = IOMUX_PAD(0x0310, 0x0160, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA1__CAN2_RX                                                     = IOMUX_PAD(0x0310, 0x0160, 0x02, 0x0364, 0x03, 0x00),
+	MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4                                             = IOMUX_PAD(0x0310, 0x0160, 0x04, 0x037C, 0x01, 0x00),
+	MX91_PAD_SD2_DATA1__GPIO3_IO4                                                   = IOMUX_PAD(0x0310, 0x0160, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA1__LPUART1_RX                                                  = IOMUX_PAD(0x0310, 0x0160, 0x03, 0x0458, 0x00, 0x00),
+	MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                                           = IOMUX_PAD(0x0310, 0x0160, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_DATA2__USDHC2_DATA2                                                = IOMUX_PAD(0x0314, 0x0164, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT                                       = IOMUX_PAD(0x0314, 0x0164, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA2__MQS2_RIGHT                                                  = IOMUX_PAD(0x0314, 0x0164, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5                                             = IOMUX_PAD(0x0314, 0x0164, 0x04, 0x0380, 0x01, 0x00),
+	MX91_PAD_SD2_DATA2__GPIO3_IO5                                                   = IOMUX_PAD(0x0314, 0x0164, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA2__LPUART2_TX                                                  = IOMUX_PAD(0x0314, 0x0164, 0x03, 0x0468, 0x00, 0x00),
+	MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                                           = IOMUX_PAD(0x0314, 0x0164, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_DATA3__USDHC2_DATA3                                                = IOMUX_PAD(0x0318, 0x0168, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA3__LPTMR2_ALT1                                                 = IOMUX_PAD(0x0318, 0x0168, 0x01, 0x0448, 0x01, 0x00),
+	MX91_PAD_SD2_DATA3__MQS2_LEFT                                                   = IOMUX_PAD(0x0318, 0x0168, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6                                             = IOMUX_PAD(0x0318, 0x0168, 0x04, 0x0384, 0x01, 0x00),
+	MX91_PAD_SD2_DATA3__GPIO3_IO6                                                   = IOMUX_PAD(0x0318, 0x0168, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_DATA3__LPUART2_RX                                                  = IOMUX_PAD(0x0318, 0x0168, 0x03, 0x0464, 0x00, 0x00),
+	MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET                                    = IOMUX_PAD(0x0318, 0x0168, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SD2_RESET_B__USDHC2_RESET_B                                            = IOMUX_PAD(0x031C, 0x016C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_RESET_B__LPTMR2_ALT2                                               = IOMUX_PAD(0x031C, 0x016C, 0x01, 0x044C, 0x01, 0x00),
+	MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7                                           = IOMUX_PAD(0x031C, 0x016C, 0x04, 0x0388, 0x01, 0x00),
+	MX91_PAD_SD2_RESET_B__GPIO3_IO7                                                 = IOMUX_PAD(0x031C, 0x016C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET                                 = IOMUX_PAD(0x031C, 0x016C, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_I2C1_SCL__LPI2C1_SCL                                                   = IOMUX_PAD(0x0320, 0x0170, 0x00, 0x03E0, 0x02, 0x00),
+	MX91_PAD_I2C1_SCL__I3C1_SCL                                                     = IOMUX_PAD(0x0320, 0x0170, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C1_SCL__LPUART1_DCB_B                                                = IOMUX_PAD(0x0320, 0x0170, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C1_SCL__TPM2_CH0                                                     = IOMUX_PAD(0x0320, 0x0170, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C1_SCL__GPIO1_IO0                                                    = IOMUX_PAD(0x0320, 0x0170, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_I2C1_SDA__LPI2C1_SDA                                                   = IOMUX_PAD(0x0324, 0x0174, 0x00, 0x03E4, 0x02, 0x00),
+	MX91_PAD_I2C1_SDA__I3C1_SDA                                                     = IOMUX_PAD(0x0324, 0x0174, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C1_SDA__LPUART1_RIN_B                                                = IOMUX_PAD(0x0324, 0x0174, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C1_SDA__TPM2_CH1                                                     = IOMUX_PAD(0x0324, 0x0174, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C1_SDA__GPIO1_IO1                                                    = IOMUX_PAD(0x0324, 0x0174, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_I2C2_SCL__LPI2C2_SCL                                                   = IOMUX_PAD(0x0328, 0x0178, 0x00, 0x03E8, 0x01, 0x00),
+	MX91_PAD_I2C2_SCL__I3C1_PUR                                                     = IOMUX_PAD(0x0328, 0x0178, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SCL__LPUART2_DCB_B                                                = IOMUX_PAD(0x0328, 0x0178, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SCL__TPM2_CH2                                                     = IOMUX_PAD(0x0328, 0x0178, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SCL__SAI1_RX_SYNC                                                 = IOMUX_PAD(0x0328, 0x0178, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SCL__GPIO1_IO3                                                    = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SCL__I3C1_PUR_B                                                   = IOMUX_PAD(0x0328, 0x0178, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_I2C2_SDA__LPI2C2_SDA                                                   = IOMUX_PAD(0x032C, 0x017C, 0x00, 0x03EC, 0x01, 0x00),
+	MX91_PAD_I2C2_SDA__LPUART2_RIN_B                                                = IOMUX_PAD(0x032C, 0x017C, 0x02, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SDA__TPM2_CH3                                                     = IOMUX_PAD(0x032C, 0x017C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SDA__SAI1_RX_BCLK                                                 = IOMUX_PAD(0x032C, 0x017C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SDA__GPIO1_IO3                                                    = IOMUX_PAD(0x032C, 0x017C, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_UART1_RXD__LPUART1_RX                                                  = IOMUX_PAD(0x0330, 0x0180, 0x00, 0x0458, 0x01, 0x00),
+	MX91_PAD_UART1_RXD__ELE_UART_RX                                                 = IOMUX_PAD(0x0330, 0x0180, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART1_RXD__LPSPI2_SIN                                                  = IOMUX_PAD(0x0330, 0x0180, 0x02, 0x0440, 0x02, 0x00),
+	MX91_PAD_UART1_RXD__TPM1_CH0                                                    = IOMUX_PAD(0x0330, 0x0180, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART1_RXD__GPIO1_IO4                                                   = IOMUX_PAD(0x0330, 0x0180, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_UART1_TXD__LPUART1_TX                                                  = IOMUX_PAD(0x0334, 0x0184, 0x00, 0x045C, 0x01, 0x00),
+	MX91_PAD_UART1_TXD__ELE_UART_TX                                                 = IOMUX_PAD(0x0334, 0x0184, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART1_TXD__LPSPI2_PCS0                                                 = IOMUX_PAD(0x0334, 0x0184, 0x02, 0x0434, 0x02, 0x00),
+	MX91_PAD_UART1_TXD__TPM1_CH1                                                    = IOMUX_PAD(0x0334, 0x0184, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART1_TXD__GPIO1_IO5                                                   = IOMUX_PAD(0x0334, 0x0184, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_UART2_RXD__LPUART2_RX                                                  = IOMUX_PAD(0x0338, 0x0188, 0x00, 0x0464, 0x01, 0x00),
+	MX91_PAD_UART2_RXD__LPUART1_CTS_B                                               = IOMUX_PAD(0x0338, 0x0188, 0x01, 0x0454, 0x01, 0x00),
+	MX91_PAD_UART2_RXD__LPSPI2_SOUT                                                 = IOMUX_PAD(0x0338, 0x0188, 0x02, 0x0444, 0x02, 0x00),
+	MX91_PAD_UART2_RXD__TPM1_CH2                                                    = IOMUX_PAD(0x0338, 0x0188, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART2_RXD__SAI1_MCLK                                                   = IOMUX_PAD(0x0338, 0x0188, 0x04, 0x04D4, 0x00, 0x00),
+	MX91_PAD_UART2_RXD__GPIO1_IO6                                                   = IOMUX_PAD(0x0338, 0x0188, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_UART2_TXD__LPUART2_TX                                                  = IOMUX_PAD(0x033C, 0x018C, 0x00, 0x0468, 0x01, 0x00),
+	MX91_PAD_UART2_TXD__LPUART1_RTS_B                                               = IOMUX_PAD(0x033C, 0x018C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART2_TXD__LPSPI2_SCK                                                  = IOMUX_PAD(0x033C, 0x018C, 0x02, 0x043C, 0x02, 0x00),
+	MX91_PAD_UART2_TXD__TPM1_CH3                                                    = IOMUX_PAD(0x033C, 0x018C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART2_TXD__GPIO1_IO7                                                   = IOMUX_PAD(0x033C, 0x018C, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_UART2_TXD__SAI3_TX_SYNC                                                = IOMUX_PAD(0x033C, 0x018C, 0x07, 0x04E0, 0x02, 0x00),
+
+	MX91_PAD_PDM_CLK__PDM_CLK                                                       = IOMUX_PAD(0x0340, 0x0190, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_CLK__MQS1_LEFT                                                     = IOMUX_PAD(0x0340, 0x0190, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_CLK__LPTMR1_ALT1                                                   = IOMUX_PAD(0x0340, 0x0190, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_CLK__GPIO1_IO8                                                     = IOMUX_PAD(0x0340, 0x0190, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_CLK__CAN1_TX                                                       = IOMUX_PAD(0x0340, 0x0190, 0x06, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0                                       = IOMUX_PAD(0x0344, 0x0194, 0x00, 0x04C4, 0x02, 0x00),
+	MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                                            = IOMUX_PAD(0x0344, 0x0194, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                                           = IOMUX_PAD(0x0344, 0x0194, 0x02, 0x0424, 0x01, 0x00),
+	MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                                           = IOMUX_PAD(0x0344, 0x0194, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                                           = IOMUX_PAD(0x0344, 0x0194, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9                                             = IOMUX_PAD(0x0344, 0x0194, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM0__CAN1_RX                                               = IOMUX_PAD(0x0344, 0x0194, 0x06, 0x0360, 0x01, 0x00),
+
+	MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1                                       = IOMUX_PAD(0x0348, 0x0198, 0x00, 0x04C8, 0x02, 0x00),
+	MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                                           = IOMUX_PAD(0x0348, 0x0198, 0x02, 0x0438, 0x01, 0x00),
+	MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                                           = IOMUX_PAD(0x0348, 0x0198, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3                                           = IOMUX_PAD(0x0348, 0x0198, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10                                            = IOMUX_PAD(0x0348, 0x0198, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1                                 = IOMUX_PAD(0x0348, 0x0198, 0x06, 0x0368, 0x01, 0x00),
+
+	MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC                                                = IOMUX_PAD(0x034C, 0x019C, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1                                               = IOMUX_PAD(0x034C, 0x019C, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXFS__LPSPI1_PCS0                                                 = IOMUX_PAD(0x034C, 0x019C, 0x02, 0x0420, 0x01, 0x00),
+	MX91_PAD_SAI1_TXFS__LPUART2_DTR_B                                               = IOMUX_PAD(0x034C, 0x019C, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXFS__MQS1_LEFT                                                   = IOMUX_PAD(0x034C, 0x019C, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXFS__GPIO1_IO11                                                  = IOMUX_PAD(0x034C, 0x019C, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SAI1_TXC__SAI1_TX_BCLK                                                 = IOMUX_PAD(0x0350, 0x01A0, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXC__LPUART2_CTS_B                                                = IOMUX_PAD(0x0350, 0x01A0, 0x01, 0x0460, 0x01, 0x00),
+	MX91_PAD_SAI1_TXC__LPSPI1_SIN                                                   = IOMUX_PAD(0x0350, 0x01A0, 0x02, 0x042C, 0x01, 0x00),
+	MX91_PAD_SAI1_TXC__LPUART1_DSR_B                                                = IOMUX_PAD(0x0350, 0x01A0, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXC__CAN1_RX                                                      = IOMUX_PAD(0x0350, 0x01A0, 0x04, 0x0360, 0x02, 0x00),
+	MX91_PAD_SAI1_TXC__GPIO1_IO12                                                   = IOMUX_PAD(0x0350, 0x01A0, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0                                               = IOMUX_PAD(0x0354, 0x01A4, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXD0__LPUART2_RTS_B                                               = IOMUX_PAD(0x0354, 0x01A4, 0x01, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXD0__LPSPI1_SCK                                                  = IOMUX_PAD(0x0354, 0x01A4, 0x02, 0x0428, 0x01, 0x00),
+	MX91_PAD_SAI1_TXD0__LPUART1_DTR_B                                               = IOMUX_PAD(0x0354, 0x01A4, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXD0__CAN1_TX                                                     = IOMUX_PAD(0x0354, 0x01A4, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXD0__GPIO1_IO13                                                  = IOMUX_PAD(0x0354, 0x01A4, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_TXD0__SAI1_MCLK                                                   = IOMUX_PAD(0x0354, 0x01A4, 0x06, 0x04D4, 0x01, 0x00),
+
+	MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0                                               = IOMUX_PAD(0x0358, 0x01A8, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_RXD0__SAI1_MCLK                                                   = IOMUX_PAD(0x0358, 0x01A8, 0x01, 0x04D4, 0x02, 0x00),
+	MX91_PAD_SAI1_RXD0__LPSPI1_SOUT                                                 = IOMUX_PAD(0x0358, 0x01A8, 0x02, 0x0430, 0x01, 0x00),
+	MX91_PAD_SAI1_RXD0__LPUART2_DSR_B                                               = IOMUX_PAD(0x0358, 0x01A8, 0x03, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_RXD0__MQS1_RIGHT                                                  = IOMUX_PAD(0x0358, 0x01A8, 0x04, 0x0000, 0x00, 0x00),
+	MX91_PAD_SAI1_RXD0__GPIO1_IO14                                                  = IOMUX_PAD(0x0358, 0x01A8, 0x05, 0x0000, 0x00, 0x00),
+
+	MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY                                               = IOMUX_PAD(0x035C, 0x01AC, 0x00, 0x0000, 0x00, 0x00),
+	MX91_PAD_WDOG_ANY__GPIO1_IO15                                                   = IOMUX_PAD(0x035C, 0x01AC, 0x05, 0x0000, 0x00, 0x00),
+};
+#endif  /* __ASM_ARCH_IMX91_PINS_H__ */

arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_IMX93
+#if defined(CONFIG_IMX93) || defined(CONFIG_IMX91)
 #define PAD_CTL_FSEL2		(0x2 << 7)
 #define PAD_CTL_FSEL3		(0x3 << 7)
 #define PAD_CTL_PUE		(0x1 << 9)

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -97,6 +97,12 @@ struct bd_info;
 #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
 #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
 
+#define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
+#define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
+#define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
+#define is_imx91() (is_cpu_type(MXC_CPU_IMX91) || is_cpu_type(MXC_CPU_IMX9111) || \
+	is_cpu_type(MXC_CPU_IMX9101) || is_cpu_type(MXC_CPU_IMX9121))
+
 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
 

arch/arm/include/asm/system.h

@@ -171,7 +171,7 @@ static inline unsigned int current_el(void)
 	return 3 & (el >> 2);
 }
 
-static inline unsigned int get_sctlr(void)
+static inline unsigned long get_sctlr(void)
 {
 	unsigned int el;
 	unsigned long val;

arch/arm/mach-apple/board.c

@@ -691,11 +691,12 @@ int dram_init_banksize(void)
 
 extern long fw_dtb_pointer;
 
-void *board_fdt_blob_setup(int *err)
+int board_fdt_blob_setup(void **fdtp)
 {
 	/* Return DTB pointer passed by m1n1 */
-	*err = 0;
-	return (void *)fw_dtb_pointer;
+	*fdtp = (void *)fw_dtb_pointer;
+
+	return 0;
 }
 
 void build_mem_map(void)

arch/arm/mach-aspeed/Kconfig

@@ -16,8 +16,8 @@ choice
 
 config ASPEED_AST2500
 	bool "Support Aspeed AST2500 SoC"
-	depends on DM_RESET
 	select CPU_ARM1176
+	select DM_RESET
 	help
 	  The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
 	  It is used as Board Management Controller on many server boards,

arch/arm/mach-imx/imx8/Kconfig

@@ -54,15 +54,8 @@ config TARGET_COLIBRI_IMX8X
 	select BOARD_LATE_INIT
 	select IMX8QXP
 
-config TARGET_DENEB
-	bool "Support i.MX8QXP Capricorn Deneb board"
-	select BINMAN
-	select BOARD_LATE_INIT
-	select FACTORYSET
-	select IMX8QXP
-
-config TARGET_GIEDI
-	bool "Support i.MX8QXP Capricorn Giedi board"
+config TARGET_CAPRICORN
+	bool "Support i.MX8QXP Capricorn board"
 	select BINMAN
 	select BOARD_LATE_INIT
 	select FACTORYSET

arch/arm/mach-imx/imx8/fdt.c

@@ -11,6 +11,8 @@
 #include <fdt_support.h>
 #include <linux/libfdt.h>
 #include <linux/printk.h>
+#include <cpu.h>
+#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -279,6 +281,134 @@ static int ft_add_optee_node(void *fdt, struct bd_info *bd)
 	return 0;
 }
 
+static int delete_node(void *blob, const char *node)
+{
+	int nodeoffset;
+	int err;
+
+	nodeoffset = fdt_path_offset(blob, node);
+	if (nodeoffset < 0)
+		return -ENXIO;
+
+	err = fdt_del_node(blob, nodeoffset);
+	if (err)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int change_property(void *blob, const char *node, const char *property,
+			   const void *value, int len)
+{
+	int nodeoffset;
+	int err;
+
+	nodeoffset = fdt_path_offset(blob, node);
+	if (nodeoffset < 0)
+		return -ENXIO;
+
+	err = fdt_setprop(blob, nodeoffset, property, value, len);
+	if (err)
+		return -EINVAL;
+
+	return 0;
+}
+
+static void update_fdt_gpu_industrial_frequencies(void *blob)
+{
+	u32 gpu_opp_table[6];
+	u32 gpu_assigned_clocks[2];
+	int err;
+
+	gpu_opp_table[0] = cpu_to_fdt32(625000); /* Normal Core Clock */
+	gpu_opp_table[1] = cpu_to_fdt32(0);
+	gpu_opp_table[2] = cpu_to_fdt32(625000); /* Normal Shader Clock */
+	gpu_opp_table[3] = cpu_to_fdt32(0);
+	gpu_opp_table[4] = cpu_to_fdt32(400000); /* Low Shader and Core Clock */
+	gpu_opp_table[5] = cpu_to_fdt32(0);
+
+	gpu_assigned_clocks[0] = cpu_to_fdt32(625000000); /* Core Clock */
+	gpu_assigned_clocks[1] = cpu_to_fdt32(625000000); /* Shader Clock */
+
+	err = change_property(blob, "/bus@53100000/gpu@53100000",
+			      "assigned-clock-rates", gpu_assigned_clocks,
+			      sizeof(gpu_assigned_clocks));
+	if (err && err != ENXIO)
+		printf("Failed to set assigned-clock-rates for GPU0: %s\n",
+		       fdt_strerror(err));
+
+	err = change_property(blob, "/bus@54100000/gpu@54100000",
+			      "assigned-clock-rates", gpu_assigned_clocks,
+			      sizeof(gpu_assigned_clocks));
+	if (err && err != ENXIO)
+		printf("Failed to set assigned-clock-rates for GPU1: %s\n",
+		       fdt_strerror(err));
+
+	err = change_property(blob, "/bus@54100000/imx8_gpu1_ss@80000000",
+			      "operating-points", &gpu_opp_table,
+			      sizeof(gpu_opp_table));
+	if (err && err != ENXIO)
+		printf("Failed to set operating-points for GPU: %s\n",
+		       fdt_strerror(err));
+}
+
+static void update_fdt_cpu_industrial_frequencies(void *blob)
+{
+	int err;
+
+	err = delete_node(blob, "/opp-table-0/opp-1200000000");
+	if (err && err != -ENXIO)
+		printf("Failed to delete 1.2 GHz node on A53: %s\n",
+		       fdt_strerror(err));
+
+	err = delete_node(blob, "/opp-table-1/opp-1596000000");
+	if (err && err != -ENXIO)
+		printf("Failed to delete 1.596 GHz node on A72: %s\n",
+		       fdt_strerror(err));
+}
+
+static void update_fdt_frequencies(void *blob)
+{
+	struct cpu_info cpu;
+	struct udevice *dev;
+	int err;
+
+	uclass_first_device(UCLASS_CPU, &dev);
+
+	err = cpu_get_info(dev, &cpu);
+	if (err) {
+		printf("Failed to get CPU info\n");
+		return;
+	}
+
+	/*
+	 * Differentiate between the automotive and industrial variants of the
+	 * i.MX8. The difference of these two CPUs is the maximum frequencies
+	 * for the CPU and GPU.
+	 * Core			Automotive [max. MHz]	Industrial [max. MHz]
+	 * A53			1200			1104
+	 * A72			1596			1296
+	 * GPU Core		800			625
+	 * GPU Shader		1000			625
+	 *
+	 * While the SCFW enforces these limits for the CPU, the OS cpufreq
+	 * driver remains unaware, causing a mismatch between reported and
+	 * actual frequencies. This is resolved by removing the unsupprted
+	 * frequencies from the device tree.
+	 *
+	 * The GPU frequencies are not enforced by the SCFW, therefore without
+	 * updating the device tree we overclock the GPU.
+	 *
+	 * Using the cpu_freq variable is the only know way to differentiate
+	 * between the automotive and industrial variants of the i.MX8.
+	 */
+	if (cpu.cpu_freq != 1104000000)
+		return;
+
+	update_fdt_cpu_industrial_frequencies(blob);
+	update_fdt_gpu_industrial_frequencies(blob);
+}
+
 int ft_system_setup(void *blob, struct bd_info *bd)
 {
 	int ret;
@@ -294,6 +424,8 @@ int ft_system_setup(void *blob, struct bd_info *bd)
 
 	update_fdt_with_owned_resources(blob);
 
+	update_fdt_frequencies(blob);
+
 	if (is_imx8qm()) {
 		ret = config_smmu_fdt(blob);
 		if (ret)

arch/arm/mach-imx/imx9/Kconfig

@@ -16,6 +16,12 @@ config IMX93
 	select IMX9
 	select ARMV8_SPL_EXCEPTION_VECTORS
 
+config IMX91
+	bool
+	select IMX9
+	select ARMV8_SPL_EXCEPTION_VECTORS
+
+
 config SYS_SOC
 	default "imx9"
 
@@ -23,6 +29,12 @@ choice
 	prompt  "NXP i.MX9 board select"
 	optional
 
+config TARGET_IMX91_11X11_EVK
+	bool "imx91_11x11_evk"
+	select OF_BOARD_FIXUP
+	select IMX91
+	imply OF_UPSTREAM
+
 config TARGET_IMX93_9X9_QSB
 	bool "imx93_qsb"
 	select OF_BOARD_FIXUP
@@ -45,9 +57,12 @@ config TARGET_PHYCORE_IMX93
 	bool "phycore_imx93"
 	select IMX93
 	select IMX9_LPDDR4X
+	select OF_BOARD_FIXUP
+	select OF_BOARD_SETUP
 
 endchoice
 
+source "board/freescale/imx91_evk/Kconfig"
 source "board/freescale/imx93_evk/Kconfig"
 source "board/freescale/imx93_qsb/Kconfig"
 source "board/phytec/phycore_imx93/Kconfig"

arch/arm/mach-imx/imx9/clock.c

@@ -30,6 +30,7 @@ static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
 	INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
 	INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
 	INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+	INT_PLL_RATE(800000000U, 1, 200, 6), /* 800Mhz */
 };
 
 static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
@@ -37,12 +38,14 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
 	FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
 	FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
 	FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+	FRAC_PLL_RATE(600000000U, 1, 200, 8, 0, 1), /* 600Mhz */
 	FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
 	FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
 	FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
 	FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
 	FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
 	FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
+	FRAC_PLL_RATE(200000000U, 1, 200, 24, 0, 1), /* 200Mhz */
 };
 
 /* return in khz */
@@ -723,7 +726,7 @@ struct imx_clk_setting imx_clk_ld_settings[] = {
 	/* SWO TRACE to 133M */
 	{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* M33 systetick to 24M */
-	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
 	/* NIC to 250M */
 	{NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
 	/* NIC_APB to 133M */
@@ -753,13 +756,17 @@ struct imx_clk_setting imx_clk_settings[] = {
 	 * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
 	 * generating MII clock at 2.5M
 	 */
-	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
+	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2, CLK_SOC_IMX93},
+	/* Wakeup AXI 250M*/
+	{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD0, 4, CLK_SOC_IMX91},
 	/* SWO TRACE to 133M */
 	{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
 	/* M33 systetick to 24M */
-	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
+	{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1, CLK_SOC_IMX93},
 	/* NIC to 400M */
-	{NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
+	{NIC_CLK_ROOT, SYS_PLL_PFD1, 2, CLK_SOC_IMX93},
+	/* NIC to 333M */
+	{NIC_CLK_ROOT, SYS_PLL_PFD0, 3, CLK_SOC_IMX91},
 	/* NIC_APB to 133M */
 	{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
 };
@@ -769,8 +776,12 @@ void bus_clock_init_low_drive(void)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
-		ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
-				 imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+		if (imx_clk_ld_settings[i].soc == CLK_SOC_ALL ||
+		    (is_imx91() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX91) ||
+		    (is_imx93() && imx_clk_ld_settings[i].soc == CLK_SOC_IMX93)) {
+			ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+					 imx_clk_ld_settings[i].src, imx_clk_ld_settings[i].div);
+		}
 	}
 }
 
@@ -779,8 +790,12 @@ void bus_clock_init(void)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
-		ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
-				 imx_clk_settings[i].src, imx_clk_settings[i].div);
+		if (imx_clk_settings[i].soc == CLK_SOC_ALL ||
+		    (is_imx91() && imx_clk_settings[i].soc == CLK_SOC_IMX91) ||
+		    (is_imx93() && imx_clk_settings[i].soc == CLK_SOC_IMX93)) {
+			ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
+					 imx_clk_settings[i].src, imx_clk_settings[i].div);
+		}
 	}
 }
 
@@ -857,7 +872,7 @@ u32 imx_get_fecclk(void)
 	return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
 }
 
-#if defined(CONFIG_IMX93) && defined(CONFIG_DWC_ETH_QOS)
+#if (CONFIG_IS_ENABLED(IMX93) || CONFIG_IS_ENABLED(IMX91)) && CONFIG_IS_ENABLED(DWC_ETH_QOS)
 static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interface_type)
 {
 	struct blk_ctrl_wakeupmix_regs *bctrl =
@@ -901,12 +916,12 @@ static int imx93_eqos_interface_init(struct udevice *dev, phy_interface_t interf
 
 int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
 {
-	if (IS_ENABLED(CONFIG_IMX93) &&
+	if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
 	    IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
 	    device_is_compatible(dev, "nxp,imx93-dwmac-eqos"))
 		return imx93_eqos_interface_init(dev, interface_type);
 
-	if (IS_ENABLED(CONFIG_IMX93) &&
+	if ((IS_ENABLED(CONFIG_IMX93) || IS_ENABLED(CONFIG_IMX91)) &&
 	    IS_ENABLED(CONFIG_FEC_MXC) &&
 	    device_is_compatible(dev, "fsl,imx93-fec"))
 		return 0;

arch/arm/mach-imx/imx9/container.cfg

@@ -6,6 +6,10 @@
 BOOT_FROM SD 0x400
 SOC_TYPE IMX9
 CONTAINER
+#ifdef CONFIG_IMX91
+IMAGE A55 bl31.bin 0x204C0000
+#else
 IMAGE A55 bl31.bin 0x204E0000
+#endif
 IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
-IMAGE A55 tee.bin 0x96000000
+IMAGE A55 tee.bin 0x96000000

arch/arm/mach-imx/imx9/imximage.cfg

@@ -5,6 +5,10 @@
 
 BOOT_FROM SD 0x400
 SOC_TYPE IMX9
+#ifdef CONFIG_IMX91
+APPEND mx91a0-ahab-container.img
+#else
 APPEND mx93a1-ahab-container.img
+#endif
 CONTAINER
-IMAGE A55 u-boot-spl-ddr.bin 0x2049A000
+IMAGE A55 u-boot-spl-ddr.bin CONFIG_SPL_TEXT_BASE

arch/arm/mach-imx/imx9/soc.c

@@ -118,6 +118,8 @@ u32 get_cpu_speed_grade_hz(void)
 
 	if (is_imx93())
 		max_speed = MHZ(1700);
+	else if (is_imx91())
+		max_speed = MHZ(1400);
 
 	/* In case the fuse of speed grade not programmed */
 	if (speed > max_speed)
@@ -195,7 +197,30 @@ static u32 get_cpu_variant_type(u32 type)
 
 	bool npu_disable = !!(val & BIT(13));
 	bool core1_disable = !!(val & BIT(15));
-	u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+	u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24);
+	u32 nxp_recog = (val & GENMASK(23, 16)) >> 16;
+
+	/* For iMX91 */
+	if (type == MXC_CPU_IMX91) {
+		switch (nxp_recog) {
+		case 0x9:
+		case 0xA:
+			type = MXC_CPU_IMX9111;
+			break;
+		case 0xD:
+		case 0xE:
+			type = MXC_CPU_IMX9121;
+			break;
+		case 0xF:
+		case 0x10:
+			type = MXC_CPU_IMX9101;
+			break;
+		default:
+			break;	/* 9131 as default */
+		}
+
+		return type;
+	}
 
 	/* Low performance 93 part */
 	if (((val >> 6) & 0x3F) == 0xE && npu_disable)
@@ -217,8 +242,14 @@ static u32 get_cpu_variant_type(u32 type)
 u32 get_cpu_rev(void)
 {
 	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+	u32 type;
 
-	return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
+	if ((gd->arch.soc_rev & 0xFFFF) == 0x9300)
+		type = MXC_CPU_IMX93;
+	else
+		type = MXC_CPU_IMX91;
+
+	return (get_cpu_variant_type(type) << 12) |
 		(CHIP_REV_1_0 + rev);
 }
 
@@ -539,7 +570,8 @@ int print_cpuinfo(void)
 
 	cpurev = get_cpu_rev();
 
-	printf("CPU:   i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
+	printf("CPU:   i.MX%s rev%d.%d\n", is_imx93() ? "93" : "91",
+	       (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
 
 	return 0;
 }
@@ -634,7 +666,7 @@ static int low_drive_freq_update(void *blob)
 	return 0;
 }
 
-#ifdef CONFIG_OF_BOARD_FIXUP
+#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93)
 #ifndef CONFIG_XPL_BUILD
 int board_fix_fdt(void *fdt)
 {
@@ -893,7 +925,9 @@ void disable_isolation(void)
 void soc_power_init(void)
 {
 	mix_power_init(MIX_PD_MEDIAMIX);
-	mix_power_init(MIX_PD_MLMIX);
+
+	if (is_imx93())
+		mix_power_init(MIX_PD_MLMIX);
 
 	disable_isolation();
 }
@@ -919,6 +953,9 @@ int m33_prepare(void)
 			(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
 	u32 val, i;
 
+	if (is_imx91())
+		return -ENODEV;
+
 	if (m33_is_rom_kicked())
 		return -EPERM;
 
@@ -1007,7 +1044,7 @@ enum imx9_soc_voltage_mode soc_target_voltage_mode(void)
 	u32 speed = get_cpu_speed_grade_hz();
 	enum imx9_soc_voltage_mode voltage = VOLT_OVER_DRIVE;
 
-	if (is_imx93()) {
+	if (is_imx93() || is_imx91()) {
 		if (speed == 1700000000)
 			voltage = VOLT_OVER_DRIVE;
 		else if (speed == 1400000000)

arch/arm/mach-imx/imx9/trdc.c

@@ -484,7 +484,7 @@ void trdc_init(void)
 	}
 }
 
-#if DEBUG
+#ifdef DEBUG
 int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
 {
 	struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);