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sunxi: sun4i: add missing sdelay() to clock_init_safe()

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This delay is required after switching the clock source.

See “A20 Reference manual v1.4” Page 50 / section
“1.5.4.16. CPU/AHB/APB0 CLOCK RATIO”: “If the clock
source is changed, at most to wait for 8 present running
clock cycles.”

This is already implemented in clock_set_pll1(), but was
still missing in clock_init_safe().

Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Ludwig Kormann 2024-02-01 09:45:50 +01:00 • committed by Andre Przywara
parent c93a6fc8f5
commit 3b08e66f69
1 changed files with 2 additions and 0 deletions
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2
arch/arm/mach-sunxi/clock_sun4i.c
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@ -25,6 +25,7 @@ void clock_init_safe(void)
APB0_DIV_1 << APB0_DIV_SHIFT | APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg); &ccm->cpu_ahb_apb0_cfg);
sdelay(20);
writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
sdelay(200); sdelay(200);
writel(AXI_DIV_1 << AXI_DIV_SHIFT | writel(AXI_DIV_1 << AXI_DIV_SHIFT |
@ -32,6 +33,7 @@ void clock_init_safe(void)
APB0_DIV_1 << APB0_DIV_SHIFT | APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg); &ccm->cpu_ahb_apb0_cfg);
sdelay(20);
#ifdef CONFIG_MACH_SUN7I #ifdef CONFIG_MACH_SUN7I
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif #endif