Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-19 03:15:00 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

clk: aspeed: Add support for SD clock

Browse source 
Add code to enable the SD clock on the ast2500 SoC.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
This commit is contained in:
Eddie James 2019-08-15 14:29:37 -05:00 • committed by Peng Fan
parent 6cf8a903c5
commit 38c9f08b41
3 changed files with 32 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
arch/arm/include/asm/arch-aspeed/scu_ast2500.h
View file

@ -22,6 +22,8 @@
#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_SDCLK_DIV_SHIFT 12
#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK 0x1f
#define SCU_HPLL_NUM_SHIFT 5
@ -107,6 +109,7 @@
#define SCU_CLKSTOP_MAC1 (1 << 20)
#define SCU_CLKSTOP_MAC2 (1 << 21)
#define SCU_CLKSTOP_SDCLK (1 << 27)
#define SCU_D2PLL_EXT1_OFF (1 << 0)
#define SCU_D2PLL_EXT1_BYPASS (1 << 1)

27
drivers/clk/aspeed/clk_ast2500.c
View file

@ -143,6 +143,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
case BCLK_SDCLK:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_SDCLK_DIV_MASK)
>> SCU_SDCLK_DIV_SHIFT);
rate = ast2500_get_hpll_rate(clkin,
readl(&priv->
scu->h_pll_param));
rate = rate / apb_div;
}
break;
case PCLK_UART1:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
@ -436,6 +447,22 @@ static int ast2500_clk_enable(struct clk *clk)
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case BCLK_SDCLK:
if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
ast_scu_unlock(priv->scu);
setbits_le32(&priv->scu->sysreset_ctrl1,
SCU_SYSRESET_SDIO);
udelay(100);
clrbits_le32(&priv->scu->clk_stop_ctrl1,
SCU_CLKSTOP_SDCLK);
mdelay(10);
clrbits_le32(&priv->scu->sysreset_ctrl1,
SCU_SYSRESET_SDIO);
ast_scu_lock(priv->scu);
}
break;
/*
* For MAC clocks the clock rate is
* configured based on whether RGMII or RMII mode has been selected

2
drivers/pinctrl/aspeed/pinctrl_ast2500.c
View file

@ -58,6 +58,8 @@ static const struct ast2500_group_config ast2500_groups[] = {
{ "MDIO1", 3, (1 << 31) | (1 << 30) },
{ "MAC2LINK", 1, (1 << 1) },
{ "MDIO2", 5, (1 << 2) },
{ "SD1", 5, (1 << 0) },
{ "SD2", 5, (1 << 1) },
};
static int ast2500_pinctrl_get_groups_count(struct udevice *dev)