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rockchip: rv1108: Convert to OF_UPSTREAM
Instead of using the local rv1108 devicetree copies from U-Boot, let's convert the rv1108 boards to OF_UPSTREAM so that the upstream kernel devicetrees can be used instead. Tested on a rv1108-elgin-r1 board. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Fabio Estevam
Kever Yang
parent
8719193045
commit
38b666577c
7 changed files with 3 additions and 725 deletions
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@ -98,10 +98,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \
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rk3368-geekbox.dtb \
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rk3368-px5-evb.dtb \
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dtb-$(CONFIG_ROCKCHIP_RV1108) += \
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rv1108-elgin-r1.dtb \
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rv1108-evb.dtb
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dtb-$(CONFIG_ROCKCHIP_RV1126) += \
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rv1126-edgeble-neu2-io.dtb
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@ -1,59 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "rv1108.dtsi"
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/ {
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model = "Elgin RV1108 R1 board";
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compatible = "elgin,rv1108-elgin", "rockchip,rv1108";
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x08000000>;
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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};
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&emmc {
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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bus-width = <8>;
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cap-mmc-highspeed;
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disable-wp;
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non-removable;
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status = "okay";
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};
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&u2phy {
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status = "okay";
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u2phy_otg: otg-port {
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status = "okay";
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};
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer_pullup>;
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status = "okay";
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};
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&usb20_otg {
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status = "okay";
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};
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&pinctrl {
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uart2m0 {
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uart2m0_xfer_pullup: uart2m0-xfer-pullup {
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rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
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<2 RK_PD1 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
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};
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};
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};
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@ -1,79 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "rv1108.dtsi"
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/ {
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model = "Rockchip RV1108 Evaluation board";
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compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x08000000>;
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};
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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vcc5v0_otg: vcc5v0-otg-drv {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-name = "vcc5v0_otg";
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gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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&gmac {
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status = "okay";
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clock_in_out = <0>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
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};
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&saradc {
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status = "okay";
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};
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&sfc {
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status = "okay";
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flash@0 {
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compatible = "gd25q256","jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <96000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&usb20_otg {
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vbus-supply = <&vcc5v0_otg>;
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status = "okay";
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};
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&usb_host_ehci {
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status = "okay";
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};
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&usb_host_ohci {
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status = "okay";
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};
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@ -1,581 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/rv1108-cru.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rv1108";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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spi0 = &sfc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@102a0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x102a0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x2000>;
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};
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uart2: serial@10210000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10210000 0x100>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "disabled";
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};
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uart1: serial@10220000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10220000 0x100>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart0: serial@10230000 {
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compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
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reg = <0x10230000 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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grf: syscon@10300000 {
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compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
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reg = <0x10300000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy: usb2-phy@100 {
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compatible = "rockchip,rv1108-usb2phy";
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reg = <0x100 0x0c>;
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clocks = <&cru SCLK_USBPHY>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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clock-output-names = "usbphy";
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rockchip,usbgrf = <&usbgrf>;
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status = "disabled";
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u2phy_otg: otg-port {
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "otg-mux";
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#phy-cells = <0>;
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status = "disabled";
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};
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u2phy_host: host-port {
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "linestate";
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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saradc: saradc@1038c000 {
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compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
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reg = <0x1038c000 0x100>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clock-frequency = <1000000>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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status = "disabled";
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};
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pmugrf: syscon@20060000 {
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compatible = "rockchip,rv1108-pmugrf", "syscon";
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reg = <0x20060000 0x1000>;
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};
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usbgrf: syscon@202a0000 {
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compatible = "rockchip,rv1108-usbgrf", "syscon";
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reg = <0x202a0000 0x1000>;
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};
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cru: clock-controller@20200000 {
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compatible = "rockchip,rv1108-cru";
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reg = <0x20200000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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emmc: dwmmc@30110000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30110000 0x4000>;
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status = "disabled";
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};
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sdio: dwmmc@30120000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30120000 0x4000>;
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status = "disabled";
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};
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sdmmc: dwmmc@30130000 {
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compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
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clock-freq-min-max = <400000 100000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x30130000 0x4000>;
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status = "disabled";
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};
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usb_host_ehci: usb@30140000 {
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compatible = "generic-ehci";
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reg = <0x30140000 0x20000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb_host_ohci: usb@30160000 {
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compatible = "generic-ohci";
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reg = <0x30160000 0x20000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb20_otg: usb@30180000 {
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compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
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reg = <0x30180000 0x40000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG>;
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clock-names = "otg";
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dr_mode = "otg";
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g-np-tx-fifo-size = <16>;
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g-rx-fifo-size = <280>;
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g-tx-fifo-size = <256 128 128 64 32 16>;
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g-use-dma;
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phys = <&u2phy_otg>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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sfc: sfc@301c0000 {
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compatible = "rockchip,sfc";
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reg = <0x301c0000 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
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clock-names = "clk_sfc", "hclk_sfc";
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pinctrl-0 = <&sfc_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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gmac: ethernet@30200000 {
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compatible = "rockchip,rv1108-gmac";
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_MAC>,
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
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<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
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clock-names = "stmmaceth",
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"mac_clk_rx", "mac_clk_tx",
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins>;
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phy-mode = "rmii";
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max-speed = <100>;
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status = "disabled";
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};
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gic: interrupt-controller@32010000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x32011000 0x1000>,
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<0x32012000 0x1000>,
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<0x32014000 0x2000>,
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<0x32016000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rv1108-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmugrf>;
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#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@20030000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20030000 0x100>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@10310000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x10310000 0x100>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@10320000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x10320000 0x100>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio3@10330000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x10330000 0x100>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <4>;
|
||||
};
|
||||
|
||||
pcfg_output_high: pcfg-output-high {
|
||||
output-high;
|
||||
};
|
||||
|
||||
pcfg_output_low: pcfg-output-low {
|
||||
output-low;
|
||||
};
|
||||
|
||||
pcfg_input_high: pcfg-input-high {
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
|
||||
gmac {
|
||||
rmii_pins: rmii-pins {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
|
||||
<1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
|
||||
<1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
|
||||
<1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2m1 {
|
||||
i2c2m1_xfer: i2c2m1-xfer {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2c2m1_gpio: i2c2m1-gpio {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2m05v {
|
||||
i2c2m05v_xfer: i2c2m05v-xfer {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
i2c2m05v_gpio: i2c2m05v-gpio {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
|
||||
<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
i2c3_xfer: i2c3-xfer {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sfc {
|
||||
sfc_pins: sfc-pins {
|
||||
rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
|
||||
<2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc_pwren: emmc-pwren {
|
||||
rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_bus1: emmc-bus1 {
|
||||
rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmmc-cd {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus1: sdmmc-bus1 {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
|
||||
<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts_gpio: uart0-rts-gpio {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart01rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2m0 {
|
||||
uart2m0_xfer: uart2m0-xfer {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2m1 {
|
||||
uart2m1_xfer: uart2m1-xfer {
|
||||
rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
|
||||
<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_5v {
|
||||
uart2_5v_cts: uart2_5v-cts {
|
||||
rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_5v_rts: uart2_5v-rts {
|
||||
rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -374,6 +374,7 @@ config ROCKCHIP_RV1108
|
|||
bool "Support Rockchip RV1108"
|
||||
select CPU_V7A
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply OF_UPSTREAM
|
||||
help
|
||||
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
|
||||
and a DSP.
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
|
|||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
|
||||
CONFIG_ENV_OFFSET=0x3F8000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rv1108-elgin-r1"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-elgin-r1"
|
||||
CONFIG_ROCKCHIP_RV1108=y
|
||||
CONFIG_ROCKCHIP_BOOT_MODE_REG=0
|
||||
CONFIG_TARGET_ELGIN_RV1108=y
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ CONFIG_TEXT_BASE=0x60000000
|
|||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rv1108-evb"
|
||||
CONFIG_ROCKCHIP_RV1108=y
|
||||
CONFIG_DEBUG_UART_BASE=0x10210000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue