arm: socfpga: Move Stratix10 and Agilex clock manager common code

Move Stratix10 and Agilex clock manager common code to new header file.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This commit is contained in:
Ley Foon Tan 2019-11-27 15:55:20 +08:00 committed by Marek Vasut
parent 975f66bb57
commit 38229994af
2 changed files with 26 additions and 13 deletions

View file

@ -1,12 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
*
*/
#ifndef _CLOCK_MANAGER_S10_
#define _CLOCK_MANAGER_S10_
#include <asm/arch/clock_manager_soc64.h>
/* Clock speed accessors */
unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
@ -14,18 +16,6 @@ unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
const unsigned int cm_get_osc_clk_hz(void);
const unsigned int cm_get_f2s_per_ref_clk_hz(void);
const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
const unsigned int cm_get_intosc_clk_hz(void);
const unsigned int cm_get_fpga_clk_hz(void);
#define CLKMGR_EOSC1_HZ 25000000
#define CLKMGR_INTOSC_HZ 460000000
#define CLKMGR_FPGA_CLK_HZ 50000000
/* Clock configuration accessors */
const struct cm_config * const cm_get_default_config(void);
struct cm_config {
/* main group */