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drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

Browse source 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2024-09-29 19:49:48 -06:00 • committed by Tom Rini
parent dac3ce976a
commit 371dc068bb
116 changed files with 289 additions and 289 deletions
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4
drivers/Makefile
View file

@ -47,7 +47,7 @@ obj-y += bus/
ifndef CONFIG_TPL_BUILD
ifndef CONFIG_VPL_BUILD
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_CPU) += cpu/
obj-$(CONFIG_SPL_CRYPTO) += crypto/
@ -80,7 +80,7 @@ obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/
endif
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += ata/
obj-$(CONFIG_DM_DEMO) += demo/

2
drivers/block/Makefile
View file

@ -9,7 +9,7 @@ ifndef CONFIG_$(SPL_)BLK
obj-$(CONFIG_SPL_LEGACY_BLOCK) += blk_legacy.o
endif
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_IDE) += ide.o
obj-$(CONFIG_RKMTD) += rkmtd.o
endif

2
drivers/bus/Makefile
View file

@ -3,7 +3,7 @@
# Makefile for the bus drivers.
#
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_TI_PWMSS) += ti-pwmss.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
endif

2
drivers/clk/altera/clk-agilex.c
View file

@ -242,7 +242,7 @@ static void clk_basic_init(struct udevice *dev,
if (!cfg)
return;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);

2
drivers/clk/altera/clk-agilex5.c
View file

@ -263,7 +263,7 @@ static void clk_basic_init(struct udevice *dev,
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
} else {
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);

2
drivers/clk/altera/clk-n5x.c
View file

@ -52,7 +52,7 @@ static void clk_basic_init(struct udevice *dev,
if (!cfg)
return;
#if IS_ENABLED(CONFIG_SPL_BUILD)
#if IS_ENABLED(CONFIG_XPL_BUILD)
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);

2
drivers/clk/clk-uclass.c
View file

@ -378,7 +378,7 @@ int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage)
* However, still set them for SPL. And still set them if explicitly
* asked.
*/
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
if (!(IS_ENABLED(CONFIG_XPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
if (stage != CLK_DEFAULTS_POST_FORCE)
return 0;

4
drivers/clk/clk_vexpress_osc.c
View file

@ -37,7 +37,7 @@ static ulong vexpress_osc_clk_get_rate(struct clk *clk)
return data;
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)
{
int err;
@ -64,7 +64,7 @@ static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)
static struct clk_ops vexpress_osc_clk_ops = {
.get_rate = vexpress_osc_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
.set_rate = vexpress_osc_clk_set_rate,
#endif
};

22
drivers/clk/clk_zynq.c
View file

@ -43,13 +43,13 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
enum zynq_clk_rclk {mio_clk, emio_clk};
#endif
struct zynq_clk_priv {
ulong ps_clk_freq;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
struct clk gem_emio_clk[2];
#endif
};
@ -75,7 +75,7 @@ static void *zynq_clk_get_register(enum zynq_clk id)
return &slcr_base->uart_clk_ctrl;
case spi0_clk ... spi1_clk:
return &slcr_base->spi_clk_ctrl;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case dci_clk:
return &slcr_base->dci_clk_ctrl;
case gem0_clk:
@ -150,7 +150,7 @@ static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
return priv->ps_clk_freq * mul;
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id)
{
u32 clk_ctrl, srcsel;
@ -199,7 +199,7 @@ static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv)
{
u32 clk_ctrl, div;
@ -223,7 +223,7 @@ static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv)
return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv)
{
u32 clk_ctrl, div0, div1;
@ -251,7 +251,7 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv,
if (!div0)
div0 = 1;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
if (two_divs) {
div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
if (!div1)
@ -268,7 +268,7 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv,
div1);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
{
struct clk *parent;
@ -366,7 +366,7 @@ static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id,
}
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_rate(struct clk *clk)
{
struct zynq_clk_priv *priv = dev_get_priv(clk->dev);
@ -502,7 +502,7 @@ static void zynq_clk_dump(struct udevice *dev)
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
.set_rate = zynq_clk_set_rate,
#endif
.enable = dummy_enable,
@ -514,7 +514,7 @@ static struct clk_ops zynq_clk_ops = {
static int zynq_clk_probe(struct udevice *dev)
{
struct zynq_clk_priv *priv = dev_get_priv(dev);
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
unsigned int i;
char name[16];
int ret;

6
drivers/clk/imx/clk-imx8mm.c
View file

@ -31,7 +31,7 @@ static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll1_out", };
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll1_out", "sys_pll3_out", };
@ -95,7 +95,7 @@ static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_
"sys_pll1_160m", "sys_pll1_200m", };
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
@ -357,7 +357,7 @@ static int imx8mm_clk_probe(struct udevice *dev)
imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MM_CLK_ENET_AXI,
imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
base + 0x8880));

6
drivers/clk/imx/clk-imx8mn.c
View file

@ -37,7 +37,7 @@ static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_2
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll_out", "sys_pll3_out", };
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll_out", "clk_ext4", };
@ -97,7 +97,7 @@ static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m"
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll_out", };
@ -359,7 +359,7 @@ static int imx8mn_clk_probe(struct udevice *dev)
imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MN_CLK_ENET_REF,
imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
base + 0xa980));

2
drivers/clk/imx/clk-imxrt1020.c
View file

@ -124,7 +124,7 @@ static int imxrt1020_clk_probe(struct udevice *dev)
clk_dm(IMXRT1020_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
struct clk *clk, *clk1;
clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);

2
drivers/clk/imx/clk-imxrt1050.c
View file

@ -180,7 +180,7 @@ static int imxrt1050_clk_probe(struct udevice *dev)
struct clk *clk, *clk1;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/* bypass pll1 before setting its rate */
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);

6
drivers/clk/rockchip/clk_px30.c
View file

@ -989,7 +989,7 @@ static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id,
return px30_peri_get_clk(priv, clk_id);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id)
{
struct px30_cru *cru = priv->cru;
@ -1261,7 +1261,7 @@ static ulong px30_clk_get_rate(struct clk *clk)
case HCLK_PERI_PRE:
rate = px30_peri_get_clk(priv, clk->id);
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case SCLK_CRYPTO:
case SCLK_CRYPTO_APK:
rate = px30_crypto_get_clk(priv, clk->id);
@ -1345,7 +1345,7 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
case HCLK_PERI_PRE:
ret = px30_peri_set_clk(priv, clk->id, rate);
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case SCLK_CRYPTO:
case SCLK_CRYPTO_APK:
ret = px30_crypto_set_clk(priv, clk->id, rate);

6
drivers/clk/rockchip/clk_rk3188.c
View file

@ -80,7 +80,7 @@ enum {
"divisors on line " __stringify(__LINE__));
/* Keep divisors as low as possible to reduce jitter and power usage */
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
#endif
@ -371,7 +371,7 @@ static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
return rockchip_spi_get_clk(cru, gclk_rate, periph);
}
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
bool has_bwadj)
{
@ -557,7 +557,7 @@ static int rk3188_clk_probe(struct udevice *dev)
return PTR_ERR(priv->grf);
priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_clk_plat *plat = dev_get_plat(dev);

8
drivers/clk/rockchip/clk_rk3288.c
View file

@ -223,7 +223,7 @@ static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
return 0;
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
#define VCO_MAX_KHZ 2200000
#define VCO_MIN_KHZ 440000
#define FREF_MAX_KHZ 2200000
@ -421,7 +421,7 @@ static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
return rockchip_i2s_get_clk(cru, gclk_rate);
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
@ -819,7 +819,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SPI2:
new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case SCLK_I2S0:
new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
break;
@ -973,7 +973,7 @@ static int rk3288_clk_probe(struct udevice *dev)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(priv->grf))
return PTR_ERR(priv->grf);
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_plat *plat = dev_get_plat(dev);

4
drivers/clk/rockchip/clk_rk3328.c
View file

@ -582,7 +582,7 @@ static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
return rk3328_spi_get_clk(cru);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id)
{
struct rk3328_cru *cru = priv->cru;
@ -746,7 +746,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_SPI:
ret = rk3328_spi_set_clk(priv->cru, rate);
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case DCLK_LCDC:
case ACLK_VOP_PRE:
case ACLK_VIO_PRE:

14
drivers/clk/rockchip/clk_rk3368.c
View file

@ -50,7 +50,7 @@ struct pll_div {
(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
"divisors on line " __stringify(__LINE__));
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
#if !defined(CONFIG_TPL_BUILD)
@ -88,7 +88,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
}
}
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
const struct pll_div *div)
{
@ -130,7 +130,7 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
}
#endif
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static void rkclk_init(struct rk3368_cru *cru)
{
u32 apllb, aplll, dpll, cpll, gpll;
@ -157,7 +157,7 @@ static void rkclk_init(struct rk3368_cru *cru)
}
#endif
#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
u32 div, con, con_id, rate;
@ -469,7 +469,7 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
case SCLK_SPI0 ... SCLK_SPI2:
rate = rk3368_spi_get_clk(priv->cru, clk->id);
break;
#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
@ -500,7 +500,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
#endif
#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
ret = rk3368_mmc_set_clk(clk, rate);
@ -586,7 +586,7 @@ static int rk3368_clk_probe(struct udevice *dev)
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
rkclk_init(priv->cru);
#endif

10
drivers/clk/rockchip/clk_rk3399.c
View file

@ -56,7 +56,7 @@ struct pll_div {
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
#if !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_XPL_BUILD)
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
#endif
@ -1464,7 +1464,7 @@ static int rk3399_clk_probe(struct udevice *dev)
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_XPL_BUILD)
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
@ -1658,7 +1658,7 @@ static struct clk_ops rk3399_pmuclk_ops = {
.set_rate = rk3399_pmuclk_set_rate,
};
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static void pmuclk_init(struct rk3399_pmucru *pmucru)
{
u32 pclk_div;
@ -1676,7 +1676,7 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru)
static int rk3399_pmuclk_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_XPL_BUILD)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
#endif
@ -1686,7 +1686,7 @@ static int rk3399_pmuclk_probe(struct udevice *dev)
priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
pmuclk_init(priv->pmucru);
#endif
return 0;

10
drivers/clk/rockchip/clk_rk3568.c
View file

@ -91,7 +91,7 @@ static struct rockchip_pll_clock rk3568_pll_clks[] = {
RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates),
};
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong
rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv,
ulong pll_id, ulong rate)
@ -1707,7 +1707,7 @@ static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate)
return rk3568_emmc_get_bclk(priv);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv)
{
struct rk3568_cru *cru = priv->cru;
@ -2413,7 +2413,7 @@ static ulong rk3568_clk_get_rate(struct clk *clk)
case TCLK_EMMC:
rate = OSC_HZ;
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case ACLK_VOP:
rate = rk3568_aclk_vop_get_clk(priv);
break;
@ -2594,7 +2594,7 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
case TCLK_EMMC:
ret = OSC_HZ;
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case ACLK_VOP:
ret = rk3568_aclk_vop_set_clk(priv, rate);
break;
@ -2894,7 +2894,7 @@ static void rk3568_clk_init(struct rk3568_clk_priv *priv)
priv->gpll_hz = GPLL_HZ;
}
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000);
if (ret < 0)
printf("Fail to set the ACLK_BUS clock.\n");

14
drivers/clk/rockchip/clk_rk3588.c
View file

@ -65,7 +65,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/*
* The SPLL is part of the SBUSCRU, not the main CRU and as
* such only directly accessible during the SPL stage.
@ -76,7 +76,7 @@ static struct rockchip_pll_clock rk3588_pll_clks[] = {
};
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
/*
*
* rational_best_approximation(31415, 10000,
@ -875,7 +875,7 @@ static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv,
return rk3588_mmc_get_clk(priv, clk_id);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
{
struct rk3588_cru *cru = priv->cru;
@ -1600,7 +1600,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk)
case CLK_GPU:
rate = 200000000;
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case CLK_AUX16M_0:
case CLK_AUX16M_1:
rate = rk3588_aux16m_get_clk(priv, clk->id);
@ -1760,7 +1760,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)
case CLK_150M_SRC:
ret = 0;
break;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
case CLK_AUX16M_0:
case CLK_AUX16M_1:
ret = rk3588_aux16m_set_clk(priv, clk->id, rate);
@ -1965,7 +1965,7 @@ static int rk3588_clk_probe(struct udevice *dev)
priv->sync_kernel = false;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru,
B0PLL, LPLL_HZ);
rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru,
@ -2051,7 +2051,7 @@ U_BOOT_DRIVER(rockchip_rk3588_cru) = {
.probe = rk3588_clk_probe,
};
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
#define SCRU_BASE 0xfd7d0000
#define SBUSCRU_BASE 0xfd7d8000

2
drivers/clk/sifive/sifive-prci.c
View file

@ -670,7 +670,7 @@ static int sifive_prci_probe(struct udevice *dev)
__prci_wrpll_read_cfg0(pd, pc->pwd);
}
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
if (device_is_compatible(dev, "sifive,fu740-c000-prci")) {
u32 prci_pll_reg;
unsigned long parent_rate;

4
drivers/clk/starfive/clk-jh7110-pll.c
View file

@ -348,10 +348,10 @@ struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
return ERR_PTR(ret);
}
if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0)
if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL0)
jh7110_pllx_set_rate(clk, 1000000000);
if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2)
if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL2)
jh7110_pllx_set_rate(clk, 1188000000);
return clk;

6
drivers/clk/stm32/clk-stm32mp1.c
View file

@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_XPL_BUILD)
/* activate clock tree initialization in the driver */
#define STM32MP1_CLOCK_TREE_INIT
#endif
@ -2279,7 +2279,7 @@ static int stm32mp1_clk_probe(struct udevice *dev)
dev_err(dev, "clock tree initialization failed (%d)\n", result);
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
#if defined(VERBOSE_DEBUG)
/* display debug information for probe after relocation */
if (gd->flags & GD_FLG_RELOC)
@ -2314,7 +2314,7 @@ static const struct clk_ops stm32mp1_clk_ops = {
.disable = stm32mp1_clk_disable,
.get_rate = stm32mp1_clk_get_rate,
.set_rate = stm32mp1_clk_set_rate,
#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD)
#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_XPL_BUILD)
.dump = stm32mp1_clk_dump,
#endif
};

4
drivers/core/ofnode.c
View file

@ -611,7 +611,7 @@ int ofnode_read_u32_array(ofnode node, const char *propname,
out_values, sz);
/* get the error right, but space is more important in SPL */
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
if (ret == -FDT_ERR_NOTFOUND)
return -EINVAL;
else if (ret == -FDT_ERR_BADLAYOUT)
@ -1468,7 +1468,7 @@ int ofnode_read_simple_size_cells(ofnode node)
bool ofnode_pre_reloc(ofnode node)
{
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_TPL_BUILD)
#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_TPL_BUILD)
/* for SPL and TPL the remaining nodes after the fdtgrep 1st pass
* had property bootph-all or bootph-pre-sram/bootph-pre-ram.
* They are removed in final dtb (fdtgrep 2nd pass)

2
drivers/crypto/fsl/jobdesc.c
View file

@ -207,7 +207,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
append_store(desc, dma_addr_out, storelen,
LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *plain_txt, uint8_t *enc_blob,
uint32_t in_sz)

6
drivers/crypto/fsl/jr.c
View file

@ -713,7 +713,7 @@ int sec_init_idx(uint8_t sec_idx)
ccsr_sec_t *sec = caam->sec;
uint32_t mcr = sec_in32(&sec->mcfgr);
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX8M)
uint32_t jrdid_ms = 0;
#endif
#ifdef CONFIG_FSL_CORENET
@ -745,14 +745,14 @@ int sec_init_idx(uint8_t sec_idx)
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX8M)
jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
#endif
jr_reset();
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/*
* For SPL Build, Set the Liodns in SEC JR0 for
* creating PAMU entries corresponding to these.

4
drivers/ddr/altera/sdram_gen5.c
View file

@ -20,7 +20,7 @@
#include "sequencer.h"
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
struct altera_gen5_sdram_priv {
struct ram_info info;
@ -651,4 +651,4 @@ U_BOOT_DRIVER(altera_gen5_sdram) = {
.priv_auto = sizeof(struct altera_gen5_sdram_priv),
};
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */

6
drivers/ddr/fsl/lc_common_dimm_params.c
View file

@ -409,18 +409,18 @@ compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
if (dimm_params[i].n_ranks) {
if (dimm_params[i].registered_dimm) {
temp1 = 1;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
printf("Detected RDIMM %s\n",
dimm_params[i].mpart);
#endif
} else {
temp2 = 1;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
printf("Detected UDIMM %s\n",
dimm_params[i].mpart);
#endif
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
puts(" ");
#endif
}

6
drivers/ddr/fsl/main.c
View file

@ -863,16 +863,16 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
if ((first_ctrl == 0) && (total_memory - 1 > (phys_size_t)~0ULL)) {
puts("Detected ");
print_size(total_memory, " of memory\n");
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
puts(" "); /* re-align to match init_dram print */
#endif
puts("This U-Boot only supports <= ");
print_size((unsigned long long)((phys_size_t)~0ULL)+1, " of DDR\n");
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
puts(" "); /* re-align to match init_dram print */
#endif
puts("You could rebuild it with CONFIG_PHYS_64BIT\n");
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
puts(" "); /* re-align to match init_dram print */
#endif
}

2
drivers/ddr/imx/imx8m/Makefile
View file

@ -4,7 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o
obj-y += ../phy/
endif

2
drivers/ddr/imx/imx8ulp/Makefile
View file

@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX8ULP_DRAM) += ddr_init.o
endif

2
drivers/ddr/imx/imx9/Makefile
View file

@ -4,7 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX9_DRAM) += ddr_init.o
obj-y += ../phy/
endif

2
drivers/ddr/imx/phy/Makefile
View file

@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
endif

44
drivers/ddr/marvell/a38x/Makefile
View file

@ -1,29 +1,29 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_SPL_BUILD) += mv_ddr_plat.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_sys_env_lib.o
obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_build_message.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_common.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_spd.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o
obj-$(CONFIG_SPL_BUILD) += xor.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr_plat.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr_sys_env_lib.o
obj-$(CONFIG_XPL_BUILD) += ddr3_debug.o
obj-$(CONFIG_XPL_BUILD) += ddr3_init.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_bist.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_centralization.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_db.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_hw_algo.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr_build_message.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr_common.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr_spd.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr_topology.o
obj-$(CONFIG_XPL_BUILD) += xor.o
obj-$(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) += old/
ifdef CONFIG_DDR4
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_mpr_pda_if.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_calibration.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_db.o
obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_leveling.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr4_mpr_pda_if.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_calibration.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_db.o
obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_leveling.o
endif

28
drivers/ddr/marvell/a38x/old/Makefile
View file

@ -2,20 +2,20 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SPL_BUILD) += ddr3_a38x.o
obj-$(CONFIG_SPL_BUILD) += ddr3_a38x_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
obj-$(CONFIG_SPL_BUILD) += ddr3_hws_hw_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o
obj-$(CONFIG_XPL_BUILD) += ddr3_a38x.o
obj-$(CONFIG_XPL_BUILD) += ddr3_a38x_training.o
obj-$(CONFIG_XPL_BUILD) += ddr3_debug.o
obj-$(CONFIG_XPL_BUILD) += ddr3_hws_hw_training.o
obj-$(CONFIG_XPL_BUILD) += ddr3_init.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_bist.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_centralization.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_db.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_hw_algo.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_ip_engine.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_leveling.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_pbs.o
obj-$(CONFIG_XPL_BUILD) += ddr3_training_static.o
define IncludeSymbolRename
CFLAGS_$(1) = -include $(srctree)/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h

20
drivers/ddr/marvell/axp/Makefile
View file

@ -1,12 +1,12 @@
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_SPL_BUILD) += ddr3_dfs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_dqs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_hw_training.o
obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
obj-$(CONFIG_SPL_BUILD) += ddr3_pbs.o
obj-$(CONFIG_SPL_BUILD) += ddr3_read_leveling.o
obj-$(CONFIG_SPL_BUILD) += ddr3_sdram.o
obj-$(CONFIG_SPL_BUILD) += ddr3_spd.o
obj-$(CONFIG_SPL_BUILD) += ddr3_write_leveling.o
obj-$(CONFIG_SPL_BUILD) += xor.o
obj-$(CONFIG_XPL_BUILD) += ddr3_dfs.o
obj-$(CONFIG_XPL_BUILD) += ddr3_dqs.o
obj-$(CONFIG_XPL_BUILD) += ddr3_hw_training.o
obj-$(CONFIG_XPL_BUILD) += ddr3_init.o
obj-$(CONFIG_XPL_BUILD) += ddr3_pbs.o
obj-$(CONFIG_XPL_BUILD) += ddr3_read_leveling.o
obj-$(CONFIG_XPL_BUILD) += ddr3_sdram.o
obj-$(CONFIG_XPL_BUILD) += ddr3_spd.o
obj-$(CONFIG_XPL_BUILD) += ddr3_write_leveling.o
obj-$(CONFIG_XPL_BUILD) += xor.o

10
drivers/firmware/firmware-zynqmp.c
View file

@ -260,7 +260,7 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
int err;
u32 ret_payload[PAYLOAD_ARG_CNT];
if (IS_ENABLED(CONFIG_SPL_BUILD))
if (IS_ENABLED(CONFIG_XPL_BUILD))
printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size));
@ -282,7 +282,7 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
if (ret_payload[0])
printf("PMUFW returned 0x%08x status!\n", ret_payload[0]);
if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_SPL_BUILD))
if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_XPL_BUILD))
panic("PMUFW config object loading failed in EL3\n");
return 0;
@ -354,7 +354,7 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n",
__func__, current_el(), api_id, arg0, arg1, arg2, arg3);
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
#if defined(CONFIG_ZYNQMP_IPI)
/*
* Use fixed payload and arg size as the EL2 call. The firmware
@ -416,10 +416,10 @@ static int zynqmp_firmware_bind(struct udevice *dev)
int ret;
struct udevice *child;
if ((IS_ENABLED(CONFIG_SPL_BUILD) &&
if ((IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) ||
(!IS_ENABLED(CONFIG_SPL_BUILD) &&
(!IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) {
ret = device_bind_driver_to_node(dev, "zynqmp_power_domain",
"zynqmp_power_domain",

2
drivers/fpga/intel_sdm_mb.c
View file

@ -17,7 +17,7 @@
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
#define BITSTREAM_CHUNK_SIZE 0xFFFF0
#define RECONFIG_STATUS_POLL_RETRY_MAX 100

6
drivers/fpga/zynqpl.c
View file

@ -414,13 +414,13 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
if (bstype != BIT_PARTIAL)
zynq_slcr_devcfg_enable();
if (!IS_ENABLED(CONFIG_SPL_BUILD))
if (!IS_ENABLED(CONFIG_XPL_BUILD))
puts("INFO:post config was not run, please run manually if needed\n");
return FPGA_SUCCESS;
}
#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD)
static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fsinfo)
{
@ -504,7 +504,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
struct xilinx_fpga_op zynq_op = {
.load = zynq_load,
#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD)
.loadfs = zynq_loadfs,
#endif
};

2
drivers/gpio/Makefile
View file

@ -3,7 +3,7 @@
# Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
obj-$(CONFIG_DM_74X164) += 74x164_gpio.o

4
drivers/gpio/gpio-uclass.c
View file

@ -412,7 +412,7 @@ int dm_gpio_request(struct gpio_desc *desc, const char *label)
static int dm_gpio_requestf(struct gpio_desc *desc, const char *fmt, ...)
{
#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
va_list args;
char buf[40];
@ -461,7 +461,7 @@ int gpio_request(unsigned gpio, const char *label)
*/
int gpio_requestf(unsigned gpio, const char *fmt, ...)
{
#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
va_list args;
char buf[40];

2
drivers/gpio/pca953x.c
View file

@ -143,7 +143,7 @@ int pca953x_get_val(uint8_t chip)
return (int)val;
}
#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_XPL_BUILD)
/*
* Display pca953x information
*/

4
drivers/gpio/rk_gpio.c
View file

@ -126,7 +126,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
}
/* Simple SPL interface to GPIOs */
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
enum {
PULL_NONE_1V8 = 0,
@ -169,7 +169,7 @@ int spl_gpio_output(void *vregs, uint gpio, int value)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
static int rockchip_gpio_probe(struct udevice *dev)
{

10
drivers/gpio/s5p_gpio.c
View file

@ -92,7 +92,7 @@ static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
writel(value, &bank->dat);
}
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/* Common GPIO API - SPL does not support driver model yet */
int gpio_set_value(unsigned gpio, int value)
{
@ -118,7 +118,7 @@ static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
value = readl(&bank->dat);
return !!(value & DAT_MASK(gpio));
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
{
@ -185,7 +185,7 @@ int s5p_gpio_get_pin(unsigned gpio)
}
/* Driver model interface */
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
/* set GPIO pin 'gpio' as an input */
static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
{
@ -230,7 +230,7 @@ static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
return 0;
}
#endif /* nCONFIG_SPL_BUILD */
#endif /* nCONFIG_XPL_BUILD */
/*
* There is no common GPIO API for pull, drv, pin, rate (yet). These
@ -260,7 +260,7 @@ void gpio_set_rate(int gpio, int mode)
s5p_gpio_get_pin(gpio), mode);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct exynos_bank_info *state = dev_get_priv(dev);

2
drivers/gpio/sunxi_gpio.c
View file

@ -245,7 +245,7 @@ int sunxi_name_to_gpio(const char *name)
{
unsigned int gpio;
int ret;
#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO
char lookup[8];
if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {

2
drivers/gpio/tca642x.c
View file

@ -164,7 +164,7 @@ int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[])
return ret;
}
#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_XPL_BUILD)
/*
* Display tca642x information
*/

2
drivers/gpio/tegra_gpio.c
View file

@ -323,7 +323,7 @@ static int gpio_tegra_bind(struct udevice *parent)
return 0;
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
bank_count = TEGRA_GPIO_BANKS;
#else

2
drivers/input/Makefile
View file

@ -8,7 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += key_matrix.o
obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o
obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o
obj-$(CONFIG_I8042_KEYB) += i8042.o

6
drivers/mailbox/zynqmp-ipi.c
View file

@ -108,7 +108,7 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
writel(msg->buf[i], &mbx[i]);
/* Use SMC calls for Exception Level less than 3 where TF-A is available */
if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) {
ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0);
debug("%s, send %ld bytes\n", __func__, msg->len);
@ -148,7 +148,7 @@ static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data)
msg->buf[i] = readl(&mbx[i]);
/* Ack to remote if EL is not 3 */
if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) {
ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK,
IPI_SMC_ACK_EIRQ_MASK);
}
@ -168,7 +168,7 @@ static int zynqmp_ipi_dest_probe(struct udevice *dev)
node = dev_ofnode(dev);
if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
if (IS_ENABLED(CONFIG_XPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
zynqmp->el3_supported = true;
ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id);

6
drivers/misc/Makefile
View file

@ -10,7 +10,7 @@ obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += sandbox_adder.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
@ -19,13 +19,13 @@ obj-$(CONFIG_SANDBOX) += swap_case.o
endif
ifdef CONFIG_$(SPL_)DM_I2C
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
obj-$(CONFIG_USB_HUB_USB251XB) += usb251xb.o
endif
endif
ifdef CONFIG_SPL_OF_PLATDATA
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif

2
drivers/misc/gsc.c
View file

@ -389,7 +389,7 @@ static int gsc_probe(struct udevice *dev)
if (priv->rtc)
dev_set_priv(priv->rtc, priv);
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
gsc_banner(dev);
#endif

2
drivers/misc/imx8/scu.c
View file

@ -191,7 +191,7 @@ static int imx8_scu_probe(struct udevice *dev)
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
#else
plat->base = (struct mu_type *)addr;

2
drivers/mmc/Makefile
View file

@ -20,7 +20,7 @@ endif
obj-$(CONFIG_SUPPORT_EMMC_BOOT) += mmc_boot.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
endif

4
drivers/mmc/mmc-uclass.c
View file

@ -301,7 +301,7 @@ struct mmc *find_mmc_device(int dev_num)
ret = blk_find_device(UCLASS_MMC, dev_num, &dev);
if (ret) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC Device %d not found\n", dev_num);
#endif
return NULL;
@ -373,7 +373,7 @@ void mmc_do_preinit(void)
}
}
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
void print_mmc_devices(char separator)
{
struct udevice *dev;

20
drivers/mmc/mmc.c
View file

@ -328,7 +328,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
break;
if (status & MMC_STATUS_MASK) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("Status Error: %#08x\n", status);
#endif
return -ECOMM;
@ -341,7 +341,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
}
if (timeout_ms <= 0) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("Timeout waiting card ready\n");
#endif
return -ETIMEDOUT;
@ -483,7 +483,7 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
if (blkcnt > 1) {
if (mmc_send_stop_transmission(mmc, false)) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("mmc fail to send stop cmd\n");
#endif
return 0;
@ -534,7 +534,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
return 0;
if ((start + blkcnt) > block_dev->lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
start + blkcnt, block_dev->lba);
#endif
@ -2424,7 +2424,7 @@ static int mmc_startup_v4(struct mmc *mmc)
mmc->capacity_gp[i] <<= 19;
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
if (part_completed) {
mmc->enh_user_size =
(ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
@ -2723,7 +2723,7 @@ static int mmc_startup(struct mmc *mmc)
bdesc->blksz = mmc->read_bl_len;
bdesc->log2blksz = LOG2(bdesc->blksz);
bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
#if !defined(CONFIG_SPL_BUILD) || \
#if !defined(CONFIG_XPL_BUILD) || \
(defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
!CONFIG_IS_ENABLED(USE_TINY_PRINTF))
sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
@ -2741,7 +2741,7 @@ static int mmc_startup(struct mmc *mmc)
bdesc->revision[0] = 0;
#endif
#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
part_init(bdesc);
#endif
@ -2953,7 +2953,7 @@ retry:
err = mmc_send_op_cond(mmc);
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
if (!quiet)
log_err("Card did not respond to voltage select! : %d\n",
err);
@ -3008,7 +3008,7 @@ int mmc_start_init(struct mmc *mmc)
#endif
if (no_card) {
mmc->has_init = 0;
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("MMC: no card present\n");
#endif
return -ENOMEDIUM;
@ -3170,7 +3170,7 @@ int mmc_initialize(struct bd_info *bis)
if (ret)
return ret;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
print_mmc_devices(',');
#endif

4
drivers/mmc/mmc_legacy.c
View file

@ -44,7 +44,7 @@ struct mmc *find_mmc_device(int dev_num)
return m;
}
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC Device %d not found\n", dev_num);
#endif
@ -93,7 +93,7 @@ void mmc_list_add(struct mmc *mmc)
list_add_tail(&mmc->link, &mmc_devices);
}
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
void print_mmc_devices(char separator)
{
struct mmc *m;

2
drivers/mmc/mmc_private.h
View file

@ -67,7 +67,7 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
}
#endif
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
#ifdef CONFIG_MMC_TRACE
void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd);

4
drivers/mmc/omap_hsmmc.c
View file

@ -59,8 +59,8 @@
DECLARE_GLOBAL_DATA_PTR;
/* simplify defines to OMAP_HSMMC_USE_GPIO */
#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_XPL_BUILD)) || \
(defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO))
#define OMAP_HSMMC_USE_GPIO
#else
#undef OMAP_HSMMC_USE_GPIO

2
drivers/mmc/rockchip_dw_mmc.c
View file

@ -83,7 +83,7 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
return -EINVAL;
priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
if (!priv->fifo_mode)
priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
#endif

2
drivers/mmc/rockchip_sdhci.c
View file

@ -609,7 +609,7 @@ static int rockchip_sdhci_probe(struct udevice *dev)
* Disable use of DMA and force use of PIO mode in SPL to fix an issue
* where loading part of TF-A into SRAM using DMA silently fails.
*/
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
if (IS_ENABLED(CONFIG_XPL_BUILD) &&
dev_read_bool(dev, "u-boot,spl-fifo-mode"))
host->flags &= ~USE_DMA;

2
drivers/mmc/socfpga_dw_mmc.c
View file

@ -61,7 +61,7 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
int ret;
ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,

2
drivers/mmc/tmio-common.c
View file

@ -385,7 +385,7 @@ static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
return false;
}
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && !IS_ENABLED(CONFIG_ARM64)) {
/*
* For UniPhier ARMv7 SoCs, the stack is allocated in locked

4
drivers/mmc/uniphier-sd.c
View file

@ -36,7 +36,7 @@ static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv)
{
#if CONFIG_IS_ENABLED(CLK)
return clk_get_rate(&priv->clk);
#elif CONFIG_SPL_BUILD
#elif CONFIG_XPL_BUILD
return 100000000;
#else
return 0;
@ -50,7 +50,7 @@ static int uniphier_sd_probe(struct udevice *dev)
priv->clk_get_rate = uniphier_sd_clk_get_rate;
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
int ret;
ret = clk_get_by_index(dev, 0, &priv->clk);

6
drivers/mmc/zynq_sdhci.c
View file

@ -289,7 +289,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
{
int ret;
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0) {
ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
SD0_ITAPCHGWIN);
@ -339,7 +339,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
return zynqmp_mmio_write(SD_OTAP_DLY,
SD0_OTAPDLYSEL_MASK,
@ -356,7 +356,7 @@ static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
static inline int zynqmp_dll_reset(u32 node_id, u32 type)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
type == PM_DLL_RESET_ASSERT ?

2
drivers/mtd/Makefile
View file

@ -16,7 +16,7 @@ mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o
# U-Boot build
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
ifneq ($(mtd-y),)
obj-y += mtd.o

2
drivers/mtd/nand/Makefile
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
nandcore-objs := core.o bbt.o
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
obj-$(CONFIG_MTD_RAW_NAND) += raw/

2
drivers/mtd/nand/raw/Makefile
View file

@ -3,7 +3,7 @@
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
ifdef CONFIG_SPL_NAND_DRIVERS
NORMAL_DRIVERS=y

4
drivers/mtd/nand/raw/atmel_nand.c
View file

@ -1251,7 +1251,7 @@ static int at91_nand_ready(struct mtd_info *mtd)
}
#endif
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/* The following code is for SPL */
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
@ -1526,4 +1526,4 @@ void board_nand_init(void)
if (atmel_nand_chip_init(i, base_addr[i]))
log_err("atmel_nand: Fail to initialize #%d chip", i);
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */

6
drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
View file

@ -152,7 +152,7 @@ static void lpc32xx_nand_init(void)
&lpc32xx_nand_mlc_registers->time_reg);
}
#if !defined(CONFIG_SPL_BUILD)
#if !defined(CONFIG_XPL_BUILD)
/**
* lpc32xx_cmd_ctrl - write command to either cmd or data register
@ -606,7 +606,7 @@ void board_nand_init(void)
pr_err("nand_register returned %i", ret);
}
#else /* defined(CONFIG_SPL_BUILD) */
#else /* defined(CONFIG_XPL_BUILD) */
void nand_init(void)
{
@ -770,4 +770,4 @@ unsigned int nand_page_size(void)
return BYTES_PER_PAGE;
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */

8
drivers/mtd/nand/raw/lpc32xx_nand_slc.c
View file

@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = {
}
};
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
@ -162,7 +162,7 @@ static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
}
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
/*
* Prepares DMA descriptors for NAND RD/WR operations
* If the size is < 256 Bytes then it is assumed to be
@ -510,7 +510,7 @@ static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
*/
int board_nand_init(struct nand_chip *lpc32xx_chip)
{
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
int ret;
/* Acquire a channel for our use */
@ -533,7 +533,7 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
lpc32xx_chip->read_byte = lpc32xx_read_byte;
lpc32xx_chip->write_byte = lpc32xx_write_byte;
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
/* Hardware ECC calculation is supported when DMA driver is selected */
lpc32xx_chip->ecc.mode = NAND_ECC_HW;

10
drivers/mtd/nand/raw/nand_base.c
View file

@ -414,7 +414,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
{
struct nand_chip *chip = mtd_to_nand(mtd);
int ret = 0;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
int res;
#endif
@ -434,7 +434,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
nand_release_device(mtd);
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
/* Mark block bad in BBT */
if (chip->bbt) {
res = nand_markbad_bbt(mtd, ofs);
@ -488,7 +488,7 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
if (!chip->bbt)
return 0;
/* Return info from the table */
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
return nand_isreserved_bbt(mtd, ofs);
#else
return 0;
@ -518,7 +518,7 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
return chip->block_bad(mtd, ofs);
/* Return info from the table */
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
return nand_isbad_bbt(mtd, ofs, allowbbt);
#else
return 0;
@ -3729,7 +3729,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
if (!chip->read_buf || chip->read_buf == nand_read_buf)
chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
if (!chip->scan_bbt)
chip->scan_bbt = nand_default_bbt;
#endif

4
drivers/mtd/nand/raw/omap_gpmc.c
View file

@ -1011,7 +1011,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
return 0;
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
/*
* omap_nand_switch_ecc - switch the ECC operation between different engines
* (h/w and s/w) and different algorithms (hamming and BCHx)
@ -1072,7 +1072,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
err = nand_scan_tail(mtd);
return err;
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
/*
* Board-specific NAND initialization. The following members of the

2
drivers/mtd/nand/raw/sand_nand.c
View file

@ -680,7 +680,7 @@ void board_nand_init(void)
log_info("Failed to get sandbox NAND: %d\n", err);
}
#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
void nand_deselect(void)
{
nand_chip->select_chip(nand_to_mtd(nand_chip), -1);

2
drivers/mtd/onenand/Makefile
View file

@ -3,7 +3,7 @@
# Copyright (C) 2005-2007 Samsung Electronics.
# Kyungmin Park <kyungmin.park@samsung.com>
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
obj-$(CONFIG_SAMSUNG_ONENAND) += samsung.o
else

2
drivers/mtd/spi/Makefile
View file

@ -6,7 +6,7 @@
obj-$(CONFIG_$(SPL_TPL_)DM_SPI_FLASH) += sf-uclass.o
spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
ifeq ($(CONFIG_$(SPL_TPL_)SPI_FLASH_TINY),y)
spi-nor-y += spi-nor-tiny.o

2
drivers/mtd/spi/sf-uclass.c
View file

@ -54,7 +54,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
struct udevice *bus;
char *str;
#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF)
#if defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF)
str = "spi_flash";
#else
char name[30];

2
drivers/mtd/spi/sf_dataflash.c
View file

@ -438,7 +438,7 @@ static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
spi_flash->size = nr_pages * pagesize;
spi_flash->erase_size = pagesize;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
print_size(spi_flash->page_size, ", erase size ");
print_size(spi_flash->erase_size, ", total ");

4
drivers/mtd/spi/spi-nor-core.c
View file

@ -1030,7 +1030,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
while (len) {
schedule();
if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) {
if (!IS_ENABLED(CONFIG_XPL_BUILD) && ctrlc()) {
addr_known = false;
ret = -EINTR;
goto erase_err;
@ -4262,7 +4262,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->erase_size = mtd->erasesize;
nor->sector_size = mtd->erasesize;
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
printf("SF: Detected %s with page size ", nor->name);
print_size(nor->page_size, ", erase size ");
print_size(nor->erase_size, ", total ");

2
drivers/net/dwc_eth_xgmac_socfpga.c
View file

@ -37,7 +37,7 @@ static int dwxgmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
xgmac->syscon_phy_regshift;
if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
if (!(IS_ENABLED(CONFIG_XPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() -
SYSMGR_SOC64_EMAC0) >> 2;

2
drivers/net/dwmac_socfpga.c
View file

@ -68,7 +68,7 @@ static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
SYSMGR_SOC64_EMAC0) >> 2;

4
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View file

@ -671,7 +671,7 @@ const struct pinctrl_ops mtk_pinctrl_ops = {
};
#if CONFIG_IS_ENABLED(DM_GPIO) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
(defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO))
static int mtk_gpio_get(struct udevice *dev, unsigned int off)
{
int val, err;
@ -814,7 +814,7 @@ int mtk_pinctrl_common_probe(struct udevice *dev,
}
#if CONFIG_IS_ENABLED(DM_GPIO) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
(defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO))
ret = mtk_gpiochip_register(dev);
#endif

4
drivers/pinctrl/pinctrl_stm32.c
View file

@ -39,7 +39,7 @@ struct stm32_gpio_bank {
struct list_head list;
};
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static char pin_name[PINNAME_SIZE];
static const char * const pinmux_mode[GPIOF_COUNT] = {
@ -488,7 +488,7 @@ static struct pinctrl_ops stm32_pinctrl_ops = {
#else /* PINCTRL_FULL */
.set_state_simple = stm32_pinctrl_set_state_simple,
#endif /* PINCTRL_FULL */
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
.get_pin_name = stm32_pinctrl_get_pin_name,
.get_pins_count = stm32_pinctrl_get_pins_count,
.get_pin_muxing = stm32_pinctrl_get_pin_muxing,

2
drivers/pinctrl/tegra/Makefile
View file

@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
ifndef CONFIG_SPL_BUILD
ifndef CONFIG_XPL_BUILD
ifdef CONFIG_TEGRA20
obj-y += pinctrl-tegra20.o
else

2
drivers/pinctrl/uniphier/pinctrl-uniphier.h
View file

@ -126,7 +126,7 @@ struct uniphier_pinctrl_socdata {
#define __UNIPHIER_PINMUX_FUNCTION(func) #func
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
/*
* a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
* suppressing "defined but not used" warnings.

2
drivers/power/Makefile
View file

@ -9,7 +9,7 @@ obj-y += pmic/
obj-y += regulator/
obj-$(CONFIG_AXP221_POWER) += axp221.o
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP305_POWER) += axp_spl.o

4
drivers/power/pmic/rk8xx.c
View file

@ -237,7 +237,7 @@ static int rk8xx_bind(struct udevice *dev)
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
if (IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
@ -331,7 +331,7 @@ static int rk8xx_probe(struct udevice *dev)
pmic_reg_read(dev, init_data[i].reg));
}
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
printf("PMIC: RK%x ", show_variant);
if (on_source && off_source)
printf("(on=0x%02x, off=0x%02x)",

6
drivers/power/pmic/stpmic1.c
View file

@ -91,7 +91,7 @@ static int stpmic1_bind(struct udevice *dev)
dev_dbg(dev, "no child found\n");
#endif /* DM_REGULATOR */
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
ret = device_bind_driver(dev, "stpmic1-nvm",
"stpmic1-nvm", NULL);
if (ret)
@ -124,7 +124,7 @@ U_BOOT_DRIVER(pmic_stpmic1) = {
.ops = &stpmic1_ops,
};
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
enum pmic_nvm_op op)
{
@ -230,7 +230,7 @@ U_BOOT_DRIVER(stpmic1_nvm) = {
.id = UCLASS_MISC,
.ops = &stpmic1_nvm_ops,
};
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
#ifdef CONFIG_SYSRESET
static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)

2
drivers/power/power_core.c
View file

@ -78,7 +78,7 @@ struct pmic *pmic_get(const char *s)
return NULL;
}
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
static int pmic_dump(struct pmic *p)
{
int i, ret;

2
drivers/power/regulator/rk8xx.c
View file

@ -16,7 +16,7 @@
#include <power/pmic.h>
#include <power/regulator.h>
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_XPL_BUILD
#define ENABLE_DRIVER
#endif

2
drivers/power/sy8106a.c
View file

@ -10,7 +10,7 @@
#define SY8106A_VOUT1_SEL 1
#define SY8106A_VOUT1_SEL_ENABLE (1 << 7)
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div)
{
if (mvolt < min)

2
drivers/ram/Makefile
View file

@ -20,7 +20,7 @@ obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
endif

4
drivers/ram/mediatek/ddr3-mt7629.c
View file

@ -233,7 +233,7 @@ struct mtk_ddr3_priv {
struct clk mem_mux;
};
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
static int mtk_ddr3_rank_size_detect(struct udevice *dev)
{
struct mtk_ddr3_priv *priv = dev_get_priv(dev);
@ -697,7 +697,7 @@ static int mtk_ddr3_probe(struct udevice *dev)
if (priv->dramc_ao == FDT_ADDR_T_NONE)
return -EINVAL;
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
int ret;
ret = clk_get_by_index(dev, 0, &priv->phy);

12
drivers/ram/rockchip/sdram_rk3188.c
View file

@ -84,7 +84,7 @@ const int ddrconf_table[] = {
#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@ -851,7 +851,7 @@ static int rk3188_dmc_of_to_plat(struct udevice *dev)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_plat(struct udevice *dev)
@ -878,7 +878,7 @@ static int conv_of_plat(struct udevice *dev)
static int rk3188_dmc_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct regmap *map;
struct udevice *dev_clk;
@ -888,7 +888,7 @@ static int rk3188_dmc_probe(struct udevice *dev)
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_plat(dev);
if (ret)
@ -950,12 +950,12 @@ U_BOOT_DRIVER(rockchip_rk3188_dmc) = {
.id = UCLASS_RAM,
.of_match = rk3188_dmc_ids,
.ops = &rk3188_dmc_ops,
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
.of_to_plat = rk3188_dmc_of_to_plat,
#endif
.probe = rk3188_dmc_probe,
.priv_auto = sizeof(struct dram_info),
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_XPL_BUILD
.plat_auto = sizeof(struct rk3188_sdram_params),
#endif
};

12
drivers/ram/rockchip/sdram_rk3288.c
View file

@ -84,7 +84,7 @@ const int ddrconf_table[] = {
#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
@ -1013,7 +1013,7 @@ static int rk3288_dmc_of_to_plat(struct udevice *dev)
return 0;
}
#endif /* CONFIG_SPL_BUILD */
#endif /* CONFIG_XPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_plat(struct udevice *dev)
@ -1041,7 +1041,7 @@ static int conv_of_plat(struct udevice *dev)
static int rk3288_dmc_probe(struct udevice *dev)
{
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
struct rk3288_sdram_params *plat = dev_get_plat(dev);
struct udevice *dev_clk;
struct regmap *map;
@ -1051,7 +1051,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_plat(dev);
if (ret)
@ -1119,13 +1119,13 @@ U_BOOT_DRIVER(rockchip_rk3288_dmc) = {
.of_match = rk3288_dmc_ids,
.ops = &rk3288_dmc_ops,
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
.of_to_plat = rk3288_dmc_of_to_plat,
#endif
.probe = rk3288_dmc_probe,
.priv_auto = sizeof(struct dram_info),
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
.plat_auto = sizeof(struct rk3288_sdram_params),
#endif
};

2
drivers/ram/rockchip/sdram_rk3399.c
View file

@ -3196,7 +3196,7 @@ U_BOOT_DRIVER(dmc_rk3399) = {
.probe = rk3399_dmc_probe,
.priv_auto = sizeof(struct dram_info),
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
.plat_auto = sizeof(struct rockchip_dmc_plat),
#endif
};

6
drivers/ram/rockchip/sdram_rv1126.c
View file

@ -34,7 +34,7 @@
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
void __iomem *pctl;
void __iomem *phy;
struct rv1126_cru *cru;
@ -49,7 +49,7 @@ struct dram_info {
};
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
#define GRF_BASE_ADDR 0xfe000000
#define PMU_GRF_BASE_ADDR 0xfe020000
@ -3507,7 +3507,7 @@ error:
static int rv1126_dmc_probe(struct udevice *dev)
{
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
(!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
if (rv1126_dmc_init(dev))
return 0;
#else

6
drivers/ram/sifive/sifive_ddr.c
View file

@ -91,7 +91,7 @@ struct sifive_ddr_info {
u32 *physical_filter_ctrl;
};
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_XPL_BUILD)
struct sifive_ddr_params {
struct sifive_ddrctl pctl_regs;
struct sifive_ddrphy phy_regs;
@ -337,7 +337,7 @@ static int sifive_ddr_probe(struct udevice *dev)
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_XPL_BUILD)
int ret;
u32 clock = 0;
@ -404,7 +404,7 @@ U_BOOT_DRIVER(sifive_ddr) = {
.ops = &sifive_ddr_ops,
.probe = sifive_ddr_probe,
.priv_auto = sizeof(struct sifive_ddr_info),
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_XPL_BUILD)
.plat_auto = sizeof(struct sifive_dmc_plat),
#endif
};

2
drivers/ram/starfive/Makefile
View file

@ -2,7 +2,7 @@
#
# Copyright (c) 2022 StarFive, Inc
#
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o

2
drivers/ram/stm32mp1/stm32mp1_ram.c
View file

@ -371,7 +371,7 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
priv->info.base = STM32_DDR_BASE;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
if (IS_ENABLED(CONFIG_XPL_BUILD)) {
priv->info.size = 0;
ret = stm32mp1_ddr_setup(dev);

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