spi: Zap CONFIG_HARD_SPI

In legacy CONFIG_HARD_SPI initalizing spi_init code, which
was removed during dm conversion cleanup.

So remove the dead instances of CONFIG_HARD_SPI, and related
code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki 2018-11-24 14:31:12 +05:30
parent efbeabee79
commit 35f9d9bdd0
23 changed files with 2 additions and 84 deletions

8
README
View file

@ -1932,14 +1932,6 @@ The following options need to be configured:
SPI configuration items (port pins to use, etc). For SPI configuration items (port pins to use, etc). For
an example, see include/configs/sacsng.h. an example, see include/configs/sacsng.h.
CONFIG_HARD_SPI
Enables a hardware SPI driver for general-purpose reads
and writes. As with CONFIG_SOFT_SPI, the board configuration
must define a list of chip-select function pointers.
Currently supported on some MPC8xxx processors. For an
example, see include/configs/mpc8349emds.h.
CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_MXC_WAIT
Timeout for waiting until spi transfer completed. Timeout for waiting until spi transfer completed.
default: (CONFIG_SYS_HZ/100) /* 10 ms */ default: (CONFIG_SYS_HZ/100) /* 10 ms */

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@ -18,13 +18,6 @@
#define HWCONFIG_BUFFER_SIZE 256 #define HWCONFIG_BUFFER_SIZE 256
#endif #endif
/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
# ifndef CONFIG_HARD_SPI
# define CONFIG_HARD_SPI
# endif
#endif
#define CONFIG_LMB #define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_RAMDISK_HIGH

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@ -273,7 +273,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
iopd->dat |= SPI_CS_MASK; iopd->dat |= SPI_CS_MASK;
} }
#endif /* CONFIG_HARD_SPI */ #endif
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd) int ft_board_setup(void *blob, bd_t *bd)

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@ -208,4 +208,4 @@ void spi_cs_deactivate(struct spi_slave *slave)
/* deactivate the spi_cs */ /* deactivate the spi_cs */
setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
} }
#endif /* CONFIG_HARD_SPI */ #endif

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@ -257,15 +257,6 @@ __weak int init_func_vid(void)
} }
#endif #endif
#if defined(CONFIG_HARD_SPI)
static int init_func_spi(void)
{
puts("SPI: ");
puts("ready\n");
return 0;
}
#endif
static int setup_mon_len(void) static int setup_mon_len(void)
{ {
#if defined(__ARM__) || defined(__MICROBLAZE__) #if defined(__ARM__) || defined(__MICROBLAZE__)
@ -863,9 +854,6 @@ static const init_fnc_t init_sequence_f[] = {
#endif #endif
#if defined(CONFIG_VID) && !defined(CONFIG_SPL) #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
init_func_vid, init_func_vid,
#endif
#if defined(CONFIG_HARD_SPI)
init_func_spi,
#endif #endif
announce_dram_init, announce_dram_init,
dram_init, /* configure available RAM banks */ dram_init, /* configure available RAM banks */

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@ -102,7 +102,6 @@
/* DSPI and Serial Flash */ /* DSPI and Serial Flash */
#define CONFIG_CF_DSPI #define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7 #define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI #ifdef CONFIG_CMD_SPI
# define CONFIG_SYS_DSPI_CS2 # define CONFIG_SYS_DSPI_CS2

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@ -151,7 +151,6 @@
/* DSPI and Serial Flash */ /* DSPI and Serial Flash */
#define CONFIG_CF_DSPI #define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH #define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7 #define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI #ifdef CONFIG_CMD_SPI

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@ -116,7 +116,6 @@
/* DSPI and Serial Flash */ /* DSPI and Serial Flash */
#define CONFIG_CF_DSPI #define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH #define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x7 #define CONFIG_SYS_SBFHDR_SIZE 0x7
#ifdef CONFIG_CMD_SPI #ifdef CONFIG_CMD_SPI

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@ -142,7 +142,6 @@
/* DSPI and Serial Flash */ /* DSPI and Serial Flash */
#define CONFIG_CF_DSPI #define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE 0x13 #define CONFIG_SYS_SBFHDR_SIZE 0x13
#ifdef CONFIG_CMD_SPI #ifdef CONFIG_CMD_SPI

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@ -370,11 +370,6 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#if defined(CONFIG_SPI_FLASH) #if defined(CONFIG_SPI_FLASH)
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0

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@ -386,12 +386,6 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0

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@ -287,11 +287,6 @@
#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
#define CONFIG_SYS_I2C_IDT6V49205B 0x69 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0

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@ -182,10 +182,6 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#ifndef CONFIG_TRAILBLAZER #ifndef CONFIG_TRAILBLAZER
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0

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@ -35,7 +35,6 @@
#endif #endif
#ifdef CONFIG_CMD_SF #ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ #define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */

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@ -38,7 +38,6 @@
#endif #endif
#ifdef CONFIG_CMD_SF #ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI 1
#define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ #define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */

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@ -159,7 +159,6 @@
*/ */
#define CONFIG_TSEC1 #define CONFIG_TSEC1
#define CONFIG_TSEC2 #define CONFIG_TSEC2
#define CONFIG_HARD_SPI
/* /*
* NOR FLASH setup * NOR FLASH setup
@ -273,15 +272,6 @@
#define CONFIG_RTC_PCF8563 #define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
/*
* SPI setup
*/
#ifdef CONFIG_HARD_SPI
#define CONFIG_SYS_GPIO1_PRELIM
#define CONFIG_SYS_GPIO1_DIR 0x00000001
#define CONFIG_SYS_GPIO1_DAT 0x00000001
#endif
/* /*
* Ethernet setup * Ethernet setup
*/ */

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@ -43,7 +43,6 @@
#define CONFIG_MXC_UART #define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_HARD_SPI
#define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)

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@ -143,7 +143,6 @@
/* SPI */ /* SPI */
#ifdef CONFIG_CMD_SPI #ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_SPI_HALF_DUPLEX #define CONFIG_SPI_HALF_DUPLEX
#endif #endif

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@ -576,11 +576,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#if defined(CONFIG_SPI_FLASH) #if defined(CONFIG_SPI_FLASH)
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0

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@ -214,11 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/*
* eSPI - Enhanced SPI
*/
#define CONFIG_HARD_SPI
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
/* /*
* General PCI * General PCI

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@ -66,7 +66,6 @@
#define CONFIG_CF_DSPI #define CONFIG_CF_DSPI
#define CONFIG_SF_DEFAULT_SPEED 50000000 #define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SERIAL_FLASH #define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 1 #define CONFIG_ENV_SPI_CS 1

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@ -42,11 +42,6 @@
#define CONFIG_MXC_UART #define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_MXC_UART_BASE UART1_BASE
/*
* SPI Configs
* */
#define CONFIG_HARD_SPI /* puts SPI: ready */
/* /*
* MMC Configs * MMC Configs
* */ * */

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@ -750,7 +750,6 @@ CONFIG_G_DNL_UMS_PRODUCT_NUM
CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_UMS_VENDOR_NUM
CONFIG_H264_FREQ CONFIG_H264_FREQ
CONFIG_H8300 CONFIG_H8300
CONFIG_HARD_SPI
CONFIG_HAS_ETH0 CONFIG_HAS_ETH0
CONFIG_HAS_ETH1 CONFIG_HAS_ETH1
CONFIG_HAS_ETH2 CONFIG_HAS_ETH2