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driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun
parent
8d451a7129
commit
34e026f9b1
19 changed files with 2378 additions and 321 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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* Copyright 2008-2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -11,20 +11,23 @@
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#include <fsl_ddr.h>
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#if defined(CONFIG_SYS_FSL_DDR3)
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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static unsigned int
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compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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compute_cas_latency(const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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{
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unsigned int i;
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unsigned int taamin_ps = 0;
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unsigned int tckmin_x_ps = 0;
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unsigned int common_caslat;
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unsigned int caslat_actual;
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unsigned int retry = 16;
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unsigned int tmp;
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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#ifdef CONFIG_SYS_FSL_DDR3
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const unsigned int taamax = 20000;
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#else
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const unsigned int taamax = 18000;
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#endif
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/* compute the common CAS latency supported between slots */
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tmp = dimm_params[0].caslat_x;
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@ -34,19 +37,20 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
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}
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common_caslat = tmp;
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/* compute the max tAAmin tCKmin between slots */
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for (i = 0; i < number_of_dimms; i++) {
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taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
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tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
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}
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/* validate if the memory clk is in the range of dimms */
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if (mclk_ps < tckmin_x_ps) {
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if (mclk_ps < outpdimm->tckmin_x_ps) {
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printf("DDR clock (MCLK cycle %u ps) is faster than "
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"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
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mclk_ps, tckmin_x_ps);
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mclk_ps, outpdimm->tckmin_x_ps);
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}
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#ifdef CONFIG_SYS_FSL_DDR4
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if (mclk_ps > outpdimm->tckmax_ps) {
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printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
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mclk_ps, outpdimm->tckmax_ps);
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}
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#endif
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/* determine the acutal cas latency */
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caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
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caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
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/* check if the dimms support the CAS latency */
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while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
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caslat_actual++;
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@ -54,13 +58,147 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
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}
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/* once the caculation of caslat_actual is completed
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* we must verify that this CAS latency value does not
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* exceed tAAmax, which is 20 ns for all DDR3 speed grades
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* exceed tAAmax, which is 20 ns for all DDR3 speed grades,
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* 18ns for all DDR4 speed grades.
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*/
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if (caslat_actual * mclk_ps > 20000) {
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if (caslat_actual * mclk_ps > taamax) {
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printf("The choosen cas latency %d is too large\n",
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caslat_actual);
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}
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outpdimm->lowest_common_SPD_caslat = caslat_actual;
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outpdimm->lowest_common_spd_caslat = caslat_actual;
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debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
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return 0;
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}
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#else /* for DDR1 and DDR2 */
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static unsigned int
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compute_cas_latency(const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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{
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int i;
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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unsigned int lowest_good_caslat;
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unsigned int not_ok;
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unsigned int temp1, temp2;
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debug("using mclk_ps = %u\n", mclk_ps);
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if (mclk_ps > outpdimm->tckmax_ps) {
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printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
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mclk_ps, outpdimm->tckmax_ps);
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}
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/*
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* Compute a CAS latency suitable for all DIMMs
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*
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* Strategy for SPD-defined latencies: compute only
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* CAS latency defined by all DIMMs.
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*/
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/*
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* Step 1: find CAS latency common to all DIMMs using bitwise
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* operation.
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*/
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temp1 = 0xFF;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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temp2 = 0;
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temp2 |= 1 << dimm_params[i].caslat_x;
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temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
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temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
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/*
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* If there was no entry for X-2 (X-1) in
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* the SPD, then caslat_x_minus_2
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* (caslat_x_minus_1) contains either 255 or
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* 0xFFFFFFFF because that's what the glorious
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* __ilog2 function returns for an input of 0.
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* On 32-bit PowerPC, left shift counts with bit
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* 26 set (that the value of 255 or 0xFFFFFFFF
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* will have), cause the destination register to
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* be 0. That is why this works.
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*/
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temp1 &= temp2;
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}
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}
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/*
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* Step 2: check each common CAS latency against tCK of each
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* DIMM's SPD.
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*/
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lowest_good_caslat = 0;
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temp2 = 0;
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while (temp1) {
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not_ok = 0;
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temp2 = __ilog2(temp1);
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debug("checking common caslat = %u\n", temp2);
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/* Check if this CAS latency will work on all DIMMs at tCK. */
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for (i = 0; i < number_of_dimms; i++) {
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if (!dimm_params[i].n_ranks)
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continue;
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if (dimm_params[i].caslat_x == temp2) {
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if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
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temp2, i, mclk_ps,
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dimm_params[i].tckmin_x_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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if (dimm_params[i].caslat_x_minus_1 == temp2) {
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unsigned int tckmin_x_minus_1_ps
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= dimm_params[i].tckmin_x_minus_1_ps;
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if (mclk_ps >= tckmin_x_minus_1_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
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temp2, i, mclk_ps,
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tckmin_x_minus_1_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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if (dimm_params[i].caslat_x_minus_2 == temp2) {
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unsigned int tckmin_x_minus_2_ps
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= dimm_params[i].tckmin_x_minus_2_ps;
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if (mclk_ps >= tckmin_x_minus_2_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
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temp2, i, mclk_ps,
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tckmin_x_minus_2_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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}
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if (!not_ok)
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lowest_good_caslat = temp2;
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temp1 &= ~(1 << temp2);
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}
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debug("lowest common SPD-defined CAS latency = %u\n",
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lowest_good_caslat);
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outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
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/*
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* Compute a common 'de-rated' CAS latency.
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*
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* The strategy here is to find the *highest* dereated cas latency
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* with the assumption that all of the DIMMs will support a dereated
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* CAS latency higher than or equal to their lowest dereated value.
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*/
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++)
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temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
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outpdimm->highest_common_derated_caslat = temp1;
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debug("highest common dereated CAS latency = %u\n", temp1);
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return 0;
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}
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@ -82,34 +220,40 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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unsigned int tckmin_x_ps = 0;
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unsigned int tckmax_ps = 0xFFFFFFFF;
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unsigned int tckmax_max_ps = 0;
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unsigned int trcd_ps = 0;
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unsigned int trp_ps = 0;
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unsigned int tras_ps = 0;
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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unsigned int taamin_ps = 0;
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#endif
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#ifdef CONFIG_SYS_FSL_DDR4
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unsigned int twr_ps = 15000;
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unsigned int trfc1_ps = 0;
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unsigned int trfc2_ps = 0;
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unsigned int trfc4_ps = 0;
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unsigned int trrds_ps = 0;
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unsigned int trrdl_ps = 0;
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unsigned int tccdl_ps = 0;
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#else
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unsigned int twr_ps = 0;
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unsigned int twtr_ps = 0;
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unsigned int trfc_ps = 0;
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unsigned int trrd_ps = 0;
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unsigned int trtp_ps = 0;
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#endif
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unsigned int trc_ps = 0;
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unsigned int refresh_rate_ps = 0;
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unsigned int extended_op_srt = 1;
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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unsigned int tis_ps = 0;
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unsigned int tih_ps = 0;
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unsigned int tds_ps = 0;
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unsigned int tdh_ps = 0;
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unsigned int trtp_ps = 0;
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unsigned int tdqsq_max_ps = 0;
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unsigned int tqhs_ps = 0;
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#endif
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unsigned int temp1, temp2;
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unsigned int additive_latency = 0;
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#if !defined(CONFIG_SYS_FSL_DDR3)
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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unsigned int lowest_good_caslat;
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unsigned int not_ok;
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debug("using mclk_ps = %u\n", mclk_ps);
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#endif
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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@ -146,31 +290,34 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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* i.e., this is the slowest the whole system can go.
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*/
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tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
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/* Either find maximum value to determine slowest
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* speed, delay, time, period, etc */
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
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#endif
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tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
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tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
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trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
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trp_ps = max(trp_ps, dimm_params[i].trp_ps);
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tras_ps = max(tras_ps, dimm_params[i].tras_ps);
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#ifdef CONFIG_SYS_FSL_DDR4
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trfc1_ps = max(trfc1_ps, dimm_params[i].trfc1_ps);
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trfc2_ps = max(trfc2_ps, dimm_params[i].trfc2_ps);
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trfc4_ps = max(trfc4_ps, dimm_params[i].trfc4_ps);
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trrds_ps = max(trrds_ps, dimm_params[i].trrds_ps);
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trrdl_ps = max(trrdl_ps, dimm_params[i].trrdl_ps);
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tccdl_ps = max(tccdl_ps, dimm_params[i].tccdl_ps);
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#else
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twr_ps = max(twr_ps, dimm_params[i].twr_ps);
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twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
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trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
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trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
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trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
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#endif
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trc_ps = max(trc_ps, dimm_params[i].trc_ps);
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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tis_ps = max(tis_ps, dimm_params[i].tis_ps);
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tih_ps = max(tih_ps, dimm_params[i].tih_ps);
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tds_ps = max(tds_ps, dimm_params[i].tds_ps);
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tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
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trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
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tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
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refresh_rate_ps = max(refresh_rate_ps,
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dimm_params[i].refresh_rate_ps);
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/* extended_op_srt is either 0 or 1, 0 having priority */
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extended_op_srt = min(extended_op_srt,
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dimm_params[i].extended_op_srt);
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/*
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* Find maximum tdqsq_max_ps to find slowest.
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*
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@ -178,6 +325,12 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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* strategy for this parameter?
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*/
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tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
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#endif
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refresh_rate_ps = max(refresh_rate_ps,
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dimm_params[i].refresh_rate_ps);
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/* extended_op_srt is either 0 or 1, 0 having priority */
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extended_op_srt = min(extended_op_srt,
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dimm_params[i].extended_op_srt);
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}
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outpdimm->ndimms_present = number_of_dimms - temp1;
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@ -189,24 +342,37 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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outpdimm->tckmin_x_ps = tckmin_x_ps;
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outpdimm->tckmax_ps = tckmax_ps;
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outpdimm->tckmax_max_ps = tckmax_max_ps;
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#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
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outpdimm->taamin_ps = taamin_ps;
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#endif
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outpdimm->trcd_ps = trcd_ps;
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outpdimm->trp_ps = trp_ps;
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outpdimm->tras_ps = tras_ps;
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outpdimm->twr_ps = twr_ps;
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#ifdef CONFIG_SYS_FSL_DDR4
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outpdimm->trfc1_ps = trfc1_ps;
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outpdimm->trfc2_ps = trfc2_ps;
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outpdimm->trfc4_ps = trfc4_ps;
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outpdimm->trrds_ps = trrds_ps;
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outpdimm->trrdl_ps = trrdl_ps;
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outpdimm->tccdl_ps = tccdl_ps;
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#else
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outpdimm->twtr_ps = twtr_ps;
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outpdimm->trfc_ps = trfc_ps;
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outpdimm->trrd_ps = trrd_ps;
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outpdimm->trtp_ps = trtp_ps;
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#endif
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outpdimm->twr_ps = twr_ps;
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outpdimm->trc_ps = trc_ps;
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outpdimm->refresh_rate_ps = refresh_rate_ps;
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outpdimm->extended_op_srt = extended_op_srt;
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#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
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outpdimm->tis_ps = tis_ps;
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outpdimm->tih_ps = tih_ps;
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outpdimm->tds_ps = tds_ps;
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outpdimm->tdh_ps = tdh_ps;
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outpdimm->trtp_ps = trtp_ps;
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outpdimm->tdqsq_max_ps = tdqsq_max_ps;
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outpdimm->tqhs_ps = tqhs_ps;
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#endif
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/* Determine common burst length for all DIMMs. */
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temp1 = 0xff;
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@ -265,128 +431,9 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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if (temp1 != 0)
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printf("ERROR: Mix different RDIMM detected!\n");
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#if defined(CONFIG_SYS_FSL_DDR3)
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if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
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/* calculate cas latency for all DDR types */
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if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
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return 1;
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#else
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/*
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* Compute a CAS latency suitable for all DIMMs
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*
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* Strategy for SPD-defined latencies: compute only
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* CAS latency defined by all DIMMs.
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*/
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/*
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* Step 1: find CAS latency common to all DIMMs using bitwise
|
||||
* operation.
|
||||
*/
|
||||
temp1 = 0xFF;
|
||||
for (i = 0; i < number_of_dimms; i++) {
|
||||
if (dimm_params[i].n_ranks) {
|
||||
temp2 = 0;
|
||||
temp2 |= 1 << dimm_params[i].caslat_x;
|
||||
temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
|
||||
temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
|
||||
/*
|
||||
* FIXME: If there was no entry for X-2 (X-1) in
|
||||
* the SPD, then caslat_x_minus_2
|
||||
* (caslat_x_minus_1) contains either 255 or
|
||||
* 0xFFFFFFFF because that's what the glorious
|
||||
* __ilog2 function returns for an input of 0.
|
||||
* On 32-bit PowerPC, left shift counts with bit
|
||||
* 26 set (that the value of 255 or 0xFFFFFFFF
|
||||
* will have), cause the destination register to
|
||||
* be 0. That is why this works.
|
||||
*/
|
||||
temp1 &= temp2;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Step 2: check each common CAS latency against tCK of each
|
||||
* DIMM's SPD.
|
||||
*/
|
||||
lowest_good_caslat = 0;
|
||||
temp2 = 0;
|
||||
while (temp1) {
|
||||
not_ok = 0;
|
||||
temp2 = __ilog2(temp1);
|
||||
debug("checking common caslat = %u\n", temp2);
|
||||
|
||||
/* Check if this CAS latency will work on all DIMMs at tCK. */
|
||||
for (i = 0; i < number_of_dimms; i++) {
|
||||
if (!dimm_params[i].n_ranks) {
|
||||
continue;
|
||||
}
|
||||
if (dimm_params[i].caslat_x == temp2) {
|
||||
if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
|
||||
debug("CL = %u ok on DIMM %u at tCK=%u"
|
||||
" ps with its tCKmin_X_ps of %u\n",
|
||||
temp2, i, mclk_ps,
|
||||
dimm_params[i].tckmin_x_ps);
|
||||
continue;
|
||||
} else {
|
||||
not_ok++;
|
||||
}
|
||||
}
|
||||
|
||||
if (dimm_params[i].caslat_x_minus_1 == temp2) {
|
||||
unsigned int tckmin_x_minus_1_ps
|
||||
= dimm_params[i].tckmin_x_minus_1_ps;
|
||||
if (mclk_ps >= tckmin_x_minus_1_ps) {
|
||||
debug("CL = %u ok on DIMM %u at "
|
||||
"tCK=%u ps with its "
|
||||
"tckmin_x_minus_1_ps of %u\n",
|
||||
temp2, i, mclk_ps,
|
||||
tckmin_x_minus_1_ps);
|
||||
continue;
|
||||
} else {
|
||||
not_ok++;
|
||||
}
|
||||
}
|
||||
|
||||
if (dimm_params[i].caslat_x_minus_2 == temp2) {
|
||||
unsigned int tckmin_x_minus_2_ps
|
||||
= dimm_params[i].tckmin_x_minus_2_ps;
|
||||
if (mclk_ps >= tckmin_x_minus_2_ps) {
|
||||
debug("CL = %u ok on DIMM %u at "
|
||||
"tCK=%u ps with its "
|
||||
"tckmin_x_minus_2_ps of %u\n",
|
||||
temp2, i, mclk_ps,
|
||||
tckmin_x_minus_2_ps);
|
||||
continue;
|
||||
} else {
|
||||
not_ok++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!not_ok) {
|
||||
lowest_good_caslat = temp2;
|
||||
}
|
||||
|
||||
temp1 &= ~(1 << temp2);
|
||||
}
|
||||
|
||||
debug("lowest common SPD-defined CAS latency = %u\n",
|
||||
lowest_good_caslat);
|
||||
outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
|
||||
|
||||
|
||||
/*
|
||||
* Compute a common 'de-rated' CAS latency.
|
||||
*
|
||||
* The strategy here is to find the *highest* dereated cas latency
|
||||
* with the assumption that all of the DIMMs will support a dereated
|
||||
* CAS latency higher than or equal to their lowest dereated value.
|
||||
*/
|
||||
temp1 = 0;
|
||||
for (i = 0; i < number_of_dimms; i++) {
|
||||
temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
|
||||
}
|
||||
outpdimm->highest_common_derated_caslat = temp1;
|
||||
debug("highest common dereated CAS latency = %u\n", temp1);
|
||||
#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */
|
||||
|
||||
/* Determine if all DIMMs ECC capable. */
|
||||
temp1 = 1;
|
||||
|
|
@ -404,14 +451,6 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
|
|||
}
|
||||
outpdimm->all_dimms_ecc_capable = temp1;
|
||||
|
||||
#ifndef CONFIG_SYS_FSL_DDR3
|
||||
/* FIXME: move to somewhere else to validate. */
|
||||
if (mclk_ps > tckmax_max_ps) {
|
||||
printf("Warning: some of the installed DIMMs "
|
||||
"can not operate this slowly.\n");
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Compute additive latency.
|
||||
*
|
||||
|
|
@ -468,27 +507,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
|
|||
additive_latency = 0;
|
||||
|
||||
#if defined(CONFIG_SYS_FSL_DDR2)
|
||||
if (lowest_good_caslat < 4) {
|
||||
additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
|
||||
? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
|
||||
if ((outpdimm->lowest_common_spd_caslat < 4) &&
|
||||
(picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
|
||||
additive_latency = picos_to_mclk(trcd_ps) -
|
||||
outpdimm->lowest_common_spd_caslat;
|
||||
if (mclk_to_picos(additive_latency) > trcd_ps) {
|
||||
additive_latency = picos_to_mclk(trcd_ps);
|
||||
debug("setting additive_latency to %u because it was "
|
||||
" greater than tRCD_ps\n", additive_latency);
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_SYS_FSL_DDR3)
|
||||
/*
|
||||
* The system will not use the global auto-precharge mode.
|
||||
* However, it uses the page mode, so we set AL=0
|
||||
*/
|
||||
additive_latency = 0;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Validate additive latency
|
||||
* FIXME: move to somewhere else to validate
|
||||
*
|
||||
* AL <= tRCD(min)
|
||||
*/
|
||||
|
|
@ -516,10 +548,19 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
|
|||
debug("trcd_ps = %u\n", outpdimm->trcd_ps);
|
||||
debug("trp_ps = %u\n", outpdimm->trp_ps);
|
||||
debug("tras_ps = %u\n", outpdimm->tras_ps);
|
||||
debug("twr_ps = %u\n", outpdimm->twr_ps);
|
||||
#ifdef CONFIG_SYS_FSL_DDR4
|
||||
debug("trfc1_ps = %u\n", trfc1_ps);
|
||||
debug("trfc2_ps = %u\n", trfc2_ps);
|
||||
debug("trfc4_ps = %u\n", trfc4_ps);
|
||||
debug("trrds_ps = %u\n", trrds_ps);
|
||||
debug("trrdl_ps = %u\n", trrdl_ps);
|
||||
debug("tccdl_ps = %u\n", tccdl_ps);
|
||||
#else
|
||||
debug("twtr_ps = %u\n", outpdimm->twtr_ps);
|
||||
debug("trfc_ps = %u\n", outpdimm->trfc_ps);
|
||||
debug("trrd_ps = %u\n", outpdimm->trrd_ps);
|
||||
#endif
|
||||
debug("twr_ps = %u\n", outpdimm->twr_ps);
|
||||
debug("trc_ps = %u\n", outpdimm->trc_ps);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue