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xtensa: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-07-13 15:19:36 +02:00 • committed by Tom Rini
parent 62b668ba13
commit 3451b69e33
12 changed files with 0 additions and 74 deletions
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13
arch/xtensa/include/asm/arch-dc232b/core.h
View file

@ -9,7 +9,6 @@
#ifndef _XTENSA_CORE_CONFIGURATION_H #ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H
/**************************************************************************** /****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/ ****************************************************************************/
@ -19,7 +18,6 @@
* configured, and a value of 0 otherwise. These macros are always defined. * configured, and a value of 0 otherwise. These macros are always defined.
*/ */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
ISA ISA
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -69,7 +67,6 @@
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
MISC MISC
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -111,7 +108,6 @@
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */ #define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
CACHE CACHE
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -126,12 +122,10 @@
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
/**************************************************************************** /****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/ ****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
@ -159,7 +153,6 @@
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4 #define XCHAL_CA_BITS 4
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -171,7 +164,6 @@
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
INTERRUPTS and TIMERS INTERRUPTS and TIMERS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -282,7 +274,6 @@
#define XCHAL_INTLEVEL7_NUM 14 #define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */ /* (There are many interrupts each at level(s) 1, 3.) */
/* /*
* External interrupt vectors/levels. * External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers * These macros describe how Xtensa processor interrupt numbers
@ -311,7 +302,6 @@
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
EXCEPTIONS and VECTORS EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -379,7 +369,6 @@
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
DEBUG DEBUG
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -389,7 +378,6 @@
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
MMU MMU
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -415,5 +403,4 @@
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */ #endif /* _XTENSA_CORE_CONFIGURATION_H */

1
arch/xtensa/include/asm/arch-dc232b/tie-asm.h
View file

@ -25,7 +25,6 @@
/* Misc */ /* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
/* Macro to save all non-coprocessor (extra) custom TIE and optional state /* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers). * (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (1 byte aligned) * Save area ptr (clobbered): ptr (1 byte aligned)

12
arch/xtensa/include/asm/arch-dc233c/core.h
View file

@ -9,7 +9,6 @@
#ifndef _XTENSA_CORE_CONFIGURATION_H #ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H
/**************************************************************************** /****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/ ****************************************************************************/
@ -19,7 +18,6 @@
* configured, and a value of 0 otherwise. These macros are always defined. * configured, and a value of 0 otherwise. These macros are always defined.
*/ */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
ISA ISA
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -86,7 +84,6 @@
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
MISC MISC
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -130,7 +127,6 @@
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ #define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
CACHE CACHE
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -148,7 +144,6 @@
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
/**************************************************************************** /****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/ ****************************************************************************/
@ -184,7 +179,6 @@
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4 #define XCHAL_CA_BITS 4
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -198,7 +192,6 @@
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
INTERRUPTS and TIMERS INTERRUPTS and TIMERS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -309,7 +302,6 @@
#define XCHAL_INTLEVEL7_NUM 14 #define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */ /* (There are many interrupts each at level(s) 1, 3.) */
/* /*
* External interrupt vectors/levels. * External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers * These macros describe how Xtensa processor interrupt numbers
@ -338,7 +330,6 @@
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
EXCEPTIONS and VECTORS EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -408,7 +399,6 @@
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
DEBUG DEBUG
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -418,7 +408,6 @@
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
MMU MMU
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -445,5 +434,4 @@
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */ #endif /* _XTENSA_CORE_CONFIGURATION_H */

1
arch/xtensa/include/asm/arch-dc233c/tie-asm.h
View file

@ -159,7 +159,6 @@
.endif .endif
.endm // xchal_ncp_load .endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1 #define XCHAL_NCP_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1

13
arch/xtensa/include/asm/arch-de212/core.h
View file

@ -9,7 +9,6 @@
#ifndef _XTENSA_CORE_CONFIGURATION_H #ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H
/**************************************************************************** /****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/ ****************************************************************************/
@ -19,7 +18,6 @@
* configured, and a value of 0 otherwise. These macros are always defined. * configured, and a value of 0 otherwise. These macros are always defined.
*/ */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
ISA ISA
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -91,7 +89,6 @@
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0 #define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
@ -130,7 +127,6 @@
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
MISC MISC
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -178,7 +174,6 @@
#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
CACHE CACHE
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -205,7 +200,6 @@
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
/**************************************************************************** /****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/ ****************************************************************************/
@ -250,7 +244,6 @@
XCHAL_HAVE_DCACHE_DYN_WAYS) && \ XCHAL_HAVE_DCACHE_DYN_WAYS) && \
(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -283,7 +276,6 @@
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
INTERRUPTS and TIMERS INTERRUPTS and TIMERS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -395,7 +387,6 @@
#define XCHAL_INTLEVEL7_NUM 14 #define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */ /* (There are many interrupts each at level(s) 1, 3.) */
/* /*
* External interrupt mapping. * External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers * These macros describe how Xtensa processor interrupt numbers
@ -442,7 +433,6 @@
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ #define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
EXCEPTIONS and VECTORS EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -512,7 +502,6 @@
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
DEBUG MODULE DEBUG MODULE
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -539,7 +528,6 @@
/* Perf counters */ /* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ #define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
/*---------------------------------------------------------------------- /*----------------------------------------------------------------------
MMU MMU
----------------------------------------------------------------------*/ ----------------------------------------------------------------------*/
@ -564,5 +552,4 @@
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */ #endif /* _XTENSA_CORE_CONFIGURATION_H */

2
arch/xtensa/include/asm/arch-de212/tie-asm.h
View file

@ -31,7 +31,6 @@
| ((ccuse) & XTHAL_SAS_ANYCC) \ | ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) ) | ((abi) & XTHAL_SAS_ANYABI) )
/* /*
* Macro to store all non-coprocessor (extra) custom TIE and optional state * Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers). * (not including zero-overhead loop registers).
@ -140,7 +139,6 @@
.endif .endif
.endm // xchal_ncp_load .endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1 #define XCHAL_NCP_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1

11
arch/xtensa/include/asm/asmmacro.h
View file

@ -59,7 +59,6 @@
loop \at, 99f loop \at, 99f
.endm .endm
.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
.ifgt \incr_log2 - 1 .ifgt \incr_log2 - 1
addi \at, \as, (1 << \incr_log2) - 1 addi \at, \as, (1 << \incr_log2) - 1
@ -72,7 +71,6 @@
loop\cond \at, 99f loop\cond \at, 99f
.endm .endm
.macro __loopt ar, as, at, incr_log2 .macro __loopt ar, as, at, incr_log2
sub \at, \as, \ar sub \at, \as, \ar
.ifgt \incr_log2 - 1 .ifgt \incr_log2 - 1
@ -82,17 +80,14 @@
loop \at, 99f loop \at, 99f
.endm .endm
.macro __loop as .macro __loop as
loop \as, 99f loop \as, 99f
.endm .endm
.macro __endl ar, as .macro __endl ar, as
99: 99:
.endm .endm
#else #else
.macro __loopi ar, at, size, incr .macro __loopi ar, at, size, incr
@ -101,7 +96,6 @@
98: 98:
.endm .endm
.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
.ifnc \mask_log2, .ifnc \mask_log2,
extui \at, \as, \incr_log2, \mask_log2 extui \at, \as, \incr_log2, \mask_log2
@ -127,25 +121,20 @@
98: 98:
.endm .endm
.macro __loop as .macro __loop as
98: 98:
.endm .endm
.macro __endl ar, as .macro __endl ar, as
bltu \ar, \as, 98b bltu \ar, \as, 98b
99: 99:
.endm .endm
#endif #endif
.macro __endla ar, as, incr .macro __endla ar, as, incr
addi \ar, \ar, \incr addi \ar, \ar, \incr
__endl \ar \as __endl \ar \as
.endm .endm
#endif /* _XTENSA_ASMMACRO_H */ #endif /* _XTENSA_ASMMACRO_H */

16
arch/xtensa/include/asm/cacheasm.h
View file

@ -51,7 +51,6 @@
.endm .endm
.macro __loop_cache_range ar as at insn line_width .macro __loop_cache_range ar as at insn line_width
extui \at, \ar, 0, \line_width extui \at, \ar, 0, \line_width
@ -63,7 +62,6 @@
.endm .endm
.macro __loop_cache_page ar at insn line_width .macro __loop_cache_page ar at insn line_width
__loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
@ -77,7 +75,6 @@
.endm .endm
.macro ___unlock_dcache_all ar at .macro ___unlock_dcache_all ar at
#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
@ -86,7 +83,6 @@
.endm .endm
.macro ___unlock_icache_all ar at .macro ___unlock_icache_all ar at
#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
@ -95,7 +91,6 @@
.endm .endm
.macro ___flush_invalidate_dcache_all ar at .macro ___flush_invalidate_dcache_all ar at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -104,7 +99,6 @@
.endm .endm
.macro ___flush_dcache_all ar at .macro ___flush_dcache_all ar at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -113,7 +107,6 @@
.endm .endm
.macro ___invalidate_dcache_all ar at .macro ___invalidate_dcache_all ar at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -123,7 +116,6 @@
.endm .endm
.macro ___invalidate_icache_all ar at .macro ___invalidate_icache_all ar at
#if XCHAL_ICACHE_SIZE #if XCHAL_ICACHE_SIZE
@ -133,7 +125,6 @@
.endm .endm
.macro ___flush_invalidate_dcache_range ar as at .macro ___flush_invalidate_dcache_range ar as at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -142,7 +133,6 @@
.endm .endm
.macro ___flush_dcache_range ar as at .macro ___flush_dcache_range ar as at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -151,7 +141,6 @@
.endm .endm
.macro ___invalidate_dcache_range ar as at .macro ___invalidate_dcache_range ar as at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -160,7 +149,6 @@
.endm .endm
.macro ___invalidate_icache_range ar as at .macro ___invalidate_icache_range ar as at
#if XCHAL_ICACHE_SIZE #if XCHAL_ICACHE_SIZE
@ -169,7 +157,6 @@
.endm .endm
.macro ___flush_invalidate_dcache_page ar as .macro ___flush_invalidate_dcache_page ar as
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -178,7 +165,6 @@
.endm .endm
.macro ___flush_dcache_page ar as .macro ___flush_dcache_page ar as
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -187,7 +173,6 @@
.endm .endm
.macro ___invalidate_dcache_page ar as .macro ___invalidate_dcache_page ar as
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
@ -196,7 +181,6 @@
.endm .endm
.macro ___invalidate_icache_page ar as .macro ___invalidate_icache_page ar as
#if XCHAL_ICACHE_SIZE #if XCHAL_ICACHE_SIZE

1
arch/xtensa/include/asm/io.h
View file

@ -111,7 +111,6 @@ void outsl(unsigned long port, const void *src, unsigned long count);
# error processor byte order undefined! # error processor byte order undefined!
#endif #endif
/* /*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem access * Convert a physical pointer to a virtual kernel pointer for /dev/mem access
*/ */

1
arch/xtensa/include/asm/processor.h
View file

@ -6,5 +6,4 @@
#ifndef _XTENSA_PROCESSOR_H #ifndef _XTENSA_PROCESSOR_H
#define _XTENSA_PROCESSOR_H #define _XTENSA_PROCESSOR_H
#endif /* _XTENSA_PROCESSOR_H */ #endif /* _XTENSA_PROCESSOR_H */

1
arch/xtensa/include/asm/types.h
View file

@ -24,7 +24,6 @@ typedef u32 dma_addr_t;
typedef unsigned long phys_addr_t; typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t; typedef unsigned long phys_size_t;
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
#endif /* _XTENSA_TYPES_H */ #endif /* _XTENSA_TYPES_H */

2
arch/xtensa/lib/time.c
View file

@ -62,7 +62,6 @@ void __udelay(unsigned long usec)
delay_cycles(mhz * lo); delay_cycles(mhz * lo);
} }
/* /*
* Return the elapsed time (ticks) since 'base'. * Return the elapsed time (ticks) since 'base'.
*/ */
@ -89,7 +88,6 @@ ulong get_timer(ulong base)
#endif #endif
} }
/* /*
* This function is derived from ARM/PowerPC code (read timebase as long long). * This function is derived from ARM/PowerPC code (read timebase as long long).
* On Xtensa it just returns the timer value. * On Xtensa it just returns the timer value.