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common: Drop checkicache() and checkdcache()

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These are used by only one arch and only within a single file. Drop the
declarations from the common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Simon Glass 2019-11-14 12:57:38 -07:00 • committed by Tom Rini
parent 9edefc2776
commit 3374d28b34
2 changed files with 76 additions and 78 deletions
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152
arch/powerpc/cpu/mpc8xx/cpu.c
View file

@ -35,6 +35,82 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/* L1 i-cache */
int checkicache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
wr_ic_cst(IDC_UNALL);
wr_ic_cst(IDC_INVALL);
wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
while (!((m = rd_ic_cst()) & IDC_CERR2)) {
wr_ic_adr(k);
wr_ic_cst(IDC_LDLCK);
__asm__ volatile ("isync");
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
wr_ic_cst(IDC_UNALL);
wr_ic_cst(IDC_INVALL);
if (cacheon)
wr_ic_cst(IDC_ENABLE);
else
wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
return lines << 4;
};
/* ------------------------------------------------------------------------- */
/* L1 d-cache */
/* call with cache disabled */
static int checkdcache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
wr_dc_cst(IDC_UNALL);
wr_dc_cst(IDC_INVALL);
wr_dc_cst(IDC_DISABLE);
while (!((m = rd_dc_cst()) & IDC_CERR2)) {
wr_dc_adr(k);
wr_dc_cst(IDC_LDLCK);
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
wr_dc_cst(IDC_UNALL);
wr_dc_cst(IDC_INVALL);
if (cacheon)
wr_dc_cst(IDC_ENABLE);
else
wr_dc_cst(IDC_DISABLE);
return lines << 4;
};
static int check_CPU(long clock, uint pvr, uint immr) static int check_CPU(long clock, uint pvr, uint immr)
{ {
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
@ -99,82 +175,6 @@ int checkcpu(void)
return check_CPU(clock, pvr, immr); return check_CPU(clock, pvr, immr);
} }
/* ------------------------------------------------------------------------- */
/* L1 i-cache */
int checkicache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
wr_ic_cst(IDC_UNALL);
wr_ic_cst(IDC_INVALL);
wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
while (!((m = rd_ic_cst()) & IDC_CERR2)) {
wr_ic_adr(k);
wr_ic_cst(IDC_LDLCK);
__asm__ volatile ("isync");
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
wr_ic_cst(IDC_UNALL);
wr_ic_cst(IDC_INVALL);
if (cacheon)
wr_ic_cst(IDC_ENABLE);
else
wr_ic_cst(IDC_DISABLE);
__asm__ volatile ("isync");
return lines << 4;
};
/* ------------------------------------------------------------------------- */
/* L1 d-cache */
/* call with cache disabled */
int checkdcache(void)
{
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
memctl8xx_t __iomem *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst() & IDC_ENABLED;
/* probe in flash memoryarea */
u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
u32 m;
u32 lines = -1;
wr_dc_cst(IDC_UNALL);
wr_dc_cst(IDC_INVALL);
wr_dc_cst(IDC_DISABLE);
while (!((m = rd_dc_cst()) & IDC_CERR2)) {
wr_dc_adr(k);
wr_dc_cst(IDC_LDLCK);
lines++;
k += 0x10; /* the number of bytes in a cacheline */
}
wr_dc_cst(IDC_UNALL);
wr_dc_cst(IDC_INVALL);
if (cacheon)
wr_dc_cst(IDC_ENABLE);
else
wr_dc_cst(IDC_DISABLE);
return lines << 4;
};
/* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */
void upmconfig(uint upm, uint *table, uint size) void upmconfig(uint upm, uint *table, uint size)

2
include/common.h
View file

@ -195,8 +195,6 @@ void trap_init (ulong);
void s_init(void); void s_init(void);
int checkicache (void);
int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int); void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void); ulong get_tbclk (void);
void reset_misc (void); void reset_misc (void);