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video: tegra20: dc: use nvidia,head property to identify DC controller
Use existing nvidia,head device tree property to get DC controller id. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
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2 changed files with 3 additions and 7 deletions
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@ -49,7 +49,7 @@ struct tegra_lcd_priv {
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int dc_clk[2]; /* Contains clk and its parent */
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ulong scdiv; /* Clock divider used by disp_clk_ctrl */
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bool rotation; /* 180 degree panel turn */
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bool pipe; /* DC controller: 0 for A, 1 for B */
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int pipe; /* DC controller: 0 for A, 1 for B */
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};
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enum {
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@ -461,9 +461,7 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
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}
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priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
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if (!strcmp(dev->name, TEGRA_DC_B))
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priv->pipe = 1;
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priv->pipe = dev_read_u32_default(dev, "nvidia,head", 0);
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rgb = fdt_subnode_offset(blob, node, "rgb");
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if (rgb < 0) {
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@ -14,15 +14,13 @@
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/* arch-tegra/dc exists only because T124 uses it */
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#include <asm/arch-tegra/dc.h>
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#define TEGRA_DC_A "dc@54200000"
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#define TEGRA_DC_B "dc@54240000"
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#define TEGRA_DSI_A "dsi@54300000"
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#define TEGRA_DSI_B "dsi@54400000"
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struct tegra_dc_plat {
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struct udevice *dev; /* Display controller device */
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struct dc_ctlr *dc; /* Display controller regmap */
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bool pipe; /* DC number: 0 for A, 1 for B */
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int pipe; /* DC number: 0 for A, 1 for B */
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ulong scdiv; /* Shift clock divider */
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};
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