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https://github.com/u-boot/u-boot.git
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Merge branch '2022-03-02-armv8-fixes-and-cleanups' into next
To quote the author: I was looking into the arm64 boot code lately and stumbled upon some issues. Also Nishanth brought back memories of a lengthy debug session, which was caused due to U-Boot keeping SErrors masked. As the resulting patches are all somewhat related, I gathered this series here to address those problems. Patches 1 to 3 address exception handling issues, with the SError enablement being the most prominent fix here. Patch 4 cleans up asm/io.h. This was on the list before[1], but was somehow lost when it was intercepted by a shorter version of itself. Patches 5 and 6 clean up some unnecessarily complicated AArch64 assembly code.
This commit is contained in:
Tom Rini
commit
2dfdba4a5a
9 changed files with 85 additions and 142 deletions
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@ -74,15 +74,6 @@ ENDPROC(smp_kick_all_cpus)
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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/* unmask SError and abort */
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msr daifclr, #4
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/* Set HCR_EL2[AMO] so SError @EL2 is taken */
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mrs x0, hcr_el2
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orr x0, x0, #0x20 /* AMO */
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msr hcr_el2, x0
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isb
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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@ -209,7 +200,7 @@ ENTRY(lowlevel_init)
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#endif
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100:
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branch_if_master x0, x1, 2f
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branch_if_master x0, 2f
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#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
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/*
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@ -126,6 +126,8 @@ pie_fixup_done:
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b 0f
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2: mrs x1, hcr_el2
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tbnz x1, #34, 1f /* HCR_EL2.E2H */
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orr x1, x1, #HCR_EL2_AMO_EL2 /* Route SErrors to EL2 */
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msr hcr_el2, x1
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set_vbar vbar_el2, x0
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Enable FP/SIMD */
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@ -134,6 +136,7 @@ pie_fixup_done:
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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msr daifclr, #0x4 /* Unmask SError interrupts */
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#ifdef COUNTER_FREQUENCY
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branch_if_not_highest_el x0, 4f
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@ -172,11 +175,11 @@ pie_fixup_done:
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bl lowlevel_init
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#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
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branch_if_master x0, x1, master_cpu
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branch_if_master x0, master_cpu
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b spin_table_secondary_jump
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/* never return */
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#elif defined(CONFIG_ARMV8_MULTIENTRY)
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branch_if_master x0, x1, master_cpu
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branch_if_master x0, master_cpu
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/*
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* Slave CPUs
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@ -189,6 +192,7 @@ slave_cpu:
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br x0 /* branch to the given address */
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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master_cpu:
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msr SPSel, #1 /* make sure we use SP_ELx */
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bl _main
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/*-----------------------------------------------------------------------*/
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@ -301,7 +305,7 @@ WEAK(lowlevel_init)
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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branch_if_master x0, 2f
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/*
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* Slave should wait for master clearing spin table.
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@ -1,45 +1,26 @@
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/*
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* linux/include/asm-arm/io.h
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* I/O device access primitives. Based on early versions from the Linux kernel.
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
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* constant addresses and variable addresses.
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* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
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* specific IO header files.
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* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
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* 04-Apr-1999 PJB Added check_signature.
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* 12-Dec-1999 RMK More cleanups
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* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
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*/
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#ifndef __ASM_ARM_IO_H
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#define __ASM_ARM_IO_H
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#ifdef __KERNEL__
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <asm/byteorder.h>
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#include <asm/memory.h>
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#include <asm/barriers.h>
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#if 0 /* XXX###XXX */
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#include <asm/arch/hardware.h>
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#endif /* XXX###XXX */
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static inline void sync(void)
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{
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}
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/*
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* Generic virtual read/write. Note that we don't support half-word
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* read/writes. We define __arch_*[bl] here, and leave __arch_*w
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* to the architecture specific code.
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*/
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/* Generic virtual read/write. */
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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@ -247,13 +228,6 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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#define setbits_64(addr, set) setbits(64, addr, set)
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#define clrsetbits_64(addr, clear, set) clrsetbits(64, addr, clear, set)
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/*
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* Now, pick up the machine-defined IO definitions
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*/
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#if 0 /* XXX###XXX */
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#include <asm/arch/io.h>
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#endif /* XXX###XXX */
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/*
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* IO port access primitives
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* -------------------------
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@ -317,16 +291,6 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
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#define writesb(a, d, s) __raw_writesb((unsigned long)a, d, s)
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#define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s)
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/*
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* DMA-consistent mapping functions. These allocate/free a region of
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* uncached, unwrite-buffered mapped memory space for use with DMA
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* devices. This is the "generic" version. The PCI specific version
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* is in pci.h
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*/
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extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
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extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
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extern void consistent_sync(void *vaddr, size_t size, int rw);
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/*
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* String version of IO memory access ops:
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*/
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@ -334,8 +298,6 @@ extern void _memcpy_fromio(void *, unsigned long, size_t);
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extern void _memcpy_toio(unsigned long, const void *, size_t);
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extern void _memset_io(unsigned long, int, size_t);
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extern void __readwrite_bug(const char *fn);
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/* Optimized copy functions to read from/write to IO sapce */
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#ifdef CONFIG_ARM64
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#include <cpu_func.h>
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@ -441,62 +403,6 @@ void __memset_io(volatile void __iomem *dst, int c, size_t count)
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#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
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#endif
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/*
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* If this architecture has ISA IO, then define the isa_read/isa_write
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* macros.
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*/
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#ifdef __mem_isa
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#define isa_readb(addr) __raw_readb(__mem_isa(addr))
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#define isa_readw(addr) __raw_readw(__mem_isa(addr))
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#define isa_readl(addr) __raw_readl(__mem_isa(addr))
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#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr))
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#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr))
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#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr))
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#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c))
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#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c))
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#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c))
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#define isa_eth_io_copy_and_sum(a,b,c,d) \
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eth_copy_and_sum((a),__mem_isa(b),(c),(d))
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static inline int
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isa_check_signature(unsigned long io_addr, const unsigned char *signature,
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int length)
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{
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int retval = 0;
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do {
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if (isa_readb(io_addr) != *signature)
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goto out;
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io_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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#else /* __mem_isa */
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#define isa_readb(addr) (__readwrite_bug("isa_readb"),0)
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#define isa_readw(addr) (__readwrite_bug("isa_readw"),0)
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#define isa_readl(addr) (__readwrite_bug("isa_readl"),0)
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#define isa_writeb(val,addr) __readwrite_bug("isa_writeb")
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#define isa_writew(val,addr) __readwrite_bug("isa_writew")
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#define isa_writel(val,addr) __readwrite_bug("isa_writel")
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#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io")
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#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio")
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#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio")
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#define isa_eth_io_copy_and_sum(a,b,c,d) \
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__readwrite_bug("isa_eth_io_copy_and_sum")
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#define isa_check_signature(io,sig,len) (0)
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#endif /* __mem_isa */
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#endif /* __KERNEL__ */
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#include <asm-generic/io.h>
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#include <iotrace.h>
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@ -69,12 +69,10 @@ lr .req x30
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*/
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.macro switch_el, xreg, el3_label, el2_label, el1_label
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mrs \xreg, CurrentEL
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cmp \xreg, 0xc
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b.eq \el3_label
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cmp \xreg, 0x8
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cmp \xreg, #0x8
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b.gt \el3_label
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b.eq \el2_label
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cmp \xreg, 0x4
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b.eq \el1_label
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b.lt \el1_label
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.endm
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/*
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@ -123,19 +121,10 @@ lr .req x30
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*/
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.macro branch_if_slave, xreg, slave_label
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#ifdef CONFIG_ARMV8_MULTIENTRY
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/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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mrs \xreg, mpidr_el1
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tst \xreg, #0xff /* Test Affinity 0 */
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b.ne \slave_label
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lsr \xreg, \xreg, #8
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tst \xreg, #0xff /* Test Affinity 1 */
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b.ne \slave_label
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lsr \xreg, \xreg, #8
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tst \xreg, #0xff /* Test Affinity 2 */
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b.ne \slave_label
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lsr \xreg, \xreg, #16
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tst \xreg, #0xff /* Test Affinity 3 */
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b.ne \slave_label
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and \xreg, \xreg, 0xffffffffff /* clear bits [63:40] */
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and \xreg, \xreg, ~0x00ff000000 /* also clear bits [31:24] */
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cbnz \xreg, \slave_label
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#endif
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.endm
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@ -143,16 +132,12 @@ lr .req x30
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* Branch if current processor is a master,
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* choose processor with all zero affinity value as the master.
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*/
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.macro branch_if_master, xreg1, xreg2, master_label
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.macro branch_if_master, xreg, master_label
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#ifdef CONFIG_ARMV8_MULTIENTRY
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/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
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mrs \xreg1, mpidr_el1
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lsr \xreg2, \xreg1, #32
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lsl \xreg2, \xreg2, #32
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lsl \xreg1, \xreg1, #40
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lsr \xreg1, \xreg1, #40
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orr \xreg1, \xreg1, \xreg2
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cbz \xreg1, \master_label
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mrs \xreg, mpidr_el1
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and \xreg, \xreg, 0xffffffffff /* clear bits [63:40] */
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and \xreg, \xreg, ~0x00ff000000 /* also clear bits [31:24] */
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cbz \xreg, \master_label
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#else
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b \master_label
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#endif
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@ -82,6 +82,7 @@
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#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
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#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
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#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
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#define HCR_EL2_AMO_EL2 (1 << 5) /* Route SErrors to EL2 */
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/*
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* ID_AA64ISAR1_EL1 bits definitions
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|
|
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@ -64,7 +64,7 @@ ENTRY(lowlevel_init)
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#endif
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#endif
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branch_if_master x0, x1, 2f
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branch_if_master x0, 2f
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/*
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* Slave should wait for master clearing spin table.
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|
|
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|
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@ -38,7 +38,7 @@ slave_wait_atf:
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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branch_if_master x0, 2f
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/*
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* Slave should wait for master clearing spin table.
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|
|
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@ -50,7 +50,7 @@ skip_smp_setup:
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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branch_if_master x0, 2f
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/*
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* Slave should wait for master clearing spin table.
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|
|
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|
|
@ -7,19 +7,73 @@
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#include <common.h>
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#include <command.h>
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#include <linux/bitops.h>
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static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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/*
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* 0xe7f...f. is undefined in ARM mode
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* 0xde.. is undefined in Thumb mode
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* Instructions starting with the upper 16 bits all 0 are permanently
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* undefined. The lower 16 bits can be used for some kind of immediate.
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* --- ARMv8 ARM (ARM DDI 0487G.a C6.2.339: "UDF")
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*/
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asm volatile (".word 0xe7f7defb\n");
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asm volatile (".word 0x00001234\n");
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return CMD_RET_FAILURE;
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}
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|
||||
/*
|
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* The ID_AA64MMFR2_EL1 register name is only know to binutils for ARMv8.2
|
||||
* and later architecture revisions. However the register is valid regardless
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||||
* of binutils architecture support or the core the code is running on, so
|
||||
* just use the generic encoding.
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||||
*/
|
||||
#define ID_AA64MMFR2_EL1 "S3_0_C0_C7_2"
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|
||||
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
|
||||
{
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||||
uint64_t reg;
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||||
|
||||
/*
|
||||
* The unaligned LDAR access below is only guaranteed to generate an
|
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* alignment fault on cores not implementing FEAT_LSE2. To avoid false
|
||||
* negatives, check this condition before we exectute LDAR.
|
||||
*/
|
||||
asm ("mrs %0, "ID_AA64MMFR2_EL1"\n" : "=r" (reg));
|
||||
if (reg & GENMASK(35, 32)) {
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||||
printf("unaligned access check only supported on pre-v8.4 cores\n");
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* The load acquire instruction requires the data source to be
|
||||
* naturally aligned, and will fault even if strict alignment fault
|
||||
* checking is disabled (but only without FEAT_LSE2).
|
||||
* --- ARMv8 ARM (ARM DDI 0487G.a B2.5.2: "Alignment of data accesses")
|
||||
*/
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asm volatile (
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||||
"mov x1, sp\n\t"
|
||||
"orr x1, x1, #3\n\t"
|
||||
"ldar x0, [x1]\n"
|
||||
::: "x0", "x1" );
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||||
|
||||
return CMD_RET_FAILURE;
|
||||
}
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||||
|
||||
static int do_breakpoint(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
asm volatile ("brk #123\n");
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||||
|
||||
return CMD_RET_FAILURE;
|
||||
}
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||||
|
||||
static struct cmd_tbl cmd_sub[] = {
|
||||
U_BOOT_CMD_MKENT(breakpoint, CONFIG_SYS_MAXARGS, 1, do_breakpoint,
|
||||
"", ""),
|
||||
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
|
||||
"", ""),
|
||||
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
|
||||
"", ""),
|
||||
};
|
||||
|
|
@ -27,7 +81,9 @@ static struct cmd_tbl cmd_sub[] = {
|
|||
static char exception_help_text[] =
|
||||
"<ex>\n"
|
||||
" The following exceptions are available:\n"
|
||||
" undefined - undefined instruction\n"
|
||||
" breakpoint - breakpoint instruction exception\n"
|
||||
" unaligned - unaligned LDAR data abort\n"
|
||||
" undefined - undefined instruction exception\n"
|
||||
;
|
||||
|
||||
#include <exception.h>
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue