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configs: stm32mp1: reduce DDR_CACHEABLE_SIZE to supported 256MB DDR

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Reduces the CONFIG_DDR_CACHEABLE_SIZE, the size of DDR mapped cacheable
before relocation, to support DDR with only 256MB because the OP-TEE
reserved memory is located at end of the DDR.

By default the new size of 128MB cacheable memory is enough
in dram_bank_mmu_setup() for early_enable_caches() in arch_cpu_init()
and is correct for DDR size = 256MB.

After relocation the real size of DDR, excluding the no-map reserved
memory, is used after the U-Boot device tree parsing.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay 2023-04-27 15:36:35 +02:00 • committed by Patrice Chotard
parent 7b802e1acf
commit 2df7fc0824
2 changed files with 2 additions and 2 deletions
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2
configs/stm32mp13_defconfig
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@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk" CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk"
CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_STM32MP13x=y CONFIG_STM32MP13x=y
CONFIG_DDR_CACHEABLE_SIZE=0x10000000 CONFIG_DDR_CACHEABLE_SIZE=0x8000000
CONFIG_CMD_STM32KEY=y CONFIG_CMD_STM32KEY=y
CONFIG_TARGET_ST_STM32MP13x=y CONFIG_TARGET_ST_STM32MP13x=y
CONFIG_ENV_OFFSET_REDUND=0x940000 CONFIG_ENV_OFFSET_REDUND=0x940000

2
configs/stm32mp15_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000
CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_DDR_CACHEABLE_SIZE=0x10000000 CONFIG_DDR_CACHEABLE_SIZE=0x8000000
CONFIG_CMD_STM32KEY=y CONFIG_CMD_STM32KEY=y
CONFIG_TYPEC_STUSB160X=y CONFIG_TYPEC_STUSB160X=y
CONFIG_TARGET_ST_STM32MP15x=y CONFIG_TARGET_ST_STM32MP15x=y