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ARM: dts: stm32: set PLL4_P to 125Mhz for ETH_CLK for stm32mp157c-odyssey

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Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to
125, 62.5 and 62.5Mhz in respectively.

Signed-off-by: Heesub Shin <heesub@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Heesub Shin 2024-04-28 23:24:02 +09:00 • committed by Patrice Chotard
parent 69374aa86a
commit 2ae44edf1d
1 changed files with 2 additions and 2 deletions
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4
arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
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@ -115,11 +115,11 @@
bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
/* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
cfg = < 3 124 5 9 9 PQR(1,1,1) >;
bootph-all;
};
};