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nand: Merge changes from Linux nand driver
[backport from linux commit 02f8c6aee8df3cdc935e9bdd4f2d020306035dbe] This patch synchronizes the nand driver with the Linux 3.0 state. Signed-off-by: Christian Hitz <christian.hitz@aizo.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: minor fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Christian Hitz
Scott Wood
parent
90e3f395bf
commit
2a8e0fc8b3
3 changed files with 538 additions and 312 deletions
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@ -1,9 +1,9 @@
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/*
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* linux/include/linux/mtd/nand.h
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*
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* Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -36,17 +36,18 @@ extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
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extern int nand_scan_tail(struct mtd_info *mtd);
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/* Free resources held by the NAND device */
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extern void nand_release (struct mtd_info *mtd);
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extern void nand_release(struct mtd_info *mtd);
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/* Internal helper for board drivers which need to override command function */
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extern void nand_wait_ready(struct mtd_info *mtd);
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/* This constant declares the max. oobsize / page, which
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/*
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* This constant declares the max. oobsize / page, which
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 218
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#define NAND_MAX_PAGESIZE 4096
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#define NAND_MAX_OOBSIZE 576
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#define NAND_MAX_PAGESIZE 8192
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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@ -79,10 +80,14 @@ extern void nand_wait_ready(struct mtd_info *mtd);
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_RNDIN 0x85
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_PARAM 0xec
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_PARAM 0xec
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#define NAND_CMD_RESET 0xff
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#define NAND_CMD_LOCK 0x2a
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#define NAND_CMD_UNLOCK1 0x23
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#define NAND_CMD_UNLOCK2 0x24
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_RNDOUTSTART 0xE0
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@ -142,9 +147,10 @@ typedef enum {
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#define NAND_GET_DEVICE 0x80
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/* Option constants for bizarre disfunctionality and real
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* features
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*/
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/*
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* Option constants for bizarre disfunctionality and real
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* features.
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*/
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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@ -155,23 +161,36 @@ typedef enum {
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information */
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/*
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* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information.
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*/
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#define NAND_IS_AND 0x00000020
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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/*
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* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits.
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*/
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#define NAND_4PAGE_ARRAY 0x00000040
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/* Chip requires that BBT is periodically rewritten to prevent
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/*
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* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others. */
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* This happens with the Renesas AG-AND chips, possibly others.
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*/
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#define BBT_AUTO_REFRESH 0x00000080
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/* Chip does not require ready check on read. True
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/*
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* Chip does not require ready check on read. True
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* for all large page devices, as they do not support
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* autoincrement.*/
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* autoincrement.
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*/
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#define NAND_NO_READRDY 0x00000100
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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/* Device is one of 'new' xD cards that expose fake nand command set */
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#define NAND_BROKEN_XD 0x00000400
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/* Device behaves just like nand, but is readonly */
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#define NAND_ROM 0x00000800
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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@ -190,17 +209,29 @@ typedef enum {
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#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
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/* Non chip related options */
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/* Use a flash based bad block table. This option is passed to the
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* default bad block table function. */
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/*
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* Use a flash based bad block table. OOB identifier is saved in OOB area.
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* This option is passed to the default bad block table function.
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*/
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#define NAND_USE_FLASH_BBT 0x00010000
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00020000
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/* This option is defined if the board driver allocates its own buffers
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(e.g. because it needs them DMA-coherent */
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/*
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* This option is defined if the board driver allocates its own buffers
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* (e.g. because it needs them DMA-coherent).
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*/
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#define NAND_OWN_BUFFERS 0x00040000
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/* Chip may not exist, so silence any errors in scan */
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#define NAND_SCAN_SILENT_NODEV 0x00080000
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/*
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* If passed additionally to NAND_USE_FLASH_BBT then BBT code will not touch
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* the OOB area.
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*/
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#define NAND_USE_FLASH_BBT_NO_OOB 0x00800000
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/* Create an empty BBT with no vendor information if the BBT is available */
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#define NAND_CREATE_EMPTY_BBT 0x01000000
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/* Options set by nand scan */
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/* bbt has already been read */
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#define NAND_BBT_SCANNED 0x40000000
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x80000000
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@ -275,13 +306,13 @@ struct nand_onfi_params {
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#define ONFI_CRC_BASE 0x4F4E
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/**
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* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in progress
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* used instead of the per chip wait queue when a hw controller is available
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* @wq: wait queue to sleep on if a NAND operation is in
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* progress used instead of the per chip wait queue
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* when a hw controller is available.
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*/
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struct nand_hw_control {
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/* XXX U-BOOT XXX */
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@ -302,58 +333,50 @@ struct nand_hw_control {
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* @prepad: padding information for syndrome based ecc generators
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* @postpad: padding information for syndrome based ecc generators
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* @layout: ECC layout control struct pointer
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* @priv: pointer to private ecc control data
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* @priv: pointer to private ecc control data
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* @hwctl: function to control hardware ecc generator. Must only
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* be provided if an hardware ECC is available
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* @calculate: function for ecc calculation or readback from ecc hardware
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* @correct: function for ecc correction, matching to ecc generator (sw/hw)
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* @read_page_raw: function to read a raw page without ECC
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* @write_page_raw: function to write a raw page without ECC
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* @read_page: function to read a page according to the ecc generator requirements
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* @write_page: function to write a page according to the ecc generator requirements
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* @read_page: function to read a page according to the ecc generator
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* requirements.
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* @read_subpage: function to read parts of the page covered by ECC.
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* @write_page: function to write a page according to the ecc generator
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* requirements.
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* @read_oob: function to read chip OOB data
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* @write_oob: function to write chip OOB data
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*/
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struct nand_ecc_ctrl {
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nand_ecc_modes_t mode;
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int steps;
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int size;
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int bytes;
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int total;
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int prepad;
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int postpad;
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nand_ecc_modes_t mode;
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int steps;
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int size;
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int bytes;
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int total;
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int prepad;
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int postpad;
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struct nand_ecclayout *layout;
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void *priv;
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void (*hwctl)(struct mtd_info *mtd, int mode);
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int (*calculate)(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code);
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int (*correct)(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc,
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uint8_t *calc_ecc);
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int (*read_page_raw)(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf, int page);
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void (*write_page_raw)(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_page)(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf, int page);
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int (*read_subpage)(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint32_t offs, uint32_t len,
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uint8_t *buf);
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void (*write_page)(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_oob)(struct mtd_info *mtd,
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struct nand_chip *chip,
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int page,
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int sndcmd);
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int (*write_oob)(struct mtd_info *mtd,
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struct nand_chip *chip,
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int page);
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void *priv;
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void (*hwctl)(struct mtd_info *mtd, int mode);
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int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code);
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int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
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uint8_t *calc_ecc);
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int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page);
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void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int page);
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int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
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uint32_t offs, uint32_t len, uint8_t *buf);
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void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf);
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int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
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int sndcmd);
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int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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};
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/**
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@ -373,125 +396,150 @@ struct nand_buffers {
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/**
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* struct nand_chip - NAND Private Flash Chip Data
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
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* flash device
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
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* flash device.
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* @read_byte: [REPLACEABLE] read one byte from the chip
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* @read_word: [REPLACEABLE] read one word from the chip
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* @write_buf: [REPLACEABLE] write data from the buffer to the chip
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* @read_buf: [REPLACEABLE] read data from the chip into the buffer
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* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
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* @verify_buf: [REPLACEABLE] verify buffer contents against the chip
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* data.
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* @select_chip: [REPLACEABLE] select chip nr
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* @block_bad: [REPLACEABLE] check, if the block is bad
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* @block_markbad: [REPLACEABLE] mark the block bad
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* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
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* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
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* ALE/CLE/nCE. Also used to write command and address
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
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* If set to NULL no access to ready/busy is available and the ready/busy information
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* is read from the chip status register
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* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
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* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
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* @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
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* mtd->oobsize, mtd->writesize and so on.
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* @id_data contains the 8 bytes values of NAND_CMD_READID.
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* Return with the bus width.
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing
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* device ready/busy line. If set to NULL no access to
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* ready/busy is available and the ready/busy information
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* is read from the chip status register.
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* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
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* commands to the chip.
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* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
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* ready.
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* @ecc: [BOARDSPECIFIC] ecc control ctructure
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* @buffers: buffer structure for read/write
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* @hwcontrol: platform-specific hardware control structure
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* @ops: oob operation operands
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* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
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* @erase_cmd: [INTERN] erase command write function, selectable due
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* to AND support.
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* @scan_bbt: [REPLACEABLE] function to scan bad block table
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
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* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
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* data from array to read regs (tR).
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* @state: [INTERN] the current state of the NAND device
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* @oob_poi: poison value buffer
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* @page_shift: [INTERN] number of address bits in a page (column address bits)
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* @page_shift: [INTERN] number of address bits in a page (column
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* address bits).
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* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
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* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
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* @chip_shift: [INTERN] number of address bits in one chip
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* @datbuf: [INTERN] internal buffer for one page + oob
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* @oobbuf: [INTERN] oob buffer for one eraseblock
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* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
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* @data_poi: [INTERN] pointer to a data buffer
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* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
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* special functionality. See the defines for further explanation
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* @badblockpos: [INTERN] position of the bad block marker in the oob area
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* @options: [BOARDSPECIFIC] various chip options. They can partly
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* be set to inform nand_scan about special functionality.
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* See the defines for further explanation.
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* @badblockpos: [INTERN] position of the bad block marker in the oob
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* area.
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* @badblockbits: [INTERN] number of bits to left-shift the bad block
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* number
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* @cellinfo: [INTERN] MLC/multichip data from chip ident
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
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* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
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* @pagebuf: [INTERN] holds the pagenumber which is currently in
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* data_buf.
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* @subpagesize: [INTERN] holds the subpagesize
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* @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
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* non 0 if ONFI supported.
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* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
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* supported, 0 otherwise.
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* @ecclayout: [REPLACEABLE] the default ecc placement scheme
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* @bbt: [INTERN] bad block table pointer
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
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* lookup.
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* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
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* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
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* @controller: [REPLACEABLE] a pointer to a hardware controller structure
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* which is shared among multiple independend devices
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* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
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* bad block scan.
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* @controller: [REPLACEABLE] a pointer to a hardware controller
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* structure which is shared among multiple independend
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* devices.
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* @priv: [OPTIONAL] pointer to private chip date
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* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
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* (determine if errors are correctable)
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* @errstat: [OPTIONAL] hardware specific function to perform
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* additional error status checks (determine if errors are
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* correctable).
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* @write_page: [REPLACEABLE] High-level page write function
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*/
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struct nand_chip {
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void __iomem *IO_ADDR_R;
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void __iomem *IO_ADDR_W;
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void __iomem *IO_ADDR_R;
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void __iomem *IO_ADDR_W;
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uint8_t (*read_byte)(struct mtd_info *mtd);
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u16 (*read_word)(struct mtd_info *mtd);
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void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
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void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
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int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
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void (*select_chip)(struct mtd_info *mtd, int chip);
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int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
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int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
|
||||
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw);
|
||||
uint8_t (*read_byte)(struct mtd_info *mtd);
|
||||
u16 (*read_word)(struct mtd_info *mtd);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
||||
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
||||
int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
|
||||
u8 *id_data);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
|
||||
int page_addr);
|
||||
int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
|
||||
int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw);
|
||||
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int numchips;
|
||||
uint64_t chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
int onfi_version;
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int numchips;
|
||||
uint64_t chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
int badblockbits;
|
||||
|
||||
int onfi_version;
|
||||
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
struct nand_onfi_params onfi_params;
|
||||
#endif
|
||||
|
||||
int state;
|
||||
int state;
|
||||
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
|
||||
struct nand_ecc_ctrl ecc;
|
||||
struct nand_buffers *buffers;
|
||||
|
||||
struct nand_hw_control hwcontrol;
|
||||
|
||||
struct mtd_oob_ops ops;
|
||||
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
|
||||
void *priv;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -535,7 +583,7 @@ struct nand_flash_dev {
|
|||
*/
|
||||
struct nand_manufacturers {
|
||||
int id;
|
||||
char * name;
|
||||
char *name;
|
||||
};
|
||||
|
||||
extern const struct nand_flash_dev nand_flash_ids[];
|
||||
|
|
@ -548,7 +596,7 @@ extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
|
|||
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
||||
int allowbbt);
|
||||
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
size_t * retlen, uint8_t * buf);
|
||||
size_t *retlen, uint8_t *buf);
|
||||
|
||||
/*
|
||||
* Constants for oob configuration
|
||||
|
|
@ -569,17 +617,20 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|||
* @priv: hardware controller specific settings
|
||||
*/
|
||||
struct platform_nand_chip {
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
const char **part_probe_types;
|
||||
void *priv;
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
const char **part_probe_types;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/* Keep gcc happy */
|
||||
struct platform_device;
|
||||
|
||||
/**
|
||||
* struct platform_nand_ctrl - controller level device structure
|
||||
* @hwcontrol: platform specific hardware control structure
|
||||
|
|
@ -592,12 +643,11 @@ struct platform_nand_chip {
|
|||
* All fields are optional and depend on the hardware driver requirements
|
||||
*/
|
||||
struct platform_nand_ctrl {
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
void *priv;
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -606,8 +656,8 @@ struct platform_nand_ctrl {
|
|||
* @ctrl: controller level device structure
|
||||
*/
|
||||
struct platform_nand_data {
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
};
|
||||
|
||||
/* Some helpers to access the data structures */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue