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m68k: Remove CONFIG_FSLDMAFEC
There are no platforms which enable this feature, so remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
56ea7c8b75
commit
2a7ea65037
14 changed files with 2 additions and 4841 deletions
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@ -1,151 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef fsl_mcdmafec_h
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#define fsl_mcdmafec_h
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/* Re-use of the definitions */
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#include <asm/fec.h>
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typedef struct fecdma {
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u32 rsvd0; /* 0x000 */
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u32 eir; /* 0x004 */
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u32 eimr; /* 0x008 */
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u32 rsvd1[6]; /* 0x00C - 0x023 */
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u32 ecr; /* 0x024 */
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u32 rsvd2[6]; /* 0x028 - 0x03F */
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u32 mmfr; /* 0x040 */
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u32 mscr; /* 0x044 */
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u32 rsvd3[7]; /* 0x048 - 0x063 */
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u32 mibc; /* 0x064 */
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u32 rsvd4[7]; /* 0x068 - 0x083 */
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u32 rcr; /* 0x084 */
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u32 rhr; /* 0x088 */
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u32 rsvd5[14]; /* 0x08C - 0x0C3 */
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u32 tcr; /* 0x0C4 */
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u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
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u32 palr; /* 0x0E4 */
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u32 paur; /* 0x0E8 */
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u32 opd; /* 0x0EC */
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u32 rsvd7[10]; /* 0x0F0 - 0x117 */
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u32 iaur; /* 0x118 */
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u32 ialr; /* 0x11C */
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u32 gaur; /* 0x120 */
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u32 galr; /* 0x124 */
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u32 rsvd8[7]; /* 0x128 - 0x143 */
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u32 tfwr; /* 0x144 */
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u32 rsvd9[14]; /* 0x148 - 0x17F */
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u32 fmc; /* 0x180 */
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u32 rfdr; /* 0x184 */
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u32 rfsr; /* 0x188 */
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u32 rfcr; /* 0x18C */
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u32 rlrfp; /* 0x190 */
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u32 rlwfp; /* 0x194 */
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u32 rfar; /* 0x198 */
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u32 rfrp; /* 0x19C */
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u32 rfwp; /* 0x1A0 */
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u32 tfdr; /* 0x1A4 */
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u32 tfsr; /* 0x1A8 */
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u32 tfcr; /* 0x1AC */
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u32 tlrfp; /* 0x1B0 */
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u32 tlwfp; /* 0x1B4 */
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u32 tfar; /* 0x1B8 */
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u32 tfrp; /* 0x1BC */
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u32 tfwp; /* 0x1C0 */
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u32 frst; /* 0x1C4 */
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u32 ctcwr; /* 0x1C8 */
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} fecdma_t;
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struct fec_info_dma {
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int index;
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u32 iobase;
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u32 pinmux;
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u32 miibase;
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int phy_addr;
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int dup_spd;
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char *phy_name;
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int phyname_init;
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cbd_t *rxbd; /* Rx BD */
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cbd_t *txbd; /* Tx BD */
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uint rx_idx;
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uint tx_idx;
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char *txbuf;
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int initialized;
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struct fec_info_dma *next;
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u16 rx_task; /* DMA receive Task Number */
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u16 tx_task; /* DMA Transmit Task Number */
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u16 rx_pri; /* DMA Receive Priority */
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u16 tx_pri; /* DMA Transmit Priority */
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u16 rx_init; /* DMA Receive Initiator */
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u16 tx_init; /* DMA Transmit Initiator */
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u16 used_tbd_idx; /* next transmit BD to clean */
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u16 clean_tbd_num; /* the number of available transmit BDs */
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int to_loop;
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struct mii_dev *bus;
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};
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/* Bit definitions and macros for IEVENT */
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#define FEC_EIR_TXERR (0x00040000)
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#define FEC_EIR_RXERR (0x00020000)
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#undef FEC_EIR_CLEAR_ALL
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#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
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/* Bit definitions and macros for R_HASH */
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#define FEC_RHASH_FCE_DC (0x80000000)
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#define FEC_RHASH_MULTCAST (0x40000000)
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#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
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/* Bit definitions and macros for FEC_TFWR */
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#undef FEC_TFWR_X_WMRK
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#undef FEC_TFWR_X_WMRK_64
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#undef FEC_TFWR_X_WMRK_128
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#undef FEC_TFWR_X_WMRK_192
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#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
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#define FEC_TFWR_X_WMRK_64 (0x00)
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#define FEC_TFWR_X_WMRK_128 (0x01)
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#define FEC_TFWR_X_WMRK_192 (0x02)
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#define FEC_TFWR_X_WMRK_256 (0x03)
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#define FEC_TFWR_X_WMRK_320 (0x04)
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#define FEC_TFWR_X_WMRK_384 (0x05)
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#define FEC_TFWR_X_WMRK_448 (0x06)
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#define FEC_TFWR_X_WMRK_512 (0x07)
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#define FEC_TFWR_X_WMRK_576 (0x08)
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#define FEC_TFWR_X_WMRK_640 (0x09)
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#define FEC_TFWR_X_WMRK_704 (0x0A)
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#define FEC_TFWR_X_WMRK_768 (0x0B)
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#define FEC_TFWR_X_WMRK_832 (0x0C)
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#define FEC_TFWR_X_WMRK_896 (0x0D)
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#define FEC_TFWR_X_WMRK_960 (0x0E)
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#define FEC_TFWR_X_WMRK_1024 (0x0F)
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/* FIFO definitions */
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/* Bit definitions and macros for FSTAT */
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#define FIFO_STAT_IP (0x80000000)
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#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
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#define FIFO_STAT_FAE (0x00800000)
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#define FIFO_STAT_RXW (0x00400000)
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#define FIFO_STAT_UF (0x00200000)
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#define FIFO_STAT_OF (0x00100000)
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#define FIFO_STAT_FR (0x00080000)
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#define FIFO_STAT_FULL (0x00040000)
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#define FIFO_STAT_ALARM (0x00020000)
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#define FIFO_STAT_EMPTY (0x00010000)
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/* Bit definitions and macros for FCTRL */
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#define FIFO_CTRL_WCTL (0x40000000)
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#define FIFO_CTRL_WFR (0x20000000)
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#define FIFO_CTRL_FRAME (0x08000000)
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#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
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#define FIFO_CTRL_IPMASK (0x00800000)
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#define FIFO_CTRL_FAEMASK (0x00400000)
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#define FIFO_CTRL_RXWMASK (0x00200000)
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#define FIFO_CTRL_UFMASK (0x00100000)
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#define FIFO_CTRL_OFMASK (0x00080000)
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#endif /* fsl_mcdmafec_h */
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@ -314,21 +314,6 @@
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#include <asm/immap_547x_8x.h>
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#include <asm/m547x_8x.h>
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#ifdef CONFIG_FSLDMAFEC
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#define FEC0_RX_TASK 0
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#define FEC0_TX_TASK 1
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#define FEC0_RX_PRIORITY 6
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#define FEC0_TX_PRIORITY 7
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#define FEC0_RX_INIT 16
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#define FEC0_TX_INIT 17
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#define FEC1_RX_TASK 2
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#define FEC1_TX_TASK 3
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#define FEC1_RX_PRIORITY 6
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#define FEC1_TX_PRIORITY 7
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#define FEC1_RX_INIT 30
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#define FEC1_TX_INIT 31
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#endif
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
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#ifdef CONFIG_SLTTMR
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@ -10,7 +10,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
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#if defined(CONFIG_MCFFEC)
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static int fec_get_node(int fec_idx)
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{
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char fec_alias[5] = {"fec"};
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@ -77,4 +77,4 @@ int fec_get_mii_base(int fec_idx, u32 *mii_base)
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return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
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}
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#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC
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#endif //CONFIG_MCFFEC
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@ -87,7 +87,6 @@ endif
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config DMA_LEGACY
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bool "Legacy DMA support"
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default y if FSLDMAFEC
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help
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Enable legacy DMA support. This does not use driver model and should
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be migrated to the new API.
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,225 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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/* Functions for initializing variable tables of different types of tasks. */
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/*
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* Do not edit!
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*/
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#include <MCD_dma.h>
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extern dmaRegs *MCD_dmaBar;
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/* Task 0 */
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void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
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int xferSize, short xferSizeIncr, int *cSave,
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volatile TaskTableEntry * taskTable, int channel)
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{
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volatile TaskTableEntry *taskChan = taskTable + channel;
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MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
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MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
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MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
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MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */
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MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
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MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
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MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
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MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */
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MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
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MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
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MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
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MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
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MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
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MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
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MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
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MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
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MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */
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MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */
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MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
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MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */
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MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
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MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
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MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */
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MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */
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/* Set the task's Enable bit in its Task Control Register */
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MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
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}
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/* Task 1 */
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void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
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short destIncr, int dmaSize, short xferSizeIncr,
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int flags, int *currBD, int *cSave,
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volatile TaskTableEntry * taskTable, int channel)
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{
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volatile TaskTableEntry *taskChan = taskTable + channel;
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MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */
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MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
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MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */
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MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
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MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */
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MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
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MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */
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MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */
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MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
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MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
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MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
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MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
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MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */
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MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */
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MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
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MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */
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MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */
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/* Set the task's Enable bit in its Task Control Register */
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MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
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}
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/* Task 2 */
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void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
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int xferSize, short xferSizeIncr, int *cSave,
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volatile TaskTableEntry * taskTable, int channel)
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{
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volatile TaskTableEntry *taskChan = taskTable + channel;
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MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
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MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
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MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
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MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */
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MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
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MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
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MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
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MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
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MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
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MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
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MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
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MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
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MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
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MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
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MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
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MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */
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MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */
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MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */
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MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */
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MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */
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MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */
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MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */
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MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
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MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
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MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */
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MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
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MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
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/* Set the task's Enable bit in its Task Control Register */
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MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
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}
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/* Task 3 */
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void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
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short destIncr, int dmaSize, short xferSizeIncr,
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int flags, int *currBD, int *cSave,
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volatile TaskTableEntry * taskTable, int channel)
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{
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volatile TaskTableEntry *taskChan = taskTable + channel;
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MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */
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MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
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MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */
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MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
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MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */
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MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
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MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */
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MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
|
||||
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */
|
||||
MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */
|
||||
MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */
|
||||
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
|
||||
MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
|
||||
}
|
||||
|
||||
/* Task 4 */
|
||||
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
|
||||
volatile TaskTableEntry * taskTable, int channel)
|
||||
{
|
||||
volatile TaskTableEntry *taskChan = taskTable + channel;
|
||||
|
||||
MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
|
||||
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */
|
||||
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */
|
||||
MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */
|
||||
MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */
|
||||
MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */
|
||||
MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
|
||||
MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
|
||||
MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */
|
||||
MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
|
||||
}
|
||||
|
||||
/* Task 5 */
|
||||
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
|
||||
volatile TaskTableEntry * taskTable, int channel)
|
||||
{
|
||||
volatile TaskTableEntry *taskChan = taskTable + channel;
|
||||
|
||||
MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
|
||||
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */
|
||||
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
|
||||
MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */
|
||||
MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */
|
||||
MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
|
||||
MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */
|
||||
MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
|
||||
MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
|
||||
MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */
|
||||
MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */
|
||||
MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */
|
||||
MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */
|
||||
MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
|
||||
}
|
||||
|
|
@ -5,7 +5,6 @@
|
|||
|
||||
obj-$(CONFIG_DMA) += dma-uclass.o
|
||||
|
||||
obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
|
||||
obj-$(CONFIG_APBH_DMA) += apbh_dma.o
|
||||
obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o
|
||||
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
|
||||
|
|
|
|||
|
|
@ -471,14 +471,6 @@ config SYS_UNIFY_CACHE
|
|||
depends on MCFFEC
|
||||
bool "Invalidate icache during ethernet operations"
|
||||
|
||||
config FSLDMAFEC
|
||||
bool "ColdFire DMA Ethernet Support"
|
||||
select PHYLIB
|
||||
select SYS_DISCOVER_PHY
|
||||
help
|
||||
This driver supports the network interface units in the
|
||||
ColdFire family.
|
||||
|
||||
config KS8851_MLL
|
||||
bool "Microchip KS8851-MLL controller driver"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@ obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
|
|||
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
|
||||
obj-$(CONFIG_FMAN_ENET) += fm/
|
||||
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
|
||||
obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
|
||||
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
|
||||
obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
|
||||
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
|
||||
|
|
|
|||
|
|
@ -1,592 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
||||
*
|
||||
* Conversion to DM
|
||||
* (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <hang.h>
|
||||
#include <malloc.h>
|
||||
#include <command.h>
|
||||
#include <config.h>
|
||||
#include <net.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mii.h>
|
||||
#include <asm/immap.h>
|
||||
#include <asm/fsl_mcdmafec.h>
|
||||
|
||||
#include "MCD_dma.h"
|
||||
|
||||
#undef ET_DEBUG
|
||||
#undef MII_DEBUG
|
||||
|
||||
/* Ethernet Transmit and Receive Buffers */
|
||||
#define DBUF_LENGTH 1520
|
||||
#define PKT_MAXBUF_SIZE 1518
|
||||
#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
|
||||
|
||||
/* RxBD bits definitions */
|
||||
#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
|
||||
BD_ENET_RX_OV | BD_ENET_RX_TR)
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void init_eth_info(struct fec_info_dma *info)
|
||||
{
|
||||
/* setup Receive and Transmit buffer descriptor */
|
||||
#ifdef CFG_SYS_FEC_BUF_USE_SRAM
|
||||
static u32 tmp;
|
||||
|
||||
if (info->index == 0)
|
||||
tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
|
||||
else
|
||||
info->rxbd = (cbd_t *)DBUF_LENGTH;
|
||||
|
||||
info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
|
||||
tmp = (u32)info->rxbd;
|
||||
info->txbd =
|
||||
(cbd_t *)((u32)info->txbd + tmp +
|
||||
(PKTBUFSRX * sizeof(cbd_t)));
|
||||
tmp = (u32)info->txbd;
|
||||
info->txbuf =
|
||||
(char *)((u32)info->txbuf + tmp +
|
||||
(CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
|
||||
tmp = (u32)info->txbuf;
|
||||
#else
|
||||
info->rxbd =
|
||||
(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
|
||||
(PKTBUFSRX * sizeof(cbd_t)));
|
||||
info->txbd =
|
||||
(cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
|
||||
(CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
|
||||
info->txbuf =
|
||||
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
|
||||
#endif
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
|
||||
#endif
|
||||
info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
|
||||
}
|
||||
|
||||
static void fec_halt(struct udevice *dev)
|
||||
{
|
||||
struct fec_info_dma *info = dev_get_priv(dev);
|
||||
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
|
||||
int counter = 0xffff;
|
||||
|
||||
/* issue graceful stop command to the FEC transmitter if necessary */
|
||||
fecp->tcr |= FEC_TCR_GTS;
|
||||
|
||||
/* wait for graceful stop to register */
|
||||
while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
|
||||
;
|
||||
|
||||
/* Disable DMA tasks */
|
||||
MCD_killDma(info->tx_task);
|
||||
MCD_killDma(info->rx_task);
|
||||
|
||||
/* Disable the Ethernet Controller */
|
||||
fecp->ecr &= ~FEC_ECR_ETHER_EN;
|
||||
|
||||
/* Clear FIFO status registers */
|
||||
fecp->rfsr &= FIFO_ERRSTAT;
|
||||
fecp->tfsr &= FIFO_ERRSTAT;
|
||||
|
||||
fecp->frst = 0x01000000;
|
||||
|
||||
/* Issue a reset command to the FEC chip */
|
||||
fecp->ecr |= FEC_ECR_RESET;
|
||||
|
||||
/* wait at least 20 clock cycles */
|
||||
mdelay(10);
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("Ethernet task stopped\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
static void dbg_fec_regs(struct eth_device *dev)
|
||||
{
|
||||
struct fec_info_dma *info = dev->priv;
|
||||
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
|
||||
|
||||
printf("=====\n");
|
||||
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
|
||||
printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
|
||||
printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
|
||||
printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
|
||||
printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
|
||||
printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
|
||||
printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
|
||||
printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
|
||||
printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
|
||||
printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
|
||||
printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
|
||||
printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
|
||||
printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
|
||||
printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
|
||||
printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
|
||||
printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
|
||||
printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
|
||||
printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
|
||||
printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
|
||||
printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
|
||||
printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
|
||||
printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
|
||||
printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
|
||||
printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
|
||||
printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
|
||||
printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
|
||||
printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
|
||||
printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
|
||||
printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
|
||||
printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
|
||||
printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
|
||||
printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
|
||||
printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
|
||||
printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
|
||||
printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
|
||||
{
|
||||
struct bd_info *bd = gd->bd;
|
||||
|
||||
if ((dup_spd >> 16) == FULL) {
|
||||
/* Set maximum frame length */
|
||||
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
|
||||
FEC_RCR_PROM | 0x100;
|
||||
fecp->tcr = FEC_TCR_FDEN;
|
||||
} else {
|
||||
/* Half duplex mode */
|
||||
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
|
||||
FEC_RCR_MII_MODE | FEC_RCR_DRT;
|
||||
fecp->tcr &= ~FEC_TCR_FDEN;
|
||||
}
|
||||
|
||||
if ((dup_spd & 0xFFFF) == _100BASET) {
|
||||
#ifdef MII_DEBUG
|
||||
printf("100Mbps\n");
|
||||
#endif
|
||||
bd->bi_ethspeed = 100;
|
||||
} else {
|
||||
#ifdef MII_DEBUG
|
||||
printf("10Mbps\n");
|
||||
#endif
|
||||
bd->bi_ethspeed = 10;
|
||||
}
|
||||
}
|
||||
|
||||
static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
|
||||
{
|
||||
u8 curr_byte; /* byte for which to compute the CRC */
|
||||
int byte; /* loop - counter */
|
||||
int bit; /* loop - counter */
|
||||
u32 crc = 0xffffffff; /* initial value */
|
||||
|
||||
for (byte = 0; byte < 6; byte++) {
|
||||
curr_byte = mac[byte];
|
||||
for (bit = 0; bit < 8; bit++) {
|
||||
if ((curr_byte & 0x01) ^ (crc & 0x01)) {
|
||||
crc >>= 1;
|
||||
crc = crc ^ 0xedb88320;
|
||||
} else {
|
||||
crc >>= 1;
|
||||
}
|
||||
curr_byte >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
crc = crc >> 26;
|
||||
|
||||
/* Set individual hash table register */
|
||||
if (crc >= 32) {
|
||||
fecp->ialr = (1 << (crc - 32));
|
||||
fecp->iaur = 0;
|
||||
} else {
|
||||
fecp->ialr = 0;
|
||||
fecp->iaur = (1 << crc);
|
||||
}
|
||||
|
||||
/* Set physical address */
|
||||
fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
|
||||
fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
|
||||
|
||||
/* Clear multicast address hash table */
|
||||
fecp->gaur = 0;
|
||||
fecp->galr = 0;
|
||||
}
|
||||
|
||||
static int fec_init(struct udevice *dev)
|
||||
{
|
||||
struct fec_info_dma *info = dev_get_priv(dev);
|
||||
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
|
||||
int rval, i;
|
||||
uchar enetaddr[6];
|
||||
|
||||
#ifdef ET_DEBUG
|
||||
printf("fec_init: iobase 0x%08x ...\n", info->iobase);
|
||||
#endif
|
||||
|
||||
fecpin_setclear(info, 1);
|
||||
fec_halt(dev);
|
||||
|
||||
mii_init();
|
||||
set_fec_duplex_speed(fecp, info->dup_spd);
|
||||
|
||||
/* We use strictly polling mode only */
|
||||
fecp->eimr = 0;
|
||||
|
||||
/* Clear any pending interrupt */
|
||||
fecp->eir = 0xffffffff;
|
||||
|
||||
/* Set station address */
|
||||
if (info->index == 0)
|
||||
rval = eth_env_get_enetaddr("ethaddr", enetaddr);
|
||||
else
|
||||
rval = eth_env_get_enetaddr("eth1addr", enetaddr);
|
||||
|
||||
if (!rval) {
|
||||
puts("Please set a valid MAC address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fec_set_hwaddr(fecp, enetaddr);
|
||||
|
||||
/* Set Opcode/Pause Duration Register */
|
||||
fecp->opd = 0x00010020;
|
||||
|
||||
/* Setup Buffers and Buffer Descriptors */
|
||||
info->rx_idx = 0;
|
||||
info->tx_idx = 0;
|
||||
|
||||
/* Setup Receiver Buffer Descriptors (13.14.24.18)
|
||||
* Settings: Empty, Wrap */
|
||||
for (i = 0; i < PKTBUFSRX; i++) {
|
||||
info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
|
||||
info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
|
||||
info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
|
||||
}
|
||||
info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
|
||||
|
||||
/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
|
||||
* Settings: Last, Tx CRC */
|
||||
for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
|
||||
info->txbd[i].cbd_sc = 0;
|
||||
info->txbd[i].cbd_datlen = 0;
|
||||
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
|
||||
}
|
||||
info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
|
||||
|
||||
info->used_tbd_idx = 0;
|
||||
info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
|
||||
|
||||
/* Set Rx FIFO alarm and granularity value */
|
||||
fecp->rfcr = 0x0c000000;
|
||||
fecp->rfar = 0x0000030c;
|
||||
|
||||
/* Set Tx FIFO granularity value */
|
||||
fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
|
||||
fecp->tfar = 0x00000080;
|
||||
|
||||
fecp->tfwr = 0x2;
|
||||
fecp->ctcwr = 0x03000000;
|
||||
|
||||
/* Enable DMA receive task */
|
||||
MCD_startDma(info->rx_task,
|
||||
(s8 *)info->rxbd,
|
||||
0,
|
||||
(s8 *)&fecp->rfdr,
|
||||
4,
|
||||
0,
|
||||
4,
|
||||
info->rx_init,
|
||||
info->rx_pri,
|
||||
(MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
|
||||
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
|
||||
);
|
||||
|
||||
/* Enable DMA tx task with no ready buffer descriptors */
|
||||
MCD_startDma(info->tx_task,
|
||||
(s8 *)info->txbd,
|
||||
0,
|
||||
(s8 *)&fecp->tfdr,
|
||||
4,
|
||||
0,
|
||||
4,
|
||||
info->tx_init,
|
||||
info->tx_pri,
|
||||
(MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
|
||||
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
|
||||
);
|
||||
|
||||
/* Now enable the transmit and receive processing */
|
||||
fecp->ecr |= FEC_ECR_ETHER_EN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mcdmafec_init(struct udevice *dev)
|
||||
{
|
||||
return fec_init(dev);
|
||||
}
|
||||
|
||||
static int mcdmafec_send(struct udevice *dev, void *packet, int length)
|
||||
{
|
||||
struct fec_info_dma *info = dev_get_priv(dev);
|
||||
cbd_t *p_tbd, *p_used_tbd;
|
||||
u16 phy_status;
|
||||
|
||||
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
|
||||
|
||||
/* process all the consumed TBDs */
|
||||
while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
|
||||
p_used_tbd = &info->txbd[info->used_tbd_idx];
|
||||
if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
|
||||
#ifdef ET_DEBUG
|
||||
printf("Cannot clean TBD %d, in use\n",
|
||||
info->clean_tbd_num);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* clean this buffer descriptor */
|
||||
if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
|
||||
p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
|
||||
else
|
||||
p_used_tbd->cbd_sc = 0;
|
||||
|
||||
/* update some indeces for a correct handling of TBD ring */
|
||||
info->clean_tbd_num++;
|
||||
info->used_tbd_idx = (info->used_tbd_idx + 1)
|
||||
% CFG_SYS_TX_ETH_BUFFER;
|
||||
}
|
||||
|
||||
/* Check for valid length of data. */
|
||||
if (length > 1500 || length <= 0)
|
||||
return -1;
|
||||
|
||||
/* Check the number of vacant TxBDs. */
|
||||
if (info->clean_tbd_num < 1) {
|
||||
printf("No available TxBDs ...\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Get the first TxBD to send the mac header */
|
||||
p_tbd = &info->txbd[info->tx_idx];
|
||||
p_tbd->cbd_datlen = length;
|
||||
p_tbd->cbd_bufaddr = (u32)packet;
|
||||
p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
|
||||
info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
|
||||
|
||||
/* Enable DMA transmit task */
|
||||
MCD_continDma(info->tx_task);
|
||||
|
||||
info->clean_tbd_num -= 1;
|
||||
|
||||
/* wait until frame is sent . */
|
||||
while (p_tbd->cbd_sc & BD_ENET_TX_READY)
|
||||
udelay(10);
|
||||
|
||||
return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
|
||||
}
|
||||
|
||||
static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
|
||||
{
|
||||
struct fec_info_dma *info = dev_get_priv(dev);
|
||||
volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
|
||||
|
||||
cbd_t *prbd = &info->rxbd[info->rx_idx];
|
||||
u32 ievent;
|
||||
int frame_length, len = 0;
|
||||
|
||||
/* Check if any critical events have happened */
|
||||
ievent = fecp->eir;
|
||||
if (ievent != 0) {
|
||||
fecp->eir = ievent;
|
||||
|
||||
if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
|
||||
printf("fec_recv: error\n");
|
||||
fec_halt(dev);
|
||||
fec_init(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ievent & FEC_EIR_HBERR) {
|
||||
/* Heartbeat error */
|
||||
fecp->tcr |= FEC_TCR_GTS;
|
||||
}
|
||||
|
||||
if (ievent & FEC_EIR_GRA) {
|
||||
/* Graceful stop complete */
|
||||
if (fecp->tcr & FEC_TCR_GTS) {
|
||||
printf("fec_recv: tcr_gts\n");
|
||||
fec_halt(dev);
|
||||
fecp->tcr &= ~FEC_TCR_GTS;
|
||||
fec_init(dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
|
||||
if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
|
||||
!(prbd->cbd_sc & BD_ENET_RX_ERR) &&
|
||||
((prbd->cbd_datlen - 4) > 14)) {
|
||||
/* Get buffer address and size */
|
||||
frame_length = prbd->cbd_datlen - 4;
|
||||
|
||||
/* Fill the buffer and pass it to upper layers */
|
||||
net_process_received_packet((uchar *)prbd->cbd_bufaddr,
|
||||
frame_length);
|
||||
len = frame_length;
|
||||
}
|
||||
|
||||
/* Reset buffer descriptor as empty */
|
||||
if (info->rx_idx == (PKTBUFSRX - 1))
|
||||
prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
|
||||
else
|
||||
prbd->cbd_sc = BD_ENET_RX_EMPTY;
|
||||
|
||||
prbd->cbd_datlen = PKTSIZE_ALIGN;
|
||||
|
||||
/* Now, we have an empty RxBD, restart the DMA receive task */
|
||||
MCD_continDma(info->rx_task);
|
||||
|
||||
/* Increment BD count */
|
||||
info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static void mcdmafec_halt(struct udevice *dev)
|
||||
{
|
||||
fec_halt(dev);
|
||||
}
|
||||
|
||||
static const struct eth_ops mcdmafec_ops = {
|
||||
.start = mcdmafec_init,
|
||||
.send = mcdmafec_send,
|
||||
.recv = mcdmafec_recv,
|
||||
.stop = mcdmafec_halt,
|
||||
};
|
||||
|
||||
/*
|
||||
* Boot sequence, called just after mcffec_of_to_plat,
|
||||
* as DM way, it replaces old mcffec_initialize.
|
||||
*/
|
||||
static int mcdmafec_probe(struct udevice *dev)
|
||||
{
|
||||
struct fec_info_dma *info = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
int node = dev_of_offset(dev);
|
||||
int retval;
|
||||
const u32 *val;
|
||||
|
||||
info->index = dev_seq(dev);
|
||||
info->iobase = pdata->iobase;
|
||||
info->miibase = pdata->iobase;
|
||||
info->phy_addr = -1;
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
|
||||
if (val)
|
||||
info->rx_task = fdt32_to_cpu(*val);
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
|
||||
if (val)
|
||||
info->tx_task = fdt32_to_cpu(*val);
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
|
||||
if (val)
|
||||
info->rx_pri = fdt32_to_cpu(*val);
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
|
||||
if (val)
|
||||
info->tx_pri = fdt32_to_cpu(*val);
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
|
||||
if (val)
|
||||
info->rx_init = fdt32_to_cpu(*val);
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
|
||||
if (val)
|
||||
info->tx_init = fdt32_to_cpu(*val);
|
||||
|
||||
#ifdef CFG_SYS_FEC_BUF_USE_SRAM
|
||||
u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
|
||||
#endif
|
||||
init_eth_info(info);
|
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
||||
info->bus = mdio_alloc();
|
||||
if (!info->bus)
|
||||
return -ENOMEM;
|
||||
strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
|
||||
info->bus->read = mcffec_miiphy_read;
|
||||
info->bus->write = mcffec_miiphy_write;
|
||||
|
||||
retval = mdio_register(info->bus);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mcdmafec_remove(struct udevice *dev)
|
||||
{
|
||||
struct fec_info_dma *priv = dev_get_priv(dev);
|
||||
|
||||
mdio_unregister(priv->bus);
|
||||
mdio_free(priv->bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Boot sequence, called 1st
|
||||
*/
|
||||
static int mcdmafec_of_to_plat(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
const u32 *val;
|
||||
|
||||
pdata->iobase = dev_read_addr(dev);
|
||||
/* Default to 10Mbit/s */
|
||||
pdata->max_speed = 10;
|
||||
|
||||
val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
|
||||
if (val)
|
||||
pdata->max_speed = fdt32_to_cpu(*val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id mcdmafec_ids[] = {
|
||||
{ .compatible = "fsl,mcf-dma-fec" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mcffec) = {
|
||||
.name = "mcdmafec",
|
||||
.id = UCLASS_ETH,
|
||||
.of_match = mcdmafec_ids,
|
||||
.of_to_plat = mcdmafec_of_to_plat,
|
||||
.probe = mcdmafec_probe,
|
||||
.remove = mcdmafec_remove,
|
||||
.ops = &mcdmafec_ops,
|
||||
.priv_auto = sizeof(struct fec_info_dma),
|
||||
.plat_auto = sizeof(struct eth_pdata),
|
||||
};
|
||||
|
|
@ -1,369 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _MCD_API_H
|
||||
#define _MCD_API_H
|
||||
|
||||
/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
|
||||
#undef MCD_INCLUDE_EU
|
||||
|
||||
/* Number of DMA channels */
|
||||
#define NCHANNELS 16
|
||||
|
||||
/* Total number of variants */
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
#define NUMOFVARIANTS 6
|
||||
#else
|
||||
#define NUMOFVARIANTS 4
|
||||
#endif
|
||||
|
||||
/* Define sizes of the various tables */
|
||||
#define TASK_TABLE_SIZE (NCHANNELS*32)
|
||||
#define VAR_TAB_SIZE (128)
|
||||
#define CONTEXT_SAVE_SIZE (128)
|
||||
#define FUNCDESC_TAB_SIZE (256)
|
||||
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
#define FUNCDESC_TAB_NUM 16
|
||||
#else
|
||||
#define FUNCDESC_TAB_NUM 1
|
||||
#endif
|
||||
|
||||
#ifndef DEFINESONLY
|
||||
|
||||
/* Portability typedefs */
|
||||
#if 1
|
||||
#include "common.h"
|
||||
#else
|
||||
#ifndef s32
|
||||
typedef int s32;
|
||||
#endif
|
||||
#ifndef u32
|
||||
typedef unsigned int u32;
|
||||
#endif
|
||||
#ifndef s16
|
||||
typedef short s16;
|
||||
#endif
|
||||
#ifndef u16
|
||||
typedef unsigned short u16;
|
||||
#endif
|
||||
#ifndef s8
|
||||
typedef char s8;
|
||||
#endif
|
||||
#ifndef u8
|
||||
typedef unsigned char u8;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These structures represent the internal registers of the
|
||||
* multi-channel DMA
|
||||
*/
|
||||
struct dmaRegs_s {
|
||||
u32 taskbar; /* task table base address */
|
||||
u32 currPtr;
|
||||
u32 endPtr;
|
||||
u32 varTablePtr;
|
||||
u16 dma_rsvd0;
|
||||
u16 ptdControl; /* ptd control */
|
||||
u32 intPending; /* interrupt pending */
|
||||
u32 intMask; /* interrupt mask */
|
||||
u16 taskControl[16]; /* task control */
|
||||
u8 priority[32]; /* priority */
|
||||
u32 initiatorMux; /* initiator mux control */
|
||||
u32 taskSize0; /* task size control 0. */
|
||||
u32 taskSize1; /* task size control 1. */
|
||||
u32 dma_rsvd1; /* reserved */
|
||||
u32 dma_rsvd2; /* reserved */
|
||||
u32 debugComp1; /* debug comparator 1 */
|
||||
u32 debugComp2; /* debug comparator 2 */
|
||||
u32 debugControl; /* debug control */
|
||||
u32 debugStatus; /* debug status */
|
||||
u32 ptdDebug; /* priority task decode debug */
|
||||
u32 dma_rsvd3[31]; /* reserved */
|
||||
};
|
||||
typedef volatile struct dmaRegs_s dmaRegs;
|
||||
|
||||
#endif
|
||||
|
||||
/* PTD contrl reg bits */
|
||||
#define PTD_CTL_TSK_PRI 0x8000
|
||||
#define PTD_CTL_COMM_PREFETCH 0x0001
|
||||
|
||||
/* Task Control reg bits and field masks */
|
||||
#define TASK_CTL_EN 0x8000
|
||||
#define TASK_CTL_VALID 0x4000
|
||||
#define TASK_CTL_ALWAYS 0x2000
|
||||
#define TASK_CTL_INIT_MASK 0x1f00
|
||||
#define TASK_CTL_ASTRT 0x0080
|
||||
#define TASK_CTL_HIPRITSKEN 0x0040
|
||||
#define TASK_CTL_HLDINITNUM 0x0020
|
||||
#define TASK_CTL_ASTSKNUM_MASK 0x000f
|
||||
|
||||
/* Priority reg bits and field masks */
|
||||
#define PRIORITY_HLD 0x80
|
||||
#define PRIORITY_PRI_MASK 0x07
|
||||
|
||||
/* Debug Control reg bits and field masks */
|
||||
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
|
||||
#define DBG_CTL_AUTO_ARM 0x00008000
|
||||
#define DBG_CTL_BREAK 0x00004000
|
||||
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
|
||||
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
|
||||
#define DBG_CTL_EXT_BREAK 0x00000004
|
||||
#define DBG_CTL_INT_BREAK 0x00000002
|
||||
|
||||
/*
|
||||
* PTD Debug reg selector addresses
|
||||
* This reg must be written with a value to show the contents of
|
||||
* one of the desired internal register.
|
||||
*/
|
||||
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
|
||||
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
|
||||
have initiators asserted */
|
||||
|
||||
/* General return values */
|
||||
#define MCD_OK 0
|
||||
#define MCD_ERROR -1
|
||||
#define MCD_TABLE_UNALIGNED -2
|
||||
#define MCD_CHANNEL_INVALID -3
|
||||
|
||||
/* MCD_initDma input flags */
|
||||
#define MCD_RELOC_TASKS 0x00000001
|
||||
#define MCD_NO_RELOC_TASKS 0x00000000
|
||||
#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
|
||||
|
||||
/*
|
||||
* MCD_dmaStatus Status Values for each channel:
|
||||
* MCD_NO_DMA - No DMA has been requested since reset
|
||||
* MCD_IDLE - DMA active, but the initiator is currently inactive
|
||||
* MCD_RUNNING - DMA active, and the initiator is currently active
|
||||
* MCD_PAUSED - DMA active but it is currently paused
|
||||
* MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
|
||||
* MCD_DONE - the most recent DMA has completed
|
||||
*/
|
||||
#define MCD_NO_DMA 1
|
||||
#define MCD_IDLE 2
|
||||
#define MCD_RUNNING 3
|
||||
#define MCD_PAUSED 4
|
||||
#define MCD_HALTED 5
|
||||
#define MCD_DONE 6
|
||||
|
||||
/* MCD_startDma parameter defines */
|
||||
|
||||
/* Constants for the funcDesc parameter */
|
||||
/*
|
||||
* MCD_NO_BYTE_SWAP - to disable byte swapping
|
||||
* MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
|
||||
* MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
|
||||
* value being DMAed
|
||||
* MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
|
||||
* each 32-bit data value DMAed
|
||||
* MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
|
||||
* MCD_BIT_REV - reverse the bits of each byte DMAed
|
||||
* MCD_CRC16 - to perform CRC-16 on DMAed data
|
||||
* MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
|
||||
* MCD_CRC32 - to perform CRC-32 on DMAed data
|
||||
* MCD_CSUMINET - to perform internet checksums on DMAed data
|
||||
* MCD_NO_CSUM - to perform no checksumming
|
||||
*/
|
||||
#define MCD_NO_BYTE_SWAP 0x00045670
|
||||
#define MCD_BYTE_REVERSE 0x00076540
|
||||
#define MCD_U16_REVERSE 0x00067450
|
||||
#define MCD_U16_BYTE_REVERSE 0x00054760
|
||||
#define MCD_NO_BIT_REV 0x00000000
|
||||
#define MCD_BIT_REV 0x00088880
|
||||
/* CRCing: */
|
||||
#define MCD_CRC16 0xc0100000
|
||||
#define MCD_CRCCCITT 0xc0200000
|
||||
#define MCD_CRC32 0xc0300000
|
||||
#define MCD_CSUMINET 0xc0400000
|
||||
#define MCD_NO_CSUM 0xa0000000
|
||||
|
||||
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
|
||||
MCD_NO_CSUM)
|
||||
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
|
||||
|
||||
/* Constants for the flags parameter */
|
||||
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
|
||||
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
|
||||
#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
|
||||
#define MCD_TT_FLAGS_MASK 0x000000ff
|
||||
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
|
||||
|
||||
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
|
||||
#define MCD_CHAIN_DMA /* TBD */
|
||||
#define MCD_EU_DMA /* TBD */
|
||||
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
|
||||
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
|
||||
|
||||
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
|
||||
/*
|
||||
* MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
|
||||
* MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
|
||||
* MCD_INTERRUPT - to generate an interrupt after completion of the DMA
|
||||
* MCD_END_FRAME - tell the DMA to end the frame when transferring
|
||||
* last byte of data in buffer
|
||||
* MCD_CRC_RESTART - to empty out the accumulated checksum prior to
|
||||
* performing the DMA
|
||||
*/
|
||||
#define MCD_BUF_READY 0x80000000
|
||||
#define MCD_WRAP 0x20000000
|
||||
#define MCD_INTERRUPT 0x10000000
|
||||
#define MCD_END_FRAME 0x08000000
|
||||
#define MCD_CRC_RESTART 0x40000000
|
||||
|
||||
/* Defines for the FEC buffer descriptor control/status word*/
|
||||
#define MCD_FEC_BUF_READY 0x8000
|
||||
#define MCD_FEC_WRAP 0x2000
|
||||
#define MCD_FEC_INTERRUPT 0x1000
|
||||
#define MCD_FEC_END_FRAME 0x0800
|
||||
|
||||
/* Defines for general intuitiveness */
|
||||
|
||||
#define MCD_TRUE 1
|
||||
#define MCD_FALSE 0
|
||||
|
||||
/* Three different cases for destination and source. */
|
||||
#define MINUS1 -1
|
||||
#define ZERO 0
|
||||
#define PLUS1 1
|
||||
|
||||
#ifndef DEFINESONLY
|
||||
|
||||
/* Task Table Entry struct*/
|
||||
typedef struct {
|
||||
u32 TDTstart; /* task descriptor table start */
|
||||
u32 TDTend; /* task descriptor table end */
|
||||
u32 varTab; /* variable table start */
|
||||
u32 FDTandFlags; /* function descriptor table start & flags */
|
||||
volatile u32 descAddrAndStatus;
|
||||
volatile u32 modifiedVarTab;
|
||||
u32 contextSaveSpace; /* context save space start */
|
||||
u32 literalBases;
|
||||
} TaskTableEntry;
|
||||
|
||||
/* Chained buffer descriptor:
|
||||
* flags - flags describing the DMA
|
||||
* csumResult - checksum performed since last checksum reset
|
||||
* srcAddr - the address to move data from
|
||||
* destAddr - the address to move data to
|
||||
* lastDestAddr - the last address written to
|
||||
* dmaSize - the no of bytes to xfer independent of the xfer sz
|
||||
* next - next buffer descriptor in chain
|
||||
* info - private info about this descriptor; DMA does not affect it
|
||||
*/
|
||||
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
|
||||
struct MCD_bufDesc_struct {
|
||||
u32 flags;
|
||||
u32 csumResult;
|
||||
s8 *srcAddr;
|
||||
s8 *destAddr;
|
||||
s8 *lastDestAddr;
|
||||
u32 dmaSize;
|
||||
MCD_bufDesc *next;
|
||||
u32 info;
|
||||
};
|
||||
|
||||
/* Progress Query struct:
|
||||
* lastSrcAddr - the most-recent or last, post-increment source address
|
||||
* lastDestAddr - the most-recent or last, post-increment destination address
|
||||
* dmaSize - the amount of data transferred for the current buffer
|
||||
* currBufDesc - pointer to the current buffer descriptor being DMAed
|
||||
*/
|
||||
|
||||
typedef volatile struct MCD_XferProg_struct {
|
||||
s8 *lastSrcAddr;
|
||||
s8 *lastDestAddr;
|
||||
u32 dmaSize;
|
||||
MCD_bufDesc *currBufDesc;
|
||||
} MCD_XferProg;
|
||||
|
||||
/* FEC buffer descriptor */
|
||||
typedef volatile struct MCD_bufDescFec_struct {
|
||||
u16 statCtrl;
|
||||
u16 length;
|
||||
u32 dataPointer;
|
||||
} MCD_bufDescFec;
|
||||
|
||||
/*************************************************************************/
|
||||
/* API function Prototypes - see MCD_dmaApi.c for further notes */
|
||||
|
||||
/* MCD_startDma starts a particular kind of DMA:
|
||||
* srcAddr - the channel on which to run the DMA
|
||||
* srcIncr - the address to move data from, or buffer-descriptor address
|
||||
* destAddr - the amount to increment the source address per transfer
|
||||
* destIncr - the address to move data to
|
||||
* dmaSize - the amount to increment the destination address per transfer
|
||||
* xferSize - the number bytes in of each data movement (1, 2, or 4)
|
||||
* initiator - what device initiates the DMA
|
||||
* priority - priority of the DMA
|
||||
* flags - flags describing the DMA
|
||||
* funcDesc - description of byte swapping, bit swapping, and CRC actions
|
||||
*/
|
||||
int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
|
||||
s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
|
||||
int priority, u32 flags, u32 funcDesc);
|
||||
|
||||
/*
|
||||
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
|
||||
* registers, relocating and creating the appropriate task structures, and
|
||||
* setting up some global settings
|
||||
*/
|
||||
int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
|
||||
|
||||
/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
|
||||
int MCD_dmaStatus(int channel);
|
||||
|
||||
/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
|
||||
int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
|
||||
|
||||
/*
|
||||
* MCD_killDma() halts the DMA on the requested channel, without any
|
||||
* intention of resuming the DMA.
|
||||
*/
|
||||
int MCD_killDma(int channel);
|
||||
|
||||
/*
|
||||
* MCD_continDma() continues a DMA which as stopped due to encountering an
|
||||
* unready buffer descriptor.
|
||||
*/
|
||||
int MCD_continDma(int channel);
|
||||
|
||||
/*
|
||||
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
|
||||
* running on that channel).
|
||||
*/
|
||||
int MCD_pauseDma(int channel);
|
||||
|
||||
/*
|
||||
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
|
||||
* running on that channel).
|
||||
*/
|
||||
int MCD_resumeDma(int channel);
|
||||
|
||||
/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
|
||||
int MCD_csumQuery(int channel, u32 * csum);
|
||||
|
||||
/*
|
||||
* MCD_getCodeSize provides the packed size required by the microcoded task
|
||||
* and structures.
|
||||
*/
|
||||
int MCD_getCodeSize(void);
|
||||
|
||||
/*
|
||||
* MCD_getVersion provides a pointer to a version string and returns a
|
||||
* version number.
|
||||
*/
|
||||
int MCD_getVersion(char **longVersion);
|
||||
|
||||
/* macro for setting a location in the variable table */
|
||||
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
|
||||
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
|
||||
so I'm avoiding surrounding it with "do {} while(0)" */
|
||||
|
||||
#endif /* DEFINESONLY */
|
||||
|
||||
#endif /* _MCD_API_H */
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
/* This file is autogenerated. Do not change */
|
||||
#define CURRBD 4
|
||||
#define DCOUNT 6
|
||||
#define DESTPTR 5
|
||||
#define SRCPTR 7
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef MCD_TSK_INIT_H
|
||||
#define MCD_TSK_INIT_H 1
|
||||
|
||||
/*
|
||||
* Do not edit!
|
||||
*/
|
||||
|
||||
/* Task 0 */
|
||||
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
|
||||
int xferSize, short xferSizeIncr, int *cSave,
|
||||
volatile TaskTableEntry * taskTable, int channel);
|
||||
|
||||
/* Task 1 */
|
||||
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
|
||||
short destIncr, int dmaSize, short xferSizeIncr,
|
||||
int flags, int *currBD, int *cSave,
|
||||
volatile TaskTableEntry * taskTable, int channel);
|
||||
|
||||
/* Task 2 */
|
||||
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
|
||||
int xferSize, short xferSizeIncr, int *cSave,
|
||||
volatile TaskTableEntry * taskTable, int channel);
|
||||
|
||||
/* Task 3 */
|
||||
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
|
||||
short destIncr, int dmaSize, short xferSizeIncr,
|
||||
int flags, int *currBD, int *cSave,
|
||||
volatile TaskTableEntry * taskTable, int channel);
|
||||
|
||||
/* Task 4 */
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
|
||||
volatile TaskTableEntry * taskTable, int channel);
|
||||
|
||||
/* Task 5 */
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
|
||||
volatile TaskTableEntry * taskTable, int channel);
|
||||
|
||||
#endif /* MCD_TSK_INIT_H */
|
||||
Loading…
Add table
Reference in a new issue