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Merge tag v2023.07-rc4 into next

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Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2023-06-12 14:55:33 -04:00
commit 260d4962e0
839 changed files with 18530 additions and 4448 deletions
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@ -17,66 +17,115 @@
Alexander Graf <agraf@csgraf.de> <agraf@suse.de> Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
Allen Martin <amartin@nvidia.com> Allen Martin <amartin@nvidia.com>
Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com>
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> <amit.kumar-mahapatra@xilinx.com>
Andreas Bießmann <andreas.devel@googlemail.com> Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann <andreas@biessmann.org> Andreas Bießmann <andreas@biessmann.org>
Aneesh V <aneesh@ti.com> Aneesh V <aneesh@ti.com>
Anup Patel <anup@brainfault.org> <anup.patel@wdc.com> Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.com>
Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com>
Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com>
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com> Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com> Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Dirk Behme <dirk.behme@googlemail.com> Dirk Behme <dirk.behme@googlemail.com>
Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com> Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
Fabio Estevam <fabio.estevam@nxp.com> Fabio Estevam <fabio.estevam@nxp.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com> Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de> Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com> <izhar.ameer.shaikh@xilinx.com>
Jagan Teki <402jagan@gmail.com> Jagan Teki <402jagan@gmail.com>
Jagan Teki <jaganna@gmail.com> Jagan Teki <jaganna@gmail.com>
Jagan Teki <jaganna@xilinx.com> Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com> Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net> Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com> Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
Marek Behún <kabel@kernel.org> <marek.behun@nic.cz> Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz> Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz>
Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com> Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
Marek Vasut <marex@denx.de> <marek.vasut@gmail.com> Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
Marek Vasut <marex@denx.de> <marex at denx.de> Marek Vasut <marex@denx.de> <marex at denx.de>
Markus Klotzbuecher <mk@denx.de> Markus Klotzbuecher <mk@denx.de>
Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org> Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com> Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
Michal Simek <michal.simek@xilinx.com> <monstr@monstr.eu> Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
Michal Simek <michal.simek@xilinx.com> <Monstr@seznam.cz> Michal Simek <michal.simek@amd.com> <root@monstr.eu>
Michal Simek <michal.simek@xilinx.com> <root@monstr.eu> Mirza <Taimoor_Mirza@mentor.com>
Mounika Grace Akula <mounika.akula@amd.com> <mounika.grace.akula@xilinx.com>
Mubin Usman Sayyed <mubin.sayyed@amd.com> <mubin.usman.sayyed@xilinx.com>
Nathalie Chan King Choy <nathalie.chan-king-choy@amd.com> <nathalie.chan-king-choy@xilinx.com>
Nathalie Chan King Choy <nathalie.chan-king-choy@amd.com> <nathalie@xilinx.com>
Nava kishore Manne <nava.kishore.manne@amd.com> <nava.manne@xilinx.com>
Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com> Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de> Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
Prabhakar Kushwaha <prabhakar@freescale.com> Prabhakar Kushwaha <prabhakar@freescale.com>
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com>
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com> Rajeshwari Shinde <rajeshwari.s@samsung.com>
Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es> Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
Ravi Patel <ravi.patel@amd.com> <ravi.patel@xilinx.com>
Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com> Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
Rohit Visavalia <rohit.visavalia@amd.com> <rohit.visavalia@xilinx.com>
Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com> Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com>
Saeed Nowshadi <saeed.nowshadi@amd.com> <saeed.nowshadi@xilinx.com>
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> <lakshmi.sai.krishna.potthuri@xilinx.com>
Sai Pavan Boddu <sai.pavan.boddu@amd.com> <sai.pavan.boddu@xilinx.com>
Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com>
Sandeep Paulraj <s-paulraj@ti.com> Sandeep Paulraj <s-paulraj@ti.com>
Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com>
Shaohui Xie <Shaohui.Xie@freescale.com> Shaohui Xie <Shaohui.Xie@freescale.com>
Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com>
Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> <shubhrajyoti.datta@xilinx.com>
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
Stefan Roese <sr@denx.de> <stroese> Stefan Roese <sr@denx.de> <stroese>
Stefano Babic <sbabic@denx.de> Stefano Babic <sbabic@denx.de>
Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
Tom Rini <trini@konsulko.com> <trini@ti.com> Tom Rini <trini@konsulko.com> <trini@ti.com>
Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com>
TsiChung Liew <Tsi-Chung.Liew@freescale.com> TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Wolfgang Denk <wd@denx.de> <wdenk> Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de> Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@pollux.(none)> Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de> Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de>
Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de> Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
Wolfgang Denk <wd@denx.de> <wd@castor.denx.de> Wolfgang Denk <wd@denx.de> <wd@castor.denx.de>
Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de> Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de>
Wolfgang Denk <wd@denx.de> <wd@nyx.(none)> Wolfgang Denk <wd@denx.de> <wd@nyx.(none)>
York Sun <yorksun@freescale.com> Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de>
Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
Wolfgang Denk <wd@denx.de> <wdenk>
York Sun <york.sun@nxp.com> York Sun <york.sun@nxp.com>
York Sun <yorksun@freescale.com>
Łukasz Majewski <l.majewski@samsung.com> Łukasz Majewski <l.majewski@samsung.com>
Lukasz Majewski <lukma@denx.de>
Mirza <Taimoor_Mirza@mentor.com>

8
Kconfig
View file

@ -397,11 +397,19 @@ endif # EXPERT
config PHYS_64BIT config PHYS_64BIT
bool "64bit physical address support" bool "64bit physical address support"
select FDT_64BIT
help help
Say Y here to support 64bit physical memory address. Say Y here to support 64bit physical memory address.
This can be used not only for 64bit SoCs, but also for This can be used not only for 64bit SoCs, but also for
large physical address extension on 32bit SoCs. large physical address extension on 32bit SoCs.
config FDT_64BIT
bool "64bit fdt address support"
help
Say Y here to support 64bit fdt addresses.
This can be used not only for 64bit SoCs, but also
for large address extensions on 32bit SoCs.
config HAS_ROM config HAS_ROM
bool bool
select BINMAN select BINMAN

2
MAINTAINERS
View file

@ -1496,8 +1496,6 @@ F: configs/k2g_hs_evm_defconfig
F: configs/k2l_hs_evm_defconfig F: configs/k2l_hs_evm_defconfig
F: configs/am65x_hs_evm_r5_defconfig F: configs/am65x_hs_evm_r5_defconfig
F: configs/am65x_hs_evm_a53_defconfig F: configs/am65x_hs_evm_a53_defconfig
F: configs/j721e_hs_evm_a72_defconfig
F: configs/j721e_hs_evm_r5_defconfig
TPM DRIVERS TPM DRIVERS
M: Ilias Apalodimas <ilias.apalodimas@linaro.org> M: Ilias Apalodimas <ilias.apalodimas@linaro.org>

4
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2023 VERSION = 2023
PATCHLEVEL = 07 PATCHLEVEL = 07
SUBLEVEL = SUBLEVEL =
EXTRAVERSION = -rc2 EXTRAVERSION = -rc4
NAME = NAME =
# *DOCUMENTATION* # *DOCUMENTATION*
@ -2123,7 +2123,7 @@ tools/version.h: include/version.h
$(Q)mkdir -p $(dir $@) $(Q)mkdir -p $(dir $@)
$(call if_changed,copy) $(call if_changed,copy)
envtools: scripts_basic $(version_h) $(timestamp_h) tools/version.h envtools: u-boot-initial-env scripts_basic $(version_h) $(timestamp_h) tools/version.h
$(Q)$(MAKE) $(build)=tools/env $(Q)$(MAKE) $(build)=tools/env
tools-only: export TOOLS_ONLY=y tools-only: export TOOLS_ONLY=y

2
arch/Kconfig
View file

@ -195,6 +195,7 @@ config SANDBOX
imply PHYLIB imply PHYLIB
imply DM_MDIO imply DM_MDIO
imply DM_MDIO_MUX imply DM_MDIO_MUX
imply ACPI
imply ACPI_PMC imply ACPI_PMC
imply ACPI_PMC_SANDBOX imply ACPI_PMC_SANDBOX
imply CMD_PMC imply CMD_PMC
@ -261,6 +262,7 @@ config X86
imply PCH imply PCH
imply PHYSMEM imply PHYSMEM
imply RTC_MC146818 imply RTC_MC146818
imply ACPI
imply ACPIGEN if !QEMU && !EFI_APP imply ACPIGEN if !QEMU && !EFI_APP
imply SYSINFO if GENERATE_SMBIOS_TABLE imply SYSINFO if GENERATE_SMBIOS_TABLE
imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE

5
arch/arm/cpu/armv7/Kconfig
View file

@ -107,6 +107,11 @@ config ARMV7_LPAE
Say Y here to use the long descriptor page table format. This is Say Y here to use the long descriptor page table format. This is
required if U-Boot runs in HYP mode. required if U-Boot runs in HYP mode.
config ARMV7_SET_CORTEX_SMPEN
bool
help
Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
config SPL_ARMV7_SET_CORTEX_SMPEN config SPL_ARMV7_SET_CORTEX_SMPEN
bool bool
help help

6
arch/arm/dts/Makefile
View file

@ -123,6 +123,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \ rk3328-evb.dtb \
rk3328-nanopi-r2c.dtb \
rk3328-nanopi-r2s.dtb \ rk3328-nanopi-r2s.dtb \
rk3328-roc-cc.dtb \ rk3328-roc-cc.dtb \
rk3328-rock64.dtb \ rk3328-rock64.dtb \
@ -157,16 +158,17 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-haikou.dtb \ rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \ rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \ rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-4c-plus.dtb \
rk3399-rock-pi-4a.dtb \ rk3399-rock-pi-4a.dtb \
rk3399-rock-pi-4b.dtb \
rk3399-rock-pi-4c.dtb \ rk3399-rock-pi-4c.dtb \
rk3399-rock960.dtb \ rk3399-rock960.dtb \
rk3399-rockpro64.dtb \ rk3399-rockpro64.dtb \
rk3399pro-rock-pi-n10.dtb rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-evb.dtb \ rk3566-anbernic-rgxx3.dtb \
rk3566-radxa-cm3-io.dtb \ rk3566-radxa-cm3-io.dtb \
rk3568-evb.dtb \
rk3568-rock-3a.dtb rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \ dtb-$(CONFIG_ROCKCHIP_RK3588) += \

6
arch/arm/dts/axp22x.dtsi
View file

@ -67,6 +67,12 @@
status = "disabled"; status = "disabled";
}; };
axp_gpio: gpio {
compatible = "x-powers,axp221-gpio";
gpio-controller;
#gpio-cells = <2>;
};
regulators { regulators {
/* Default work frequency for buck regulators */ /* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>; x-powers,dcdc-freq = <3000>;

7
arch/arm/dts/axp809.dtsi
View file

@ -50,4 +50,11 @@
compatible = "x-powers,axp809"; compatible = "x-powers,axp809";
interrupt-controller; interrupt-controller;
#interrupt-cells = <1>; #interrupt-cells = <1>;
axp_gpio: gpio {
compatible = "x-powers,axp809-gpio",
"x-powers,axp221-gpio";
gpio-controller;
#gpio-cells = <2>;
};
}; };

14
arch/arm/dts/axp81x.dtsi
View file

@ -62,16 +62,6 @@
compatible = "x-powers,axp813-gpio"; compatible = "x-powers,axp813-gpio";
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
}; };
battery_power_supply: battery-power { battery_power_supply: battery-power {
@ -144,15 +134,11 @@
}; };
reg_ldo_io0: ldo-io0 { reg_ldo_io0: ldo-io0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_ldo>;
/* Disable by default to avoid conflicts with GPIO */ /* Disable by default to avoid conflicts with GPIO */
status = "disabled"; status = "disabled";
}; };
reg_ldo_io1: ldo-io1 { reg_ldo_io1: ldo-io1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_ldo>;
/* Disable by default to avoid conflicts with GPIO */ /* Disable by default to avoid conflicts with GPIO */
status = "disabled"; status = "disabled";
}; };

51
arch/arm/dts/imx7d-sdb-u-boot.dtsi
View file

@ -5,3 +5,54 @@
&usbotg1 { &usbotg1 {
dr_mode = "peripheral"; dr_mode = "peripheral";
}; };
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
};
&pinctrl_usdhc1 {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
&iomuxc {
pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
>;
};
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
};

29
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
View file

@ -10,25 +10,6 @@
bootph-pre-ram; bootph-pre-ram;
}; };
aliases {
usbgadget0 = &usbg1;
usbgadget1 = &usbg2;
};
usbg1: usbg1 {
compatible = "fsl,imx27-usb-gadget";
dr_mode = "peripheral";
chipidea,usb = <&usbotg1>;
status = "okay";
};
usbg2: usbg2 {
compatible = "fsl,imx27-usb-gadget";
dr_mode = "peripheral";
chipidea,usb = <&usbotg2>;
status = "okay";
};
firmware { firmware {
optee { optee {
compatible = "linaro,optee-tz"; compatible = "linaro,optee-tz";
@ -141,16 +122,6 @@
reset-deassert-us = <100000>; reset-deassert-us = <100000>;
}; };
&usbotg1 {
status = "okay";
extcon = <&ptn5110>;
};
&usbotg2 {
status = "okay";
extcon = <&ptn5110_2>;
};
&s4muap { &s4muap {
bootph-pre-ram; bootph-pre-ram;
status = "okay"; status = "okay";

391
arch/arm/dts/imx93-11x11-evk.dts
View file

@ -1,36 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* /*
* Copyright 2021 NXP * Copyright 2022 NXP
*/ */
/dts-v1/; /dts-v1/;
#include "imx93.dtsi" #include "imx93.dtsi"
/{ / {
model = "NXP i.MX93 11X11 EVK board";
compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
chosen { chosen {
stdout-path = &lpuart1; stdout-path = &lpuart1;
}; };
reserved-memory { reg_vref_1v8: regulator-adc-vref {
#address-cells = <2>;
#size-cells = <2>;
ranges;
audio: audio@a4120000 {
compatible = "shared-dma-pool";
reg = <0 0xa4120000 0 0x100000>;
no-map;
};
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "can2-stby"; regulator-name = "vref_1v8";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <1800000>;
gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
enable-active-low;
}; };
reg_usdhc2_vmmc: regulator-usdhc2 { reg_usdhc2_vmmc: regulator-usdhc2 {
@ -43,81 +32,57 @@
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
}; };
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
}; };
&lpi2c1 { &adc1 {
#address-cells = <1>; vref-supply = <&reg_vref_1v8>;
#size-cells = <0>; status = "okay";
clock-frequency = <400000>; };
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c1>; &mu1 {
pinctrl-1 = <&pinctrl_lpi2c1>; status = "okay";
};
&mu2 {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay"; status = "okay";
ptn5110: tcpc@50 { mdio {
compatible = "nxp,ptn5110"; compatible = "snps,dwmac-mdio";
reg = <0x50>; #address-cells = <1>;
interrupt-parent = <&pcal6524>; #size-cells = <0>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>; clock-frequency = <5000000>;
status = "okay";
port { ethphy1: ethernet-phy@1 {
typec1_dr_sw: endpoint { reg = <1>;
remote-endpoint = <&usb1_drd_sw>; eee-broken-1000t;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
}; };
}; };
};
ptn5110_2: tcpc@51 { &fec {
compatible = "nxp,ptn5110"; pinctrl-names = "default";
reg = <0x51>; pinctrl-0 = <&pinctrl_fec>;
interrupt-parent = <&pcal6524>; phy-mode = "rgmii-id";
interrupts = <9 IRQ_TYPE_EDGE_FALLING>; phy-handle = <&ethphy2>;
status = "okay"; fsl,magic-packet;
status = "okay";
port { mdio {
typec2_dr_sw: endpoint { #address-cells = <1>;
remote-endpoint = <&usb2_drd_sw>; #size-cells = <0>;
}; clock-frequency = <5000000>;
};
typec2_con: connector { ethphy2: ethernet-phy@2 {
compatible = "usb-c-connector"; reg = <2>;
label = "USB-C"; eee-broken-1000t;
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
}; };
}; };
}; };
@ -134,15 +99,14 @@
pmic@25 { pmic@25 {
compatible = "nxp,pca9451a"; compatible = "nxp,pca9451a";
reg = <0x25>; reg = <0x25>;
pinctrl-names = "default";
interrupt-parent = <&pcal6524>; interrupt-parent = <&pcal6524>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
regulators { regulators {
buck1: BUCK1 { buck1: BUCK1 {
regulator-name = "BUCK1"; regulator-name = "BUCK1";
regulator-min-microvolt = <600000>; regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2187500>; regulator-max-microvolt = <2237500>;
regulator-boot-on; regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-ramp-delay = <3125>; regulator-ramp-delay = <3125>;
@ -189,22 +153,6 @@
regulator-always-on; regulator-always-on;
}; };
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 { ldo4: LDO4 {
regulator-name = "LDO4"; regulator-name = "LDO4";
regulator-min-microvolt = <800000>; regulator-min-microvolt = <800000>;
@ -250,48 +198,6 @@
status = "okay"; status = "okay";
}; };
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 { &usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-0 = <&pinctrl_usdhc1>;
@ -315,116 +221,17 @@
no-mmc; no-mmc;
}; };
&usdhc3 {
status = "disabled";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
eee-broken-1000t;
rtl821x,aldps-disable;
rtl821x,clkout-disable;
};
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
rtl821x,aldps-disable;
rtl821x,clkout-disable;
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi>;
status = "disabled";
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&iomuxc { &iomuxc {
pinctrl-names = "default"; pinctrl_lpi2c2: lpi2c2grp {
status = "okay";
pinctrl_flexcan2: flexcan2grp {
fsl,pins = < fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>; >;
}; };
pinctrl_flexspi: flexspigrp { pinctrl_pcal6524: pcal6524grp {
fsl,pins = < fsl,pins = <
MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42
MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42
MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42
MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42
MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42
MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42
MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42
MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42
MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42
MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42
MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>; >;
}; };
@ -447,23 +254,22 @@
>; >;
}; };
pinctrl_lpi2c1: lpi2c1grp { pinctrl_fec: fecgrp {
fsl,pins = < fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
>; MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
}; MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
pinctrl_lpi2c2: lpi2c2grp { MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
fsl,pins = < MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
>; MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
}; MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
pinctrl_pcal6524: pcal6524grp { MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
fsl,pins = < MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>; >;
}; };
@ -474,54 +280,43 @@
>; >;
}; };
pinctrl_uart2: uart2grp {
fsl,pins = <
MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp { pinctrl_usdhc1: usdhc1grp {
fsl,pins = < fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>; >;
}; };
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = < fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>; >;
}; };
pinctrl_usdhc2_gpio: usdhc2gpiogrp { pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = < fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>; >;
}; };
pinctrl_usdhc2: usdhc2grp { pinctrl_usdhc2: usdhc2grp {
fsl,pins = < fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>; >;
}; };
}; };
&wdog3 {
status = "okay";
};

194
arch/arm/dts/imx93-pinfunc.h
View file

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/* /*
* Copyright 2022 NXP * Copyright 2022 NXP
*/ */
@ -10,57 +10,57 @@
* The pin function ID is a tuple of * The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val> * <mux_reg conf_reg input_reg mux_mode input_val>
*/ */
#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03E0 0x0 0x0 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x03CC 0x5 0x0 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0438 0x6 0x0 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x03D0 0x5 0x0 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0
#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x0434 0x6 0x0 #define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0
#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0 #define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0
#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03EC 0x1 0x0 #define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0
#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x043C 0x5 0x1 #define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1
#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03F4 0x6 0x0 #define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0
#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 #define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0
#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E8 0x1 0x0 #define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0
#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0438 0x5 0x1 #define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1
#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03F0 0x6 0x0 #define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0
#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 #define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0
#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0
#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1 #define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1
#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03FC 0x6 0x0 #define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0
#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 #define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0
#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0
#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F8 0x6 0x0 #define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0
#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 #define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0
#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0
@ -68,23 +68,23 @@
#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03FC 0x6 0x1 #define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1
#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 #define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0
#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0440 0x2 0x0 #define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0
#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F8 0x6 0x1 #define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1
#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 #define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0
#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x0444 0x2 0x0 #define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0
#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x0404 0x6 0x0 #define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0
#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 #define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0
#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0
@ -92,7 +92,7 @@
#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x0400 0x6 0x0 #define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0
#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 #define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0
#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0
@ -100,7 +100,7 @@
#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x0404 0x6 0x1 #define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1
#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 #define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0
#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0
@ -108,7 +108,7 @@
#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x0400 0x6 0x1 #define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1
#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 #define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0
#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0
@ -116,7 +116,7 @@
#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x040C 0x6 0x0 #define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0
#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 #define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0
#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0
@ -124,47 +124,47 @@
#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0408 0x6 0x0 #define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0
#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 #define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0
#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0448 0x2 0x0 #define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0
#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x040C 0x6 0x1 #define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1
#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0458 0x7 0x0 #define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0
#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x044C 0x2 0x0 #define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0
#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0408 0x6 0x1 #define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1
#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 #define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0
#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x0424 0x1 0x0 #define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0
#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0430 0x6 0x0 #define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0
#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 #define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0
#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0420 0x1 0x0 #define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0
#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x042C 0x6 0x0 #define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0
#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 #define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0
#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0448 0x2 0x1 #define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1
#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x041C 0x4 0x0 #define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0
#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0428 0x6 0x0 #define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0
#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 #define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0
#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0
@ -175,7 +175,7 @@
#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 #define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0
#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x0454 0x1 0x0 #define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0
#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0
@ -183,8 +183,8 @@
#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 #define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0
#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0458 0x1 0x1 #define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1
#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x044C 0x2 0x1 #define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1
#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0
@ -192,7 +192,7 @@
#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0
#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 #define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0
#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0440 0x2 0x1 #define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1
#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0
@ -205,58 +205,58 @@
#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x0454 0x7 0x1 #define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1
#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0460 0x1 0x0 #define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0
#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x045C 0x2 0x0 #define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0
#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03F4 0x6 0x1 #define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1
#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 #define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0
#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x0464 0x1 0x0 #define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0
#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03F0 0x6 0x1 #define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1
#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 #define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0
#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0468 0x1 0x0 #define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0
#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 #define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0
#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 #define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0
#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x046C 0x1 0x0 #define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0
#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 #define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0
#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03DC 0x5 0x1 #define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1
#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 #define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0
#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0470 0x1 0x0 #define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0
#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x0444 0x2 0x1 #define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1
#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03E0 0x5 0x1 #define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1
#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0
#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x0474 0x1 0x0 #define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0
#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 #define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1
#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 #define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0
#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 #define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0
#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03E4 0x5 0x1 #define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1
#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 #define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0
#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 #define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0
#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03EC 0x1 0x1 #define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1
#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0
#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 #define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0
#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E8 0x1 0x1 #define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1
#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 #define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0
#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 #define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0
@ -266,20 +266,19 @@
#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 #define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1
#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 #define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0
#define MX93_PAD_CCM_CLKO3__GPIO3_IO28 0x0090 0x0240 0x03CC 0x5 0x1 #define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0
#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 #define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0
#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 #define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0
#define MX93_PAD_CCM_CLKO4__GPIO3_IO29 0x0094 0x0244 0x03D0 0x5 0x1 #define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0
#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 #define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0
#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 #define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0
#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03D4 0x2 0x0 #define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0
#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 #define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0
#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 #define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0
#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 #define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0
#define MX93_PAD_ENET1_MDC__LPUART5_RTS_B 0x0098 0x0248 0x0000 0x6 0x0
#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 #define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0
#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D8 0x2 0x0 #define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0
#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 #define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0
#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0
@ -302,7 +301,7 @@
#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 #define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 #define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0
#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x0424 0x1 0x1 #define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1
#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0
#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 #define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0
@ -323,21 +322,21 @@
#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 #define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0420 0x1 0x1 #define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1
#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 #define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x041C 0x1 0x1 #define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1
#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0410 0x3 0x0 #define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0
#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 #define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x0414 0x3 0x0 #define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0
#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0
#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 #define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0
#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 #define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0
#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0418 0x3 0x0 #define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0
#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 #define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0
#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 #define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0
#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 #define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0
@ -365,7 +364,7 @@
#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 #define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 #define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0
#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 #define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0
#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0430 0x1 0x1 #define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1
#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 #define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0
#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 #define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0
#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 #define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0
@ -390,24 +389,24 @@
#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 #define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x042C 0x1 0x1 #define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1
#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 #define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x045C 0x1 0x1 #define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1
#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 #define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0428 0x1 0x1 #define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1
#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 #define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0
#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 #define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0
#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0
#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 #define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0
#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 #define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0
#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x045C 0x2 0x2 #define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2
#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 #define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0
#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 #define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0
#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 #define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0
@ -457,43 +456,42 @@
#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 #define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0
#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 #define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0
#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 #define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0
#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0418 0x2 0x1 #define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1
#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 #define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0
#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 #define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0
#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 #define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0
#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0460 0x0 0x1 #define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1
#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 #define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0
#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 #define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1
#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 #define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0
#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x0464 0x0 0x1 #define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1
#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 #define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0
#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 #define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0
#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 #define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0468 0x0 0x1 #define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1
#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 #define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1
#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 #define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x046C 0x0 0x1 #define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1
#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 #define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1
#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 #define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0470 0x0 0x1 #define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1
#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 #define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1
#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 #define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0
#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x0474 0x0 0x1 #define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1
#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 #define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0
#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 #define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1
#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 #define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0
#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 #define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0
#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 #define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0
#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03D4 0x2 0x1 #define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1
#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 #define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1
#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 #define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0
#define MX93_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0150 0x0300 0x0000 0x6 0x0
#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 #define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0
#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 #define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0
#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D8 0x2 0x1 #define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1
#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 #define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1
#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 #define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0
#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 #define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0
@ -523,34 +521,34 @@
#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 #define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0
#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 #define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0
#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 #define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0
#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0410 0x1 0x1 #define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1
#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 #define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0
#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 #define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1
#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 #define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0
#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 #define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0
#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 #define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0
#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x0414 0x1 0x1 #define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1
#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 #define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1
#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 #define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0
#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 #define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0
#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x0 0x0 #define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0
#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 #define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0
#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 #define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0
#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 #define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0
#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 #define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0
#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x0 0x0 #define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0
#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 #define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0
#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 #define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0
#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 #define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0
#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 #define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0
#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x0 0x0 #define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0
#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 #define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0
#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 #define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0
#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 #define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0
#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 #define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0
#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 #define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0
#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 #define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0
#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x0 0x0 #define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0
#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 #define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0
#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 #define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0
#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 #define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0
@ -569,7 +567,7 @@
#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 #define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0
#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 #define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0
#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 #define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0
#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0450 0x4 0x0 #define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0
#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 #define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0
#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 #define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0
#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 #define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0
@ -581,14 +579,14 @@
#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 #define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0
#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 #define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0
#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 #define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0
#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0440 0x0 0x2 #define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2
#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 #define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0
#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 #define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0
#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 #define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0
#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 #define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0
#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 #define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0
#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 #define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0
#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x0444 0x0 0x2 #define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2
#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 #define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0
#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 #define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0
#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 #define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0
@ -614,7 +612,7 @@
#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 #define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0
#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 #define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0
#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 #define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0
#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0450 0x1 0x1 #define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1
#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 #define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0
#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 #define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0
#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 #define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0

618
arch/arm/dts/imx93.dtsi
View file

@ -1,15 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* /*
* Copyright 2021 NXP * Copyright 2022 NXP
*/ */
#include <dt-bindings/clock/imx93-clock.h> #include <dt-bindings/clock/imx93-clock.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/fsl,imx93-power.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/imx93-power.h>
#include <dt-bindings/usb/pd.h>
#include "imx93-pinfunc.h" #include "imx93-pinfunc.h"
@ -23,11 +22,17 @@
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
gpio3 = &gpio4; gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1; mmc0 = &usdhc1;
mmc1 = &usdhc2; mmc1 = &usdhc2;
mmc2 = &usdhc3; mmc2 = &usdhc3;
ethernet0 = &fec;
ethernet1 = &eqos;
serial0 = &lpuart1; serial0 = &lpuart1;
serial1 = &lpuart2; serial1 = &lpuart2;
serial2 = &lpuart3; serial2 = &lpuart3;
@ -36,14 +41,6 @@
serial5 = &lpuart6; serial5 = &lpuart6;
serial6 = &lpuart7; serial6 = &lpuart7;
serial7 = &lpuart8; serial7 = &lpuart8;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
usb0 = &usbotg1;
usb1 = &usbotg2;
}; };
cpus { cpus {
@ -89,6 +86,11 @@
clock-output-names = "clk_ext1"; clock-output-names = "clk_ext1";
}; };
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci { psci {
compatible = "arm,psci-1.0"; compatible = "arm,psci-1.0";
method = "smc"; method = "smc";
@ -115,6 +117,38 @@
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
}; };
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
soc@0 { soc@0 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
@ -129,46 +163,53 @@
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
anomix_ns_gpr: syscon@44210000 {
compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
reg = <0x44210000 0x1000>;
};
mu1: mailbox@44230000 { mu1: mailbox@44230000 {
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
reg = <0x44230000 0x10000>; reg = <0x44230000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_MU1_B_GATE>;
#mbox-cells = <2>; #mbox-cells = <2>;
status = "disabled"; status = "disabled";
}; };
anomix_ns_gpr: blk-ctrl-anomix@42420000 {
compatible = "syscon";
reg = <0x44210000 0x1000>;
};
system_counter: timer@44290000 { system_counter: timer@44290000 {
compatible = "nxp,sysctr-timer"; compatible = "nxp,sysctr-timer";
reg = <0x44290000 0x30000>; reg = <0x44290000 0x30000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>; clocks = <&osc_24m>;
clock-names = "per"; clock-names = "per";
nxp,no-divider;
}; };
i3c1: i3c-master@44330000 { tpm1: pwm@44310000 {
#address-cells = <3>; compatible = "fsl,imx7ulp-pwm";
#size-cells = <0>; reg = <0x44310000 0x1000>;
compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; clocks = <&clk IMX93_CLK_TPM1_GATE>;
reg = <0x44330000 0x10000>; #pwm-cells = <3>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";
clocks = <&clk IMX93_CLK_I3C1_GATE>, };
<&clk IMX93_CLK_I3C1_GATE>,
<&clk IMX93_CLK_DUMMY>; tpm2: pwm@44320000 {
clock-names = "pclk", "fast_clk", "slow_clk"; compatible = "fsl,imx7ulp-pwm";
reg = <0x44320000 0x10000>;
clocks = <&clk IMX93_CLK_TPM2_GATE>;
#pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
lpi2c1: i2c@44340000 { lpi2c1: i2c@44340000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x44340000 0x10000>; reg = <0x44340000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C1_GATE>, clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
<&clk IMX93_CLK_LPI2C1_GATE>; <&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -176,9 +217,11 @@
lpi2c2: i2c@44350000 { lpi2c2: i2c@44350000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x44350000 0x10000>; reg = <0x44350000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C2_GATE>, clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
<&clk IMX93_CLK_LPI2C2_GATE>; <&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -190,7 +233,7 @@
reg = <0x44360000 0x10000>; reg = <0x44360000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI1_GATE>, clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
<&clk IMX93_CLK_LPSPI1_GATE>; <&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -202,14 +245,13 @@
reg = <0x44370000 0x10000>; reg = <0x44370000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI2_GATE>, clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
<&clk IMX93_CLK_LPSPI2_GATE>; <&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
lpuart1: serial@44380000 { lpuart1: serial@44380000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x44380000 0x1000>; reg = <0x44380000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART1_GATE>; clocks = <&clk IMX93_CLK_LPUART1_GATE>;
@ -218,8 +260,7 @@
}; };
lpuart2: serial@44390000 { lpuart2: serial@44390000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x44390000 0x1000>; reg = <0x44390000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART2_GATE>; clocks = <&clk IMX93_CLK_LPUART2_GATE>;
@ -227,9 +268,40 @@
status = "disabled"; status = "disabled";
}; };
flexcan1: can@443a0000 {
compatible = "fsl,imx93-flexcan";
reg = <0x443a0000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_BUS_AON>,
<&clk IMX93_CLK_CAN1_GATE>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX93_CLK_CAN1>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
iomuxc: pinctrl@443c0000 { iomuxc: pinctrl@443c0000 {
compatible = "fsl,imx93-iomuxc"; compatible = "fsl,imx93-iomuxc";
reg = <0x443c0000 0x10000>; reg = <0x443c0000 0x10000>;
status = "okay";
};
bbnsm: bbnsm@44440000 {
compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
reg = <0x44440000 0x10000>;
bbnsm_rtc: rtc {
compatible = "nxp,imx93-bbnsm-rtc";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
bbnsm_pwrkey: pwrkey {
compatible = "nxp,imx93-bbnsm-pwrkey";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
linux,code = <KEY_POWER>;
};
}; };
clk: clock-controller@44450000 { clk: clock-controller@44450000 {
@ -238,25 +310,63 @@
#clock-cells = <1>; #clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
clock-names = "osc_32k", "osc_24m", "clk_ext1"; clock-names = "osc_32k", "osc_24m", "clk_ext1";
assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <393216000>;
status = "okay"; status = "okay";
}; };
src: system-controller@44460000 {
compatible = "fsl,imx93-src", "syscon";
reg = <0x44460000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mediamix: power-domain@44462400 {
compatible = "fsl,imx93-src-slice";
reg = <0x44462400 0x400>, <0x44465800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_MEDIA_APB>;
};
mlmix: power-domain@44461800 {
compatible = "fsl,imx93-src-slice";
reg = <0x44461800 0x400>, <0x44464800 0x400>;
#power-domain-cells = <0>;
clocks = <&clk IMX93_CLK_ML_APB>,
<&clk IMX93_CLK_ML>;
};
};
anatop: anatop@44480000 { anatop: anatop@44480000 {
compatible = "fsl,imx93-anatop", "syscon"; compatible = "fsl,imx93-anatop", "syscon";
reg = <0x44480000 0x10000>; reg = <0x44480000 0x10000>;
}; };
tmu: tmu@44482000 {
compatible = "fsl,imx93-tmu";
reg = <0x44482000 0x1000>;
clocks = <&clk IMX93_CLK_TMC_GATE>;
little-endian;
fsl,tmu-calibration = <0x0000000e 0x800000da
0x00000029 0x800000e9
0x00000056 0x80000102
0x000000a2 0x8000012a
0x00000116 0x80000166
0x00000195 0x800001a7
0x000001b2 0x800001b6>;
#thermal-sensor-cells = <1>;
};
adc1: adc@44530000 { adc1: adc@44530000 {
compatible = "nxp,imx93-adc"; compatible = "nxp,imx93-adc";
reg = <0x44530000 0x10000>; reg = <0x44530000 0x10000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_ADC1_GATE>; clocks = <&clk IMX93_CLK_ADC1_GATE>;
clock-names = "ipg"; clock-names = "ipg";
#io-channel-cells = <1>;
status = "disabled"; status = "disabled";
}; };
}; };
@ -268,8 +378,8 @@
#size-cells = <1>; #size-cells = <1>;
ranges; ranges;
wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 { wakeupmix_gpr: syscon@42420000 {
compatible = "syscon"; compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
reg = <0x42420000 0x1000>; reg = <0x42420000 0x1000>;
}; };
@ -277,6 +387,7 @@
compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
reg = <0x42440000 0x10000>; reg = <0x42440000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_MU2_B_GATE>;
#mbox-cells = <2>; #mbox-cells = <2>;
status = "disabled"; status = "disabled";
}; };
@ -287,39 +398,48 @@
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WDOG3_GATE>; clocks = <&clk IMX93_CLK_WDOG3_GATE>;
timeout-sec = <40>; timeout-sec = <40>;
};
tpm3: pwm@424e0000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x424e0000 0x1000>;
clocks = <&clk IMX93_CLK_TPM3_GATE>;
#pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
tpm4: pwm@424f0000 { tpm4: pwm@424f0000 {
compatible = "fsl,imx7ulp-pwm"; compatible = "fsl,imx7ulp-pwm";
reg = <0x424f0000 0x1000>; reg = <0x424f0000 0x10000>;
clocks = <&clk IMX93_CLK_TPM4_GATE>; clocks = <&clk IMX93_CLK_TPM4_GATE>;
assigned-clocks = <&clk IMX93_CLK_TPM4>;
assigned-clock-parents = <&clk IMX93_CLK_24M>;
assigned-clock-rates = <24000000>;
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
i3c2: i3c-master@42520000 { tpm5: pwm@42500000 {
#address-cells = <3>; compatible = "fsl,imx7ulp-pwm";
#size-cells = <0>; reg = <0x42500000 0x10000>;
compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master"; clocks = <&clk IMX93_CLK_TPM5_GATE>;
reg = <0x42520000 0x10000>; #pwm-cells = <3>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";
clocks = <&clk IMX93_CLK_I3C2_GATE>, };
<&clk IMX93_CLK_I3C2_GATE>,
<&clk IMX93_CLK_DUMMY>; tpm6: pwm@42510000 {
clock-names = "pclk", "fast_clk", "slow_clk"; compatible = "fsl,imx7ulp-pwm";
reg = <0x42510000 0x10000>;
clocks = <&clk IMX93_CLK_TPM6_GATE>;
#pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
lpi2c3: i2c@42530000 { lpi2c3: i2c@42530000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x42530000 0x10000>; reg = <0x42530000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C3_GATE>, clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
<&clk IMX93_CLK_LPI2C3_GATE>; <&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -327,9 +447,11 @@
lpi2c4: i2c@42540000 { lpi2c4: i2c@42540000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x42540000 0x10000>; reg = <0x42540000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C4_GATE>, clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
<&clk IMX93_CLK_LPI2C4_GATE>; <&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -341,7 +463,7 @@
reg = <0x42550000 0x10000>; reg = <0x42550000 0x10000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI3_GATE>, clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
<&clk IMX93_CLK_LPSPI3_GATE>; <&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -353,14 +475,13 @@
reg = <0x42560000 0x10000>; reg = <0x42560000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI4_GATE>, clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
<&clk IMX93_CLK_LPSPI4_GATE>; <&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
lpuart3: serial@42570000 { lpuart3: serial@42570000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x42570000 0x1000>; reg = <0x42570000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART3_GATE>; clocks = <&clk IMX93_CLK_LPUART3_GATE>;
@ -369,8 +490,7 @@
}; };
lpuart4: serial@42580000 { lpuart4: serial@42580000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x42580000 0x1000>; reg = <0x42580000 0x1000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART4_GATE>; clocks = <&clk IMX93_CLK_LPUART4_GATE>;
@ -379,8 +499,7 @@
}; };
lpuart5: serial@42590000 { lpuart5: serial@42590000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x42590000 0x1000>; reg = <0x42590000 0x1000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART5_GATE>; clocks = <&clk IMX93_CLK_LPUART5_GATE>;
@ -389,8 +508,7 @@
}; };
lpuart6: serial@425a0000 { lpuart6: serial@425a0000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x425a0000 0x1000>; reg = <0x425a0000 0x1000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART6_GATE>; clocks = <&clk IMX93_CLK_LPUART6_GATE>;
@ -398,22 +516,37 @@
status = "disabled"; status = "disabled";
}; };
flexspi: spi@425e0000 { flexcan2: can@425b0000 {
#address-cells = <1>; compatible = "fsl,imx93-flexcan";
#size-cells = <0>; reg = <0x425b0000 0x10000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_CAN2_GATE>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX93_CLK_CAN2>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
flexspi1: spi@425e0000 {
compatible = "nxp,imx8mm-fspi"; compatible = "nxp,imx8mm-fspi";
reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap"; reg-names = "fspi_base", "fspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_DUMMY>, clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
<&clk IMX93_CLK_DUMMY>; <&clk IMX93_CLK_FLEXSPI1_GATE>;
clock-names = "fspi", "fspi_en"; clock-names = "fspi_en", "fspi";
assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
status = "disabled"; status = "disabled";
}; };
lpuart7: serial@42690000 { lpuart7: serial@42690000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x42690000 0x1000>; reg = <0x42690000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART7_GATE>; clocks = <&clk IMX93_CLK_LPUART7_GATE>;
@ -422,8 +555,7 @@
}; };
lpuart8: serial@426a0000 { lpuart8: serial@426a0000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
"fsl,imx7ulp-lpuart";
reg = <0x426a0000 0x1000>; reg = <0x426a0000 0x1000>;
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART8_GATE>; clocks = <&clk IMX93_CLK_LPUART8_GATE>;
@ -434,9 +566,11 @@
lpi2c5: i2c@426b0000 { lpi2c5: i2c@426b0000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x426b0000 0x10000>; reg = <0x426b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C5_GATE>, clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
<&clk IMX93_CLK_LPI2C5_GATE>; <&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
@ -444,12 +578,87 @@
lpi2c6: i2c@426c0000 { lpi2c6: i2c@426c0000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x426c0000 0x10000>; reg = <0x426c0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C6_GATE>, clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
<&clk IMX93_CLK_LPI2C6_GATE>; <&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg"; clock-names = "per", "ipg";
status = "disabled"; status = "disabled";
}; };
lpi2c7: i2c@426d0000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x426d0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpi2c8: i2c@426e0000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x426e0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi5: spi@426f0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x426f0000 0x10000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi6: spi@42700000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42700000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi7: spi@42710000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42710000 0x10000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
lpspi8: spi@42720000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
reg = <0x42720000 0x10000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
status = "disabled";
};
}; };
aips3: bus@42800000 { aips3: bus@42800000 {
@ -463,8 +672,8 @@
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
reg = <0x42850000 0x10000>; reg = <0x42850000 0x10000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_DUMMY>, clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_USDHC1_GATE>; <&clk IMX93_CLK_USDHC1_GATE>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <8>; bus-width = <8>;
@ -477,8 +686,8 @@
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
reg = <0x42860000 0x10000>; reg = <0x42860000 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_DUMMY>, clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_USDHC2_GATE>; <&clk IMX93_CLK_USDHC2_GATE>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
@ -487,15 +696,37 @@
status = "disabled"; status = "disabled";
}; };
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_QOS_GATE>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_ENET_QOS_GATE>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
status = "disabled";
};
fec: ethernet@42890000 { fec: ethernet@42890000 {
compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x42890000 0x10000>; reg = <0x42890000 0x10000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_WAKEUP_AXI>, clocks = <&clk IMX93_CLK_ENET1_GATE>,
<&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_ENET1_GATE>,
<&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>; <&clk IMX93_CLK_ENET_REF_PHY>;
@ -510,29 +741,6 @@
assigned-clock-rates = <100000000>, <250000000>, <50000000>; assigned-clock-rates = <100000000>, <250000000>, <50000000>;
fsl,num-tx-queues = <3>; fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>; fsl,num-rx-queues = <3>;
fsl,wakeup_irq = <2>;
status = "disabled";
};
eqos: ethernet@428a0000 {
compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x428a0000 0x10000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eth_wake_irq", "macirq";
clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>,
<&clk IMX93_CLK_WAKEUP_AXI>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
<&clk IMX93_CLK_ENET>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
clk_csr = <0>;
status = "disabled"; status = "disabled";
}; };
@ -540,8 +748,8 @@
compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
reg = <0x428b0000 0x10000>; reg = <0x428b0000 0x10000>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_DUMMY>, clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_USDHC3_GATE>; <&clk IMX93_CLK_USDHC3_GATE>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
bus-width = <4>; bus-width = <4>;
@ -551,138 +759,90 @@
}; };
}; };
gpio2: gpio@43810000 { gpio2: gpio@43810080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x43810080 0x1000>, <0x43810040 0x40>; reg = <0x43810080 0x1000>, <0x43810040 0x40>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller;
interrupt-controller; #interrupt-cells = <2>;
#interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO2_GATE>,
gpio-ranges = <&iomuxc 0 32 32>; <&clk IMX93_CLK_GPIO2_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 4 30>;
}; };
gpio3: gpio@43820000 { gpio3: gpio@43820080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x43820080 0x1000>, <0x43820040 0x40>; reg = <0x43820080 0x1000>, <0x43820040 0x40>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller;
interrupt-controller; #interrupt-cells = <2>;
#interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO3_GATE>,
gpio-ranges = <&iomuxc 0 64 32>; <&clk IMX93_CLK_GPIO3_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
<&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
}; };
gpio4: gpio@43830000 { gpio4: gpio@43830080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x43830080 0x1000>, <0x43830040 0x40>; reg = <0x43830080 0x1000>, <0x43830040 0x40>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller;
interrupt-controller; #interrupt-cells = <2>;
#interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO4_GATE>,
gpio-ranges = <&iomuxc 0 96 32>; <&clk IMX93_CLK_GPIO4_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
}; };
gpio1: gpio@47400000 { gpio1: gpio@47400080 {
compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
reg = <0x47400080 0x1000>, <0x47400040 0x40>; reg = <0x47400080 0x1000>, <0x47400040 0x40>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller;
interrupt-controller; #interrupt-cells = <2>;
#interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO1_GATE>,
gpio-ranges = <&iomuxc 0 0 32>; <&clk IMX93_CLK_GPIO1_GATE>;
clock-names = "gpio", "port";
gpio-ranges = <&iomuxc 0 92 16>;
}; };
ocotp: efuse@47510000 { s4muap: mailbox@47520000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx93-ocotp", "syscon";
reg = <0x47510000 0x1000>;
status = "disabled";
};
s4muap: s4muap@47520000 {
compatible = "fsl,imx93-mu-s4"; compatible = "fsl,imx93-mu-s4";
reg = <0x47520000 0x10000>; reg = <0x47520000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "txirq", "rxirq"; interrupt-names = "tx", "rx";
#mbox-cells = <2>; #mbox-cells = <2>;
status = "okay";
}; };
sentnl_mu: sentnl-mu { media_blk_ctrl: system-controller@4ac10000 {
#address-cells = <1>; compatible = "fsl,imx93-media-blk-ctrl", "syscon";
#size-cells = <1>; reg = <0x4ac10000 0x10000>;
compatible = "fsl,imx-sentnl"; power-domains = <&mediamix>;
mboxes = <&s4muap 0 0 &s4muap 1 0>; clocks = <&clk IMX93_CLK_MEDIA_APB>,
mbox-names = "tx", "rx"; <&clk IMX93_CLK_MEDIA_AXI>,
fsl,sentnl_mu_id = <2>; <&clk IMX93_CLK_NIC_MEDIA_GATE>,
fsl,sentnl_mu_max_users = <4>; <&clk IMX93_CLK_MEDIA_DISP_PIX>,
status = "okay"; <&clk IMX93_CLK_CAM_PIX>,
dma-ranges = <0x80000000 0x80000000 0x20000000>; <&clk IMX93_CLK_PXP_GATE>,
}; <&clk IMX93_CLK_LCDIF_GATE>,
<&clk IMX93_CLK_ISI_GATE>,
ddr-pmu@4e300e00 { <&clk IMX93_CLK_MIPI_CSI_GATE>,
compatible = "fsl,imx93-ddr-pmu"; <&clk IMX93_CLK_MIPI_DSI_GATE>;
reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */ clock-names = "apb", "axi", "nic", "disp", "cam",
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; "pxp", "lcdif", "isi", "csi", "dsi";
}; #power-domain-cells = <1>;
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
clock-names = "main_clk";
};
usbotg1: usb@4c100000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
reg = <0x4c100000 0x200>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled"; status = "disabled";
}; };
usbmisc1: usbmisc@4c100200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
reg = <0x4c100200 0x200>;
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
clock-names = "main_clk";
};
usbotg2: usb@4c200000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
reg = <0x4c200000 0x200>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
clock-names = "usb2_ctrl_root_clk";
assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
};
usbmisc2: usbmisc@4c200200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
reg = <0x4c200200 0x200>;
};
}; };
}; };

512
arch/arm/dts/r9a06g032-ddr.dtsi Normal file
View file

@ -0,0 +1,512 @@
// SPDX-License-Identifier: GPL-2.0
cadence,ctl-000 = <
DENALI_CTL_00_DATA
DENALI_CTL_01_DATA
DENALI_CTL_02_DATA
DENALI_CTL_03_DATA
DENALI_CTL_04_DATA
DENALI_CTL_05_DATA
DENALI_CTL_06_DATA
DENALI_CTL_07_DATA
DENALI_CTL_08_DATA
DENALI_CTL_09_DATA
DENALI_CTL_10_DATA
DENALI_CTL_11_DATA
DENALI_CTL_12_DATA
DENALI_CTL_13_DATA
DENALI_CTL_14_DATA
DENALI_CTL_15_DATA
DENALI_CTL_16_DATA
DENALI_CTL_17_DATA
DENALI_CTL_18_DATA
DENALI_CTL_19_DATA
DENALI_CTL_20_DATA
DENALI_CTL_21_DATA
DENALI_CTL_22_DATA
DENALI_CTL_23_DATA
DENALI_CTL_24_DATA
DENALI_CTL_25_DATA
DENALI_CTL_26_DATA
DENALI_CTL_27_DATA
DENALI_CTL_28_DATA
DENALI_CTL_29_DATA
DENALI_CTL_30_DATA
DENALI_CTL_31_DATA
DENALI_CTL_32_DATA
DENALI_CTL_33_DATA
DENALI_CTL_34_DATA
DENALI_CTL_35_DATA
DENALI_CTL_36_DATA
DENALI_CTL_37_DATA
DENALI_CTL_38_DATA
DENALI_CTL_39_DATA
DENALI_CTL_40_DATA
DENALI_CTL_41_DATA
DENALI_CTL_42_DATA
DENALI_CTL_43_DATA
DENALI_CTL_44_DATA
DENALI_CTL_45_DATA
DENALI_CTL_46_DATA
DENALI_CTL_47_DATA
DENALI_CTL_48_DATA
DENALI_CTL_49_DATA
DENALI_CTL_50_DATA
DENALI_CTL_51_DATA
DENALI_CTL_52_DATA
DENALI_CTL_53_DATA
DENALI_CTL_54_DATA
DENALI_CTL_55_DATA
DENALI_CTL_56_DATA
DENALI_CTL_57_DATA
DENALI_CTL_58_DATA
DENALI_CTL_59_DATA
DENALI_CTL_60_DATA
DENALI_CTL_61_DATA
DENALI_CTL_62_DATA
DENALI_CTL_63_DATA
DENALI_CTL_64_DATA
DENALI_CTL_65_DATA
DENALI_CTL_66_DATA
DENALI_CTL_67_DATA
DENALI_CTL_68_DATA
DENALI_CTL_69_DATA
DENALI_CTL_70_DATA
DENALI_CTL_71_DATA
DENALI_CTL_72_DATA
DENALI_CTL_73_DATA
DENALI_CTL_74_DATA
DENALI_CTL_75_DATA
DENALI_CTL_76_DATA
DENALI_CTL_77_DATA
DENALI_CTL_78_DATA
DENALI_CTL_79_DATA
DENALI_CTL_80_DATA
DENALI_CTL_81_DATA
DENALI_CTL_82_DATA
DENALI_CTL_83_DATA
DENALI_CTL_84_DATA
DENALI_CTL_85_DATA
DENALI_CTL_86_DATA
DENALI_CTL_87_DATA
DENALI_CTL_88_DATA
DENALI_CTL_89_DATA
DENALI_CTL_90_DATA
DENALI_CTL_91_DATA
DENALI_CTL_92_DATA
>;
cadence,ctl-350 = <
DENALI_CTL_350_DATA
DENALI_CTL_351_DATA
DENALI_CTL_352_DATA
DENALI_CTL_353_DATA
DENALI_CTL_354_DATA
DENALI_CTL_355_DATA
DENALI_CTL_356_DATA
DENALI_CTL_357_DATA
DENALI_CTL_358_DATA
DENALI_CTL_359_DATA
DENALI_CTL_360_DATA
DENALI_CTL_361_DATA
DENALI_CTL_362_DATA
DENALI_CTL_363_DATA
DENALI_CTL_364_DATA
DENALI_CTL_365_DATA
DENALI_CTL_366_DATA
DENALI_CTL_367_DATA
DENALI_CTL_368_DATA
DENALI_CTL_369_DATA
DENALI_CTL_370_DATA
DENALI_CTL_371_DATA
DENALI_CTL_372_DATA
DENALI_CTL_373_DATA
DENALI_CTL_374_DATA
>;
#undef DENALI_CTL_00_DATA
#undef DENALI_CTL_01_DATA
#undef DENALI_CTL_02_DATA
#undef DENALI_CTL_03_DATA
#undef DENALI_CTL_04_DATA
#undef DENALI_CTL_05_DATA
#undef DENALI_CTL_06_DATA
#undef DENALI_CTL_07_DATA
#undef DENALI_CTL_08_DATA
#undef DENALI_CTL_09_DATA
#undef DENALI_CTL_10_DATA
#undef DENALI_CTL_11_DATA
#undef DENALI_CTL_12_DATA
#undef DENALI_CTL_13_DATA
#undef DENALI_CTL_14_DATA
#undef DENALI_CTL_15_DATA
#undef DENALI_CTL_16_DATA
#undef DENALI_CTL_17_DATA
#undef DENALI_CTL_18_DATA
#undef DENALI_CTL_19_DATA
#undef DENALI_CTL_20_DATA
#undef DENALI_CTL_21_DATA
#undef DENALI_CTL_22_DATA
#undef DENALI_CTL_23_DATA
#undef DENALI_CTL_24_DATA
#undef DENALI_CTL_25_DATA
#undef DENALI_CTL_26_DATA
#undef DENALI_CTL_27_DATA
#undef DENALI_CTL_28_DATA
#undef DENALI_CTL_29_DATA
#undef DENALI_CTL_30_DATA
#undef DENALI_CTL_31_DATA
#undef DENALI_CTL_32_DATA
#undef DENALI_CTL_33_DATA
#undef DENALI_CTL_34_DATA
#undef DENALI_CTL_35_DATA
#undef DENALI_CTL_36_DATA
#undef DENALI_CTL_37_DATA
#undef DENALI_CTL_38_DATA
#undef DENALI_CTL_39_DATA
#undef DENALI_CTL_40_DATA
#undef DENALI_CTL_41_DATA
#undef DENALI_CTL_42_DATA
#undef DENALI_CTL_43_DATA
#undef DENALI_CTL_44_DATA
#undef DENALI_CTL_45_DATA
#undef DENALI_CTL_46_DATA
#undef DENALI_CTL_47_DATA
#undef DENALI_CTL_48_DATA
#undef DENALI_CTL_49_DATA
#undef DENALI_CTL_50_DATA
#undef DENALI_CTL_51_DATA
#undef DENALI_CTL_52_DATA
#undef DENALI_CTL_53_DATA
#undef DENALI_CTL_54_DATA
#undef DENALI_CTL_55_DATA
#undef DENALI_CTL_56_DATA
#undef DENALI_CTL_57_DATA
#undef DENALI_CTL_58_DATA
#undef DENALI_CTL_59_DATA
#undef DENALI_CTL_60_DATA
#undef DENALI_CTL_61_DATA
#undef DENALI_CTL_62_DATA
#undef DENALI_CTL_63_DATA
#undef DENALI_CTL_64_DATA
#undef DENALI_CTL_65_DATA
#undef DENALI_CTL_66_DATA
#undef DENALI_CTL_67_DATA
#undef DENALI_CTL_68_DATA
#undef DENALI_CTL_69_DATA
#undef DENALI_CTL_70_DATA
#undef DENALI_CTL_71_DATA
#undef DENALI_CTL_72_DATA
#undef DENALI_CTL_73_DATA
#undef DENALI_CTL_74_DATA
#undef DENALI_CTL_75_DATA
#undef DENALI_CTL_76_DATA
#undef DENALI_CTL_77_DATA
#undef DENALI_CTL_78_DATA
#undef DENALI_CTL_79_DATA
#undef DENALI_CTL_80_DATA
#undef DENALI_CTL_81_DATA
#undef DENALI_CTL_82_DATA
#undef DENALI_CTL_83_DATA
#undef DENALI_CTL_84_DATA
#undef DENALI_CTL_85_DATA
#undef DENALI_CTL_86_DATA
#undef DENALI_CTL_87_DATA
#undef DENALI_CTL_88_DATA
#undef DENALI_CTL_89_DATA
#undef DENALI_CTL_90_DATA
#undef DENALI_CTL_91_DATA
#undef DENALI_CTL_92_DATA
#undef DENALI_CTL_93_DATA
#undef DENALI_CTL_94_DATA
#undef DENALI_CTL_95_DATA
#undef DENALI_CTL_96_DATA
#undef DENALI_CTL_97_DATA
#undef DENALI_CTL_98_DATA
#undef DENALI_CTL_99_DATA
#undef DENALI_CTL_100_DATA
#undef DENALI_CTL_101_DATA
#undef DENALI_CTL_102_DATA
#undef DENALI_CTL_103_DATA
#undef DENALI_CTL_104_DATA
#undef DENALI_CTL_105_DATA
#undef DENALI_CTL_106_DATA
#undef DENALI_CTL_107_DATA
#undef DENALI_CTL_108_DATA
#undef DENALI_CTL_109_DATA
#undef DENALI_CTL_110_DATA
#undef DENALI_CTL_111_DATA
#undef DENALI_CTL_112_DATA
#undef DENALI_CTL_113_DATA
#undef DENALI_CTL_114_DATA
#undef DENALI_CTL_115_DATA
#undef DENALI_CTL_116_DATA
#undef DENALI_CTL_117_DATA
#undef DENALI_CTL_118_DATA
#undef DENALI_CTL_119_DATA
#undef DENALI_CTL_120_DATA
#undef DENALI_CTL_121_DATA
#undef DENALI_CTL_122_DATA
#undef DENALI_CTL_123_DATA
#undef DENALI_CTL_124_DATA
#undef DENALI_CTL_125_DATA
#undef DENALI_CTL_126_DATA
#undef DENALI_CTL_127_DATA
#undef DENALI_CTL_128_DATA
#undef DENALI_CTL_129_DATA
#undef DENALI_CTL_130_DATA
#undef DENALI_CTL_131_DATA
#undef DENALI_CTL_132_DATA
#undef DENALI_CTL_133_DATA
#undef DENALI_CTL_134_DATA
#undef DENALI_CTL_135_DATA
#undef DENALI_CTL_136_DATA
#undef DENALI_CTL_137_DATA
#undef DENALI_CTL_138_DATA
#undef DENALI_CTL_139_DATA
#undef DENALI_CTL_140_DATA
#undef DENALI_CTL_141_DATA
#undef DENALI_CTL_142_DATA
#undef DENALI_CTL_143_DATA
#undef DENALI_CTL_144_DATA
#undef DENALI_CTL_145_DATA
#undef DENALI_CTL_146_DATA
#undef DENALI_CTL_147_DATA
#undef DENALI_CTL_148_DATA
#undef DENALI_CTL_149_DATA
#undef DENALI_CTL_150_DATA
#undef DENALI_CTL_151_DATA
#undef DENALI_CTL_152_DATA
#undef DENALI_CTL_153_DATA
#undef DENALI_CTL_154_DATA
#undef DENALI_CTL_155_DATA
#undef DENALI_CTL_156_DATA
#undef DENALI_CTL_157_DATA
#undef DENALI_CTL_158_DATA
#undef DENALI_CTL_159_DATA
#undef DENALI_CTL_160_DATA
#undef DENALI_CTL_161_DATA
#undef DENALI_CTL_162_DATA
#undef DENALI_CTL_163_DATA
#undef DENALI_CTL_164_DATA
#undef DENALI_CTL_165_DATA
#undef DENALI_CTL_166_DATA
#undef DENALI_CTL_167_DATA
#undef DENALI_CTL_168_DATA
#undef DENALI_CTL_169_DATA
#undef DENALI_CTL_170_DATA
#undef DENALI_CTL_171_DATA
#undef DENALI_CTL_172_DATA
#undef DENALI_CTL_173_DATA
#undef DENALI_CTL_174_DATA
#undef DENALI_CTL_175_DATA
#undef DENALI_CTL_176_DATA
#undef DENALI_CTL_177_DATA
#undef DENALI_CTL_178_DATA
#undef DENALI_CTL_179_DATA
#undef DENALI_CTL_180_DATA
#undef DENALI_CTL_181_DATA
#undef DENALI_CTL_182_DATA
#undef DENALI_CTL_183_DATA
#undef DENALI_CTL_184_DATA
#undef DENALI_CTL_185_DATA
#undef DENALI_CTL_186_DATA
#undef DENALI_CTL_187_DATA
#undef DENALI_CTL_188_DATA
#undef DENALI_CTL_189_DATA
#undef DENALI_CTL_190_DATA
#undef DENALI_CTL_191_DATA
#undef DENALI_CTL_192_DATA
#undef DENALI_CTL_193_DATA
#undef DENALI_CTL_194_DATA
#undef DENALI_CTL_195_DATA
#undef DENALI_CTL_196_DATA
#undef DENALI_CTL_197_DATA
#undef DENALI_CTL_198_DATA
#undef DENALI_CTL_199_DATA
#undef DENALI_CTL_200_DATA
#undef DENALI_CTL_201_DATA
#undef DENALI_CTL_202_DATA
#undef DENALI_CTL_203_DATA
#undef DENALI_CTL_204_DATA
#undef DENALI_CTL_205_DATA
#undef DENALI_CTL_206_DATA
#undef DENALI_CTL_207_DATA
#undef DENALI_CTL_208_DATA
#undef DENALI_CTL_209_DATA
#undef DENALI_CTL_210_DATA
#undef DENALI_CTL_211_DATA
#undef DENALI_CTL_212_DATA
#undef DENALI_CTL_213_DATA
#undef DENALI_CTL_214_DATA
#undef DENALI_CTL_215_DATA
#undef DENALI_CTL_216_DATA
#undef DENALI_CTL_217_DATA
#undef DENALI_CTL_218_DATA
#undef DENALI_CTL_219_DATA
#undef DENALI_CTL_220_DATA
#undef DENALI_CTL_221_DATA
#undef DENALI_CTL_222_DATA
#undef DENALI_CTL_223_DATA
#undef DENALI_CTL_224_DATA
#undef DENALI_CTL_225_DATA
#undef DENALI_CTL_226_DATA
#undef DENALI_CTL_227_DATA
#undef DENALI_CTL_228_DATA
#undef DENALI_CTL_229_DATA
#undef DENALI_CTL_230_DATA
#undef DENALI_CTL_231_DATA
#undef DENALI_CTL_232_DATA
#undef DENALI_CTL_233_DATA
#undef DENALI_CTL_234_DATA
#undef DENALI_CTL_235_DATA
#undef DENALI_CTL_236_DATA
#undef DENALI_CTL_237_DATA
#undef DENALI_CTL_238_DATA
#undef DENALI_CTL_239_DATA
#undef DENALI_CTL_240_DATA
#undef DENALI_CTL_241_DATA
#undef DENALI_CTL_242_DATA
#undef DENALI_CTL_243_DATA
#undef DENALI_CTL_244_DATA
#undef DENALI_CTL_245_DATA
#undef DENALI_CTL_246_DATA
#undef DENALI_CTL_247_DATA
#undef DENALI_CTL_248_DATA
#undef DENALI_CTL_249_DATA
#undef DENALI_CTL_250_DATA
#undef DENALI_CTL_251_DATA
#undef DENALI_CTL_252_DATA
#undef DENALI_CTL_253_DATA
#undef DENALI_CTL_254_DATA
#undef DENALI_CTL_255_DATA
#undef DENALI_CTL_256_DATA
#undef DENALI_CTL_257_DATA
#undef DENALI_CTL_258_DATA
#undef DENALI_CTL_259_DATA
#undef DENALI_CTL_260_DATA
#undef DENALI_CTL_261_DATA
#undef DENALI_CTL_262_DATA
#undef DENALI_CTL_263_DATA
#undef DENALI_CTL_264_DATA
#undef DENALI_CTL_265_DATA
#undef DENALI_CTL_266_DATA
#undef DENALI_CTL_267_DATA
#undef DENALI_CTL_268_DATA
#undef DENALI_CTL_269_DATA
#undef DENALI_CTL_270_DATA
#undef DENALI_CTL_271_DATA
#undef DENALI_CTL_272_DATA
#undef DENALI_CTL_273_DATA
#undef DENALI_CTL_274_DATA
#undef DENALI_CTL_275_DATA
#undef DENALI_CTL_276_DATA
#undef DENALI_CTL_277_DATA
#undef DENALI_CTL_278_DATA
#undef DENALI_CTL_279_DATA
#undef DENALI_CTL_280_DATA
#undef DENALI_CTL_281_DATA
#undef DENALI_CTL_282_DATA
#undef DENALI_CTL_283_DATA
#undef DENALI_CTL_284_DATA
#undef DENALI_CTL_285_DATA
#undef DENALI_CTL_286_DATA
#undef DENALI_CTL_287_DATA
#undef DENALI_CTL_288_DATA
#undef DENALI_CTL_289_DATA
#undef DENALI_CTL_290_DATA
#undef DENALI_CTL_291_DATA
#undef DENALI_CTL_292_DATA
#undef DENALI_CTL_293_DATA
#undef DENALI_CTL_294_DATA
#undef DENALI_CTL_295_DATA
#undef DENALI_CTL_296_DATA
#undef DENALI_CTL_297_DATA
#undef DENALI_CTL_298_DATA
#undef DENALI_CTL_299_DATA
#undef DENALI_CTL_300_DATA
#undef DENALI_CTL_301_DATA
#undef DENALI_CTL_302_DATA
#undef DENALI_CTL_303_DATA
#undef DENALI_CTL_304_DATA
#undef DENALI_CTL_305_DATA
#undef DENALI_CTL_306_DATA
#undef DENALI_CTL_307_DATA
#undef DENALI_CTL_308_DATA
#undef DENALI_CTL_309_DATA
#undef DENALI_CTL_310_DATA
#undef DENALI_CTL_311_DATA
#undef DENALI_CTL_312_DATA
#undef DENALI_CTL_313_DATA
#undef DENALI_CTL_314_DATA
#undef DENALI_CTL_315_DATA
#undef DENALI_CTL_316_DATA
#undef DENALI_CTL_317_DATA
#undef DENALI_CTL_318_DATA
#undef DENALI_CTL_319_DATA
#undef DENALI_CTL_320_DATA
#undef DENALI_CTL_321_DATA
#undef DENALI_CTL_322_DATA
#undef DENALI_CTL_323_DATA
#undef DENALI_CTL_324_DATA
#undef DENALI_CTL_325_DATA
#undef DENALI_CTL_326_DATA
#undef DENALI_CTL_327_DATA
#undef DENALI_CTL_328_DATA
#undef DENALI_CTL_329_DATA
#undef DENALI_CTL_330_DATA
#undef DENALI_CTL_331_DATA
#undef DENALI_CTL_332_DATA
#undef DENALI_CTL_333_DATA
#undef DENALI_CTL_334_DATA
#undef DENALI_CTL_335_DATA
#undef DENALI_CTL_336_DATA
#undef DENALI_CTL_337_DATA
#undef DENALI_CTL_338_DATA
#undef DENALI_CTL_339_DATA
#undef DENALI_CTL_340_DATA
#undef DENALI_CTL_341_DATA
#undef DENALI_CTL_342_DATA
#undef DENALI_CTL_343_DATA
#undef DENALI_CTL_344_DATA
#undef DENALI_CTL_345_DATA
#undef DENALI_CTL_346_DATA
#undef DENALI_CTL_347_DATA
#undef DENALI_CTL_348_DATA
#undef DENALI_CTL_349_DATA
#undef DENALI_CTL_350_DATA
#undef DENALI_CTL_351_DATA
#undef DENALI_CTL_352_DATA
#undef DENALI_CTL_353_DATA
#undef DENALI_CTL_354_DATA
#undef DENALI_CTL_355_DATA
#undef DENALI_CTL_356_DATA
#undef DENALI_CTL_357_DATA
#undef DENALI_CTL_358_DATA
#undef DENALI_CTL_359_DATA
#undef DENALI_CTL_360_DATA
#undef DENALI_CTL_361_DATA
#undef DENALI_CTL_362_DATA
#undef DENALI_CTL_363_DATA
#undef DENALI_CTL_364_DATA
#undef DENALI_CTL_365_DATA
#undef DENALI_CTL_366_DATA
#undef DENALI_CTL_367_DATA
#undef DENALI_CTL_368_DATA
#undef DENALI_CTL_369_DATA
#undef DENALI_CTL_370_DATA
#undef DENALI_CTL_371_DATA
#undef DENALI_CTL_372_DATA
#undef DENALI_CTL_373_DATA
#undef DENALI_CTL_374_DATA

23
arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Configuration file for binman
*
* After building u-boot, can generate the SPKG output by running:
* tools/binman/binman build -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -O <outdir>
*/
#include <config.h>
/ {
binman: binman {
};
};
&binman {
mkimage {
filename = "u-boot.bin.spkg";
args = "-n board/schneider/rzn1-snarc/spkgimage.cfg -T spkgimage -a 0x20040000 -e 0x20040000";
u-boot {
};
};
};

92
arch/arm/dts/r9a06g032-rzn1-snarc.dts Normal file
View file

@ -0,0 +1,92 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for Schneider RZ/N1 Board
*
* Based on r9a06g032-rzn1d400-db.dts
*/
/dts-v1/;
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
#include "r9a06g032.dtsi"
/ {
model = "Schneider RZ/N1 Board";
compatible = "schneider,rzn1", "renesas,r9a06g032";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
plat_regs: syscon@4000c000 {
compatible = "syscon";
reg = <0x4000c000 0x1000>;
};
system-controller@4000c000 {
regmap = <&plat_regs>;
};
ddrctrl: memory-controller@4000d000 {
compatible = "cadence,ddr-ctrl";
reg = <0x4000d000 0x1000>, <0x4000e000 0x100>;
reg-names = "ddrc", "phy";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>;
clock-names = "clk_ddrc", "hclk_ddrc";
syscon = <&plat_regs>;
status = "disabled";
};
};
reboot {
compatible = "syscon-reboot";
regmap = <&plat_regs>;
offset = <0x198>; /* sysctrl.RSTEN */
mask = <0x40>; /* bit 6 = SWRST_REQ */
value = <0x40>;
};
};
&ddrctrl {
status = "okay";
conf-1 {
size = <0x40000000>; /* 1 GB */
#include "renesas/is43tr16256a_125k_CTL.h"
#include "r9a06g032-ddr.dtsi"
};
conf-2 {
size = <0x10000000>; /* 256 MB */
#include "renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h"
#include "r9a06g032-ddr.dtsi"
};
};
&pinctrl {
status = "okay";
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
bias-disable;
};
};
&uart0 {
pinctrl-0 = <&pins_uart0>;
pinctrl-names = "default";
status = "okay";
};

477
arch/arm/dts/r9a06g032.dtsi Normal file
View file

@ -0,0 +1,477 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
*
* Copyright (C) 2018 Renesas Electronics Europe Limited
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
/ {
compatible = "renesas,r9a06g032";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clocks = <&sysctrl R9A06G032_CLK_A7MP>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
clocks = <&sysctrl R9A06G032_CLK_A7MP>;
enable-method = "renesas,r9a06g032-smp";
cpu-release-addr = <0 0x4000c204>;
};
};
ext_jtag_clk: extjtagclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ext_mclk: extmclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
};
ext_rgmii_ref: extrgmiiref {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
ext_rtc_clk: extrtcclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges;
rtc0: rtc@40006000 {
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
reg = <0x40006000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm", "timer", "pps";
clocks = <&sysctrl R9A06G032_HCLK_RTC>;
clock-names = "hclk";
power-domains = <&sysctrl>;
status = "disabled";
};
wdt0: watchdog@40008000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40008000 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
status = "disabled";
};
wdt1: watchdog@40009000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40009000 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
status = "disabled";
};
sysctrl: system-controller@4000c000 {
compatible = "renesas,r9a06g032-sysctrl";
reg = <0x4000c000 0x1000>;
status = "okay";
#clock-cells = <1>;
#power-domain-cells = <0>;
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
#address-cells = <1>;
#size-cells = <1>;
dmamux: dma-router@a0 {
compatible = "renesas,rzn1-dmamux";
reg = <0xa0 4>;
#dma-cells = <6>;
dma-requests = <32>;
dma-masters = <&dma0 &dma1>;
};
};
udc: usb@4001e000 {
compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
reg = <0x4001e000 0x2000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_USBF>,
<&sysctrl R9A06G032_HCLK_USBPM>;
clock-names = "hclkf", "hclkpm";
power-domains = <&sysctrl>;
status = "disabled";
};
pci_usb: pci@40030000 {
compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
device_type = "pci";
clocks = <&sysctrl R9A06G032_HCLK_USBH>,
<&sysctrl R9A06G032_HCLK_USBPM>,
<&sysctrl R9A06G032_CLK_PCI_USB>;
clock-names = "hclkh", "hclkpm", "pciclk";
power-domains = <&sysctrl>;
reg = <0x40030000 0xc00>,
<0x40020000 0x1100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
/* Should map all possible DDR as inbound ranges, but
* the IP only supports a 256MB, 512MB, or 1GB window.
* flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
*/
dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
phys = <&usbphy>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x1000 0 0 0 0>;
phys = <&usbphy>;
phy-names = "usb";
};
};
uart0: serial@40060000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
reg = <0x40060000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
uart1: serial@40061000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
reg = <0x40061000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
uart2: serial@40062000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
reg = <0x40062000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
status = "disabled";
};
uart3: serial@50000000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
reg = <0x50000000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@50001000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
reg = <0x50001000 0x400>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart5: serial@50002000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
reg = <0x50002000 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart6: serial@50003000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
reg = <0x50003000 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
dma-names = "rx", "tx";
status = "disabled";
};
uart7: serial@50004000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
reg = <0x50004000 0x400>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
dma-names = "rx", "tx";
status = "disabled";
};
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
status = "okay";
};
nand_controller: nand-controller@40102000 {
compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
reg = <0x40102000 0x2000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
power-domains = <&sysctrl>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dma0: dma-controller@40104000 {
compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
reg = <0x40104000 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hclk";
clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
dma-channels = <8>;
dma-requests = <16>;
dma-masters = <1>;
#dma-cells = <3>;
block_size = <0xfff>;
data-width = <8>;
};
dma1: dma-controller@40105000 {
compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
reg = <0x40105000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hclk";
clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
dma-channels = <8>;
dma-requests = <16>;
dma-masters = <1>;
#dma-cells = <3>;
block_size = <0xfff>;
data-width = <8>;
};
gmac2: ethernet@44002000 {
compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
reg = <0x44002000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
clock-names = "stmmaceth";
power-domains = <&sysctrl>;
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <2048>;
rx-fifo-depth = <4096>;
status = "disabled";
};
eth_miic: eth-miic@44030000 {
compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x44030000 0x10000>;
clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
<&sysctrl R9A06G032_CLK_RGMII_REF>,
<&sysctrl R9A06G032_CLK_RMII_REF>,
<&sysctrl R9A06G032_HCLK_SWITCH_RG>;
clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
power-domains = <&sysctrl>;
status = "disabled";
mii_conv1: mii-conv@1 {
reg = <1>;
status = "disabled";
};
mii_conv2: mii-conv@2 {
reg = <2>;
status = "disabled";
};
mii_conv3: mii-conv@3 {
reg = <3>;
status = "disabled";
};
mii_conv4: mii-conv@4 {
reg = <4>;
status = "disabled";
};
mii_conv5: mii-conv@5 {
reg = <5>;
status = "disabled";
};
};
switch: switch@44050000 {
compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
reg = <0x44050000 0x10000>;
clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
<&sysctrl R9A06G032_CLK_SWITCH>;
clock-names = "hclk", "clk";
power-domains = <&sysctrl>;
status = "disabled";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
switch_port0: port@0 {
reg = <0>;
pcs-handle = <&mii_conv5>;
status = "disabled";
};
switch_port1: port@1 {
reg = <1>;
pcs-handle = <&mii_conv4>;
status = "disabled";
};
switch_port2: port@2 {
reg = <2>;
pcs-handle = <&mii_conv3>;
status = "disabled";
};
switch_port3: port@3 {
reg = <3>;
pcs-handle = <&mii_conv2>;
status = "disabled";
};
switch_port4: port@4 {
reg = <4>;
ethernet = <&gmac2>;
label = "cpu";
phy-mode = "internal";
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x44101000 0x1000>, /* Distributer */
<0x44102000 0x2000>, /* CPU interface */
<0x44104000 0x2000>, /* Virt interface control */
<0x44106000 0x2000>; /* Virt CPU interface */
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
can0: can@52104000 {
compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
reg-io-width = <4>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
power-domains = <&sysctrl>;
status = "disabled";
};
can1: can@52105000 {
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52105000 0x800>;
reg-io-width = <4>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
power-domains = <&sysctrl>;
status = "disabled";
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
arm,cpu-registers-not-fw-configured;
always-on;
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
usbphy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "disabled";
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "rk3328-nanopi-r2s-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
*/
/dts-v1/;
#include "rk3328-nanopi-r2s.dts"
/ {
model = "FriendlyElec NanoPi R2C";
compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
};
&gmac2io {
phy-handle = <&yt8521s>;
tx_delay = <0x22>;
rx_delay = <0x12>;
mdio {
/delete-node/ ethernet-phy@1;
yt8521s: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
motorcomm,clk-out-frequency-hz = <125000000>;
motorcomm,keep-pll-enabled;
motorcomm,auto-sleep-disabled;
pinctrl-0 = <&eth_phy_reset_pin>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Radxa Limited
*/
#include "rk3399-rock-pi-4-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2019 Radxa Limited
* Copyright (c) 2022 Amarula Solutions(India)
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "rk3399.dtsi"
#include "rk3399-t-opp.dtsi"
/ {
model = "Radxa ROCK 4C+";
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led1 &user_led2>;
/* USER_LED1 */
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
/* USER_LED2 */
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc_3v3: vcc-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_phy1: vcc3v3-phy1-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_phy1";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3>;
};
vcc5v0_host1: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host1";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_host0_s0>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vdd_log: vdd-log-regulator {
compatible = "regulator-fixed";
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc3v3_phy1>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x2a>;
rx_delay = <0x21>;
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
avdd-0v9-supply = <&vcc_0v9_s0>;
avdd-1v8-supply = <&vcc_1v8_s0>;
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
i2c-scl-falling-time-ns = <30>;
i2c-scl-rising-time-ns = <180>;
clock-frequency = <400000>;
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_buck5_s3>;
vcc6-supply = <&vcc_buck5_s3>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_center: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_center";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_cpu_l";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc3v3_sys";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_buck5_s3: DCDC_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_buck5_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_0v9_s3: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc_0v9_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_0v9_s0: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc_0v9_s0";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vcc_1v8_s0: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_mipi: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_mipi";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5_s0: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc_1v5_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0_s0: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_3v0_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sdio_s0: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sdio_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_cam: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_cam";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc5v0_host0_s0: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc5v0_host0_s0";
regulator-state-mem {
regulator-on-in-suspend;
};
};
lcd_3v3: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "lcd_3v3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-compatible = "fan53555-reg";
pinctrl-0 = <&vsel1_gpio>;
vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
regulator-compatible = "fan53555-reg";
pinctrl-0 = <&vsel2_gpio>;
vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-initial-mode = <1>; /* 1:force PWM 2:auto */
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
audio-supply = <&vcc_1v8_s0>;
bt656-supply = <&vcc_3v0_s0>;
gpio1830-supply = <&vcc_3v0_s0>;
sdmmc-supply = <&vcc_sdio_s0>;
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
user_led1: user-led1 {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led2: user-led2 {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdmmc {
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>,
<4 9 1 &pcfg_pull_up_8ma>,
<4 10 1 &pcfg_pull_up_8ma>,
<4 11 1 &pcfg_pull_up_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>;
};
};
usb-typec {
vcc5v0_typec0_en: vcc5v0-typec-en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0_s0>;
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8_s3>;
};
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
non-removable;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <800>;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vcc_sdio_s0>;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host1>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host1>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
clocks = <&rk809 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8_s3>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
extcon = <&u2phy0>;
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "host";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

6
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
View file

@ -12,6 +12,12 @@
}; };
}; };
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
};
&vdd_log { &vdd_log {
regulator-init-microvolt = <950000>; regulator-init-microvolt = <950000>;
}; };

239
arch/arm/dts/rk3399-rock-pi-4.dtsi
View file

@ -6,14 +6,15 @@
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h> #include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi" #include "rk3399.dtsi"
#include "rk3399-opp.dtsi" #include "rk3399-opp.dtsi"
/ { / {
aliases { aliases {
mmc0 = &sdmmc; mmc0 = &sdhci;
mmc1 = &sdhci; mmc1 = &sdmmc;
}; };
chosen { chosen {
@ -27,6 +28,20 @@
#clock-cells = <0>; #clock-cells = <0>;
}; };
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_led2>;
/* USER_LED2 */
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
sdio_pwrseq: sdio-pwrseq { sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple"; compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>; clocks = <&rk808 1>;
@ -36,6 +51,40 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
}; };
sound: sound {
compatible = "audio-graph-card";
label = "Analog";
dais = <&i2s0_p0>;
};
sound-dit {
compatible = "audio-graph-card";
label = "SPDIF";
dais = <&spdif_p0>;
};
spdif-dit {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port {
dit_p0_0: endpoint {
remote-endpoint = <&spdif_p0_0>;
};
};
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vbus_typec";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc12v_dcin: dc-12v { vcc12v_dcin: dc-12v {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin"; regulator-name = "vcc12v_dcin";
@ -45,23 +94,13 @@
regulator-max-microvolt = <12000000>; regulator-max-microvolt = <12000000>;
}; };
vcc5v0_sys: vcc-sys { vcc3v3_lan: vcc3v3-lan-regulator {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys"; regulator-name = "vcc3v3_lan";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_dcin>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>; vin-supply = <&vcc3v3_sys>;
}; };
@ -98,35 +137,35 @@
vin-supply = <&vcc5v0_sys>; vin-supply = <&vcc5v0_sys>;
}; };
vcc5v0_typec: vcc5v0-typec-regulator { vcc5v0_sys: vcc-sys {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
enable-active-high; regulator-name = "vcc5v0_sys";
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc_lan: vcc3v3-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_lan";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
}; };
vdd_log: vdd-log { vdd_log: vdd-log {
compatible = "pwm-regulator"; compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>; pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc5v0_sys>;
regulator-name = "vdd_log"; regulator-name = "vdd_log";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <800000>; regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>; regulator-max-microvolt = <1400000>;
vin-supply = <&vcc5v0_sys>;
}; };
}; };
@ -162,7 +201,7 @@
assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>; assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input"; clock_in_out = "input";
phy-supply = <&vcc_lan>; phy-supply = <&vcc3v3_lan>;
phy-mode = "rgmii"; phy-mode = "rgmii";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>; pinctrl-0 = <&rgmii_pins>;
@ -180,6 +219,8 @@
}; };
&hdmi { &hdmi {
avdd-0v9-supply = <&vcca0v9_hdmi>;
avdd-1v8-supply = <&vcca1v8_hdmi>;
ddc-i2c-bus = <&i2c3>; ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>; pinctrl-0 = <&hdmi_cec>;
@ -267,8 +308,8 @@
}; };
}; };
vcc1v8_codec: LDO_REG1 { vcca1v8_codec: LDO_REG1 {
regulator-name = "vcc1v8_codec"; regulator-name = "vcca1v8_codec";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
@ -278,8 +319,8 @@
}; };
}; };
vcc1v8_hdmi: LDO_REG2 { vcca1v8_hdmi: LDO_REG2 {
regulator-name = "vcc1v8_hdmi"; regulator-name = "vcca1v8_hdmi";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
@ -336,8 +377,8 @@
}; };
}; };
vcc0v9_hdmi: LDO_REG7 { vcca0v9_hdmi: LDO_REG7 {
regulator-name = "vcc0v9_hdmi"; regulator-name = "vcca0v9_hdmi";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
@ -422,6 +463,20 @@
i2c-scl-rising-time-ns = <300>; i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>; i2c-scl-falling-time-ns = <15>;
status = "okay"; status = "okay";
es8316: codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s0_p0_0>;
};
};
};
}; };
&i2c3 { &i2c3 {
@ -441,12 +496,19 @@
rockchip,capture-channels = <2>; rockchip,capture-channels = <2>;
rockchip,playback-channels = <2>; rockchip,playback-channels = <2>;
status = "okay"; status = "okay";
i2s0_p0: port {
i2s0_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
}; };
&i2s1 { &i2s1 {
rockchip,playback-channels = <2>; rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>; rockchip,capture-channels = <2>;
status = "okay";
}; };
&i2s2 { &i2s2 {
@ -454,21 +516,10 @@
}; };
&io_domains { &io_domains {
status = "okay"; audio-supply = <&vcca1v8_codec>;
bt656-supply = <&vcc_3v0>; bt656-supply = <&vcc_3v0>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>; gpio1830-supply = <&vcc_3v0>;
}; sdmmc-supply = <&vcc_sdio>;
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_3v0>;
};
&pcie_phy {
status = "okay"; status = "okay";
}; };
@ -483,6 +534,10 @@
status = "okay"; status = "okay";
}; };
&pcie_phy {
status = "okay";
};
&pinctrl { &pinctrl {
bt { bt {
bt_enable_h: bt-enable-h { bt_enable_h: bt-enable-h {
@ -498,12 +553,42 @@
}; };
}; };
es8316 {
hp_detect: hp-detect {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
hp_int: hp-int {
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
user_led2: user-led2 {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie { pcie {
pcie_pwr_en: pcie-pwr-en { pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
}; };
}; };
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio0 { sdio0 {
sdio0_bus4: sdio0-bus4 { sdio0_bus4: sdio0-bus4 {
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
@ -521,20 +606,6 @@
}; };
}; };
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_pin: vsel2-pin {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb-typec { usb-typec {
vcc5v0_typec_en: vcc5v0-typec-en { vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
@ -558,6 +629,11 @@
}; };
}; };
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pwm2 { &pwm2 {
status = "okay"; status = "okay";
}; };
@ -568,6 +644,14 @@
vref-supply = <&vcc_1v8>; vref-supply = <&vcc_1v8>;
}; };
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdio0 { &sdio0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -595,12 +679,13 @@
status = "okay"; status = "okay";
}; };
&sdhci { &spdif {
bus-width = <8>;
mmc-hs400-1_8v; spdif_p0: port {
mmc-hs400-enhanced-strobe; spdif_p0_0: endpoint {
non-removable; remote-endpoint = <&dit_p0_0>;
status = "okay"; };
};
}; };
&tcphy0 { &tcphy0 {
@ -675,15 +760,15 @@
status = "okay"; status = "okay";
}; };
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_0 { &usbdrd_dwc3_0 {
status = "okay"; status = "okay";
dr_mode = "host"; dr_mode = "host";
}; };
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 { &usbdrd_dwc3_1 {
status = "okay"; status = "okay";
dr_mode = "host"; dr_mode = "host";

0
arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi → arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
View file

46
arch/arm/dts/rk3399-rock-pi-4b.dts
View file

@ -1,46 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
*/
/dts-v1/;
#include "rk3399-rock-pi-4.dtsi"
/ {
model = "Radxa ROCK Pi 4B";
compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399";
aliases {
mmc2 = &sdio0;
};
};
&sdio0 {
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&uart0 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};

20
arch/arm/dts/rk3399-rock-pi-4c.dts
View file

@ -17,6 +17,13 @@
}; };
}; };
&es8316 {
pinctrl-0 = <&hp_detect &hp_int>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>;
};
&sdio0 { &sdio0 {
status = "okay"; status = "okay";
@ -24,25 +31,32 @@
compatible = "brcm,bcm4329-fmac"; compatible = "brcm,bcm4329-fmac";
reg = <1>; reg = <1>;
interrupt-parent = <&gpio0>; interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake"; interrupt-names = "host-wake";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>; pinctrl-0 = <&wifi_host_wake_l>;
}; };
}; };
&sound {
hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
};
&uart0 { &uart0 {
status = "okay"; status = "okay";
bluetooth { bluetooth {
compatible = "brcm,bcm43438-bt"; compatible = "brcm,bcm4345c5";
clocks = <&rk808 1>; clocks = <&rk808 1>;
clock-names = "ext_clock"; clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
max-speed = <1500000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
}; };
}; };

5
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
View file

@ -15,6 +15,11 @@
}; };
}; };
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
};
&spi1 { &spi1 {
spi_flash: flash@0 { spi_flash: flash@0 {
bootph-all; bootph-all;

114
arch/arm/dts/rk3399-t-opp.dtsi Normal file
View file

@ -0,0 +1,114 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
* Copyright (c) 2022 Radxa Limited
*/
/ {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <875000 875000 1250000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000 875000 1250000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <900000 900000 1250000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <975000 975000 1250000>;
};
};
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <875000 875000 1250000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <875000 875000 1250000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <875000 875000 1250000>;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <925000 925000 1250000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000 1000000 1250000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1075000 1075000 1250000>;
};
opp06 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1150000 1150000 1250000>;
};
};
gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <875000 875000 1150000>;
};
opp01 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <875000 875000 1150000>;
};
opp02 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <875000 875000 1150000>;
};
opp03 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000 975000 1150000>;
};
};
};
&cpu_l0 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l1 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l2 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_l3 {
operating-points-v2 = <&cluster0_opp>;
};
&cpu_b0 {
operating-points-v2 = <&cluster1_opp>;
};
&cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};

1
arch/arm/dts/rk3399-u-boot.dtsi
View file

@ -120,6 +120,7 @@
&sdhci { &sdhci {
max-frequency = <200000000>; max-frequency = <200000000>;
bootph-all; bootph-all;
u-boot,spl-fifo-mode;
}; };
&sdmmc { &sdmmc {

86
arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi Normal file
View file

@ -0,0 +1,86 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk356x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0;
};
rng: rng@fe388000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xfe388000 0x0 0x2000>;
status = "okay";
};
};
&cru {
assigned-clocks =
<&pmucru CLK_RTC_32K>,
<&pmucru PLL_PPLL>,
<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
<&cru PLL_GPLL>,
<&cru ACLK_BUS>, <&cru PCLK_BUS>,
<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
<&cru HCLK_TOP>, <&cru PCLK_TOP>,
<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
<&cru CPLL_500M>, <&cru CPLL_333M>,
<&cru CPLL_250M>, <&cru CPLL_125M>,
<&cru CPLL_100M>, <&cru CPLL_62P5M>,
<&cru CPLL_50M>, <&cru CPLL_25M>;
assigned-clock-rates =
<32768>,
<200000000>,
<100000000>, <1000000000>,
<1188000000>,
<150000000>, <100000000>,
<500000000>, <400000000>,
<150000000>, <100000000>,
<300000000>, <150000000>,
<500000000>, <333333333>,
<250000000>, <125000000>,
<100000000>, <62500000>,
<50000000>, <25000000>;
assigned-clock-parents =
<&pmucru CLK_RTC32K_FRAC>;
};
&i2c2 {
status = "okay";
};
&pmucru {
assigned-clocks = <&pmucru SCLK_32K_IOE>;
assigned-clock-parents = <&pmucru CLK_RTC_32K>;
};
/*
* We don't need the clocks, but if they are present they may cause
* probing to fail so we remove them for U-Boot.
*/
&rk817 {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ clocks;
/delete-property/ clock-names;
};
&sdhci {
pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
<&emmc_datastrobe>, <&emmc_rstnout>;
pinctrl-names = "default";
bus-width = <8>;
max-frequency = <200000000>;
mmc-hs200-1_8v;
non-removable;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart2 {
clock-frequency = <24000000>;
bootph-all;
status = "okay";
};

18
arch/arm/dts/rk3566-anbernic-rgxx3.dts Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3566-anbernic-rgxx3.dtsi"
/ {
/*
* Note this is a pseudo-model that doesn't exist in mainline Linux.
* This model is used for all RGXX3 devices and the board.c file will
* set the correct dtb name for loading mainline Linux automatically.
*/
model = "RGXX3";
compatible = "anbernic,rg353m", "anbernic,rg353p",
"anbernic,rg353v", "anbernic,rg353vs",
"anbernic,rg503", "rockchip,rk3566";
};

786
arch/arm/dts/rk3566-anbernic-rgxx3.dtsi Normal file
View file

@ -0,0 +1,786 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3566.dtsi"
/ {
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
adc-joystick {
compatible = "adc-joystick";
io-channels = <&adc_mux 0>,
<&adc_mux 1>,
<&adc_mux 2>,
<&adc_mux 3>;
pinctrl-0 = <&joy_mux_en>;
pinctrl-names = "default";
poll-interval = <60>;
#address-cells = <1>;
#size-cells = <0>;
axis@0 {
reg = <0>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <1023 15>;
linux,code = <ABS_X>;
};
axis@1 {
reg = <1>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <15 1023>;
linux,code = <ABS_RX>;
};
axis@2 {
reg = <2>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <15 1023>;
linux,code = <ABS_Y>;
};
axis@3 {
reg = <3>;
abs-flat = <32>;
abs-fuzz = <32>;
abs-range = <1023 15>;
linux,code = <ABS_RY>;
};
};
adc_keys: adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <60>;
/*
* Button is mapped to F key in BSP kernel, but
* according to input guidelines it should be mode.
*/
button-mode {
label = "MODE";
linux,code = <BTN_MODE>;
press-threshold-microvolt = <1750>;
};
};
adc_mux: adc-mux {
compatible = "io-channel-mux";
channels = "left_x", "right_x", "left_y", "right_y";
#io-channel-cells = <1>;
io-channels = <&saradc 3>;
io-channel-names = "parent";
mux-controls = <&gpio_mux>;
settle-time-us = <100>;
};
gpio_keys_control: gpio-keys-control {
compatible = "gpio-keys";
pinctrl-0 = <&btn_pins_ctrl>;
pinctrl-names = "default";
button-b {
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
label = "SOUTH";
linux,code = <BTN_SOUTH>;
};
button-down {
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
label = "DPAD-DOWN";
linux,code = <BTN_DPAD_DOWN>;
};
button-l1 {
gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
label = "TL";
linux,code = <BTN_TL>;
};
button-l2 {
gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
label = "TL2";
linux,code = <BTN_TL2>;
};
button-select {
gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
label = "SELECT";
linux,code = <BTN_SELECT>;
};
button-start {
gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
label = "START";
linux,code = <BTN_START>;
};
button-thumbl {
gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
label = "THUMBL";
linux,code = <BTN_THUMBL>;
};
button-thumbr {
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
label = "THUMBR";
linux,code = <BTN_THUMBR>;
};
button-up {
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
label = "DPAD-UP";
linux,code = <BTN_DPAD_UP>;
};
button-x {
gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
label = "NORTH";
linux,code = <BTN_NORTH>;
};
};
gpio_keys_vol: gpio-keys-vol {
compatible = "gpio-keys";
autorepeat;
pinctrl-0 = <&btn_pins_vol>;
pinctrl-names = "default";
button-vol-down {
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
label = "VOLUMEDOWN";
linux,code = <KEY_VOLUMEDOWN>;
};
button-vol-up {
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
label = "VOLUMEUP";
linux,code = <KEY_VOLUMEUP>;
};
};
gpio_mux: mux-controller {
compatible = "gpio-mux";
mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
<&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
#mux-control-cells = <0>;
};
hdmi-con {
compatible = "hdmi-connector";
ddc-i2c-bus = <&i2c5>;
type = "c";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds: gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
green_led: led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "on";
function = LED_FUNCTION_POWER;
gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
};
amber_led: led-1 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_CHARGING;
gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
retain-state-suspended;
};
red_led: led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk817 1>;
clock-names = "ext_clock";
pinctrl-0 = <&wifi_enable_h>;
pinctrl-names = "default";
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
};
vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&vcc_lcd_h>;
pinctrl-names = "default";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_lcd0_n";
vin-supply = <&vcc_3v3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_sys: regulator-vcc-sys {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
regulator-name = "vcc_sys";
};
vcc_wifi: regulator-vcc-wifi {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&vcc_wifi_h>;
pinctrl-names = "default";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_wifi";
};
vibrator: pwm-vibrator {
compatible = "pwm-vibrator";
pwm-names = "enable";
pwms = <&pwm5 0 1000000000 0>;
};
};
&combphy1 {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
pinctrl-0 = <&hdmitxm0_cec>;
pinctrl-names = "default";
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
status = "okay";
rk817: pmic@20 {
compatible = "rockchip,rk817";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
clock-names = "mclk";
clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
#clock-cells = <1>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&dcdc_boost>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_gpu: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_3v3: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x2>;
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcca1v8_pmu: LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdda_0v9: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v9_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vccio_acodec: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_acodec";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_pmu: LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_1v8: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_dvp: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc1v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc2v8_dvp: LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc2v8_dvp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
dcdc_boost: BOOST {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <4700000>;
regulator-max-microvolt = <5400000>;
regulator-name = "boost";
regulator-state-mem {
regulator-off-in-suspend;
};
};
otg_switch: OTG_SWITCH {
regulator-name = "otg_switch";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu: regulator@40 {
compatible = "fcs,fan53555";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-name = "vdd_cpu";
regulator-ramp-delay = <2300>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
/* Unknown/unused device at 0x3c */
status = "disabled";
};
&i2c5 {
pinctrl-0 = <&i2c5m1_xfer>;
pinctrl-names = "default";
status = "okay";
};
&i2s0_8ch {
status = "okay";
};
&i2s1_8ch {
pinctrl-0 = <&i2s1m0_sclktx
&i2s1m0_lrcktx
&i2s1m0_sdi0
&i2s1m0_sdo0>;
pinctrl-names = "default";
rockchip,trcm-sync-tx-only;
status = "okay";
};
&pinctrl {
gpio-btns {
btn_pins_ctrl: btn-pins-ctrl {
rockchip,pins =
<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
};
btn_pins_vol: btn-pins-vol {
rockchip,pins =
<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-led {
led_pins: led-pins {
rockchip,pins =
<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
joy-mux {
joy_mux_en: joy-mux-en {
rockchip,pins =
<0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc3v3-lcd {
vcc_lcd_h: vcc-lcd-h {
rockchip,pins =
<0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vcc-wifi {
vcc_wifi_h: vcc-wifi-h {
rockchip,pins =
<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
status = "okay";
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc1v8_dvp>;
vccio7-supply = <&vcc_3v3>;
};
&pwm5 {
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdmmc0 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
pinctrl-names = "default";
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>;
pinctrl-names = "default";
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vcc1v8_dvp>;
status = "okay";
};
&sdmmc2 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
vqmmc-supply = <&vcca1v8_pmu>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
};
};
&uart2 {
status = "okay";
};
/*
* Lack the schematics to verify, but port works as a peripheral
* (and not a host or OTG port).
*/
&usb_host0_xhci {
dr_mode = "peripheral";
phys = <&usb2phy0_otg>;
phy-names = "usb2-phy";
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>;
status = "okay";
};
&usb2phy0 {
status = "okay";
};
&usb2phy0_otg {
status = "okay";
};
&usb2phy1 {
status = "okay";
};
&usb2phy1_host {
status = "okay";
};
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

61
arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
View file

@ -11,6 +11,67 @@
}; };
}; };
&emmc_bus8 {
bootph-all;
};
&emmc_clk {
bootph-all;
};
&emmc_cmd {
bootph-all;
};
&emmc_datastrobe {
bootph-all;
};
&pinctrl {
bootph-all;
};
&pcfg_pull_none {
bootph-all;
};
&pcfg_pull_up_drv_level_2 {
bootph-all;
};
&pcfg_pull_up {
bootph-all;
};
&sdmmc0_bus4 {
bootph-all;
};
&sdmmc0_clk {
bootph-all;
};
&sdmmc0_cmd {
bootph-all;
};
&sdmmc0_det {
bootph-all;
};
&sdmmc0_pwren {
bootph-all;
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
};
&uart2m0_xfer {
bootph-all;
};
&uart2 { &uart2 {
clock-frequency = <24000000>; clock-frequency = <24000000>;
bootph-all; bootph-all;

78
arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
View file

@ -7,12 +7,67 @@
#include "rk356x-u-boot.dtsi" #include "rk356x-u-boot.dtsi"
/ { / {
aliases {
spi0 = &sfc;
};
chosen { chosen {
stdout-path = &uart2; stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
}; };
}; };
&emmc_bus8 {
bootph-all;
};
&emmc_clk {
bootph-all;
};
&emmc_cmd {
bootph-all;
};
&emmc_datastrobe {
bootph-all;
};
&fspi_pins {
bootph-all;
};
&pinctrl {
bootph-all;
};
&pcfg_pull_none {
bootph-all;
};
&pcfg_pull_up_drv_level_2 {
bootph-all;
};
&pcfg_pull_up {
bootph-all;
};
&sdmmc0_bus4 {
bootph-all;
};
&sdmmc0_clk {
bootph-all;
};
&sdmmc0_cmd {
bootph-all;
};
&sdmmc0_det {
bootph-all;
};
&sdhci { &sdhci {
cap-mmc-highspeed; cap-mmc-highspeed;
mmc-ddr-1_8v; mmc-ddr-1_8v;
@ -21,6 +76,23 @@
mmc-hs400-enhanced-strobe; mmc-hs400-enhanced-strobe;
}; };
&sfc {
bootph-pre-ram;
u-boot,spl-sfc-no-dma;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&sdmmc2 { &sdmmc2 {
status = "disabled"; status = "disabled";
}; };
@ -29,6 +101,10 @@
status = "disabled"; status = "disabled";
}; };
&uart2m0_xfer {
bootph-all;
};
&uart2 { &uart2 {
clock-frequency = <24000000>; clock-frequency = <24000000>;
bootph-all; bootph-all;

16
arch/arm/dts/rk356x-u-boot.dtsi
View file

@ -34,6 +34,11 @@
}; };
}; };
&xin24m {
bootph-all;
status = "okay";
};
&cru { &cru {
bootph-all; bootph-all;
status = "okay"; status = "okay";
@ -63,3 +68,14 @@
bootph-pre-ram; bootph-pre-ram;
status = "okay"; status = "okay";
}; };
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
&binman {
simple-bin-spi {
mkimage {
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
offset = <0x8000>;
};
};
};
#endif

182
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
View file

@ -4,15 +4,99 @@
*/ */
#include "rk3588-u-boot.dtsi" #include "rk3588-u-boot.dtsi"
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ { / {
aliases { aliases {
mmc1 = &sdmmc; mmc1 = &sdmmc;
spi0 = &sfc;
}; };
chosen { chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
}; };
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0_ps {
status = "okay";
};
&emmc_bus8 {
bootph-all;
};
&emmc_clk {
bootph-all;
};
&emmc_cmd {
bootph-all;
};
&emmc_data_strobe {
bootph-all;
};
&emmc_rstnout {
bootph-all;
};
&fspim2_pins {
bootph-all;
};
&pcie2x1l2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pinctrl {
bootph-all;
pcie {
pcie_reset_h: pcie-reset-h {
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie2x1l2_pins: pcie2x1l2-pins {
rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
<3 RK_PD0 4 &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pcfg_pull_none {
bootph-all;
};
&pcfg_pull_up_drv_level_2 {
bootph-all;
};
&pcfg_pull_up {
bootph-all;
}; };
&sdmmc { &sdmmc {
@ -20,6 +104,22 @@
status = "okay"; status = "okay";
}; };
&sdmmc_bus4 {
bootph-all;
};
&sdmmc_clk {
bootph-all;
};
&sdmmc_cmd {
bootph-all;
};
&sdmmc_det {
bootph-all;
};
&sdhci { &sdhci {
cap-mmc-highspeed; cap-mmc-highspeed;
mmc-ddr-1_8v; mmc-ddr-1_8v;
@ -27,3 +127,85 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
}; };
&sfc {
bootph-pre-ram;
u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
bootph-pre-ram;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&uart2m0_xfer {
bootph-all;
};
&usb_host0_ehci {
companion = <&usb_host0_ohci>;
phys = <&u2phy2_host>;
phy-names = "usb2-phy";
status = "okay";
};
&usb_host0_ohci {
phys = <&u2phy2_host>;
phy-names = "usb2-phy";
status = "okay";
};
&usb2phy2_grf {
status = "okay";
};
&u2phy2 {
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
reset-names = "phy", "apb";
clock-output-names = "usb480m_phy2";
status = "okay";
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&usb_host1_ehci {
companion = <&usb_host1_ohci>;
phys = <&u2phy3_host>;
phy-names = "usb2-phy";
status = "okay";
};
&usb_host1_ohci {
phys = <&u2phy3_host>;
phy-names = "usb2-phy";
status = "okay";
};
&usb2phy3_grf {
status = "okay";
};
&u2phy3 {
resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
reset-names = "phy", "apb";
clock-output-names = "usb480m_phy3";
status = "okay";
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};

184
arch/arm/dts/rk3588s-u-boot.dtsi
View file

@ -4,6 +4,7 @@
*/ */
#include "rockchip-u-boot.dtsi" #include "rockchip-u-boot.dtsi"
#include <dt-bindings/phy/phy.h>
/ { / {
dmc { dmc {
@ -12,12 +13,167 @@
status = "okay"; status = "okay";
}; };
usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";
reg = <0x0 0xfc800000 0x0 0x40000>;
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";
reg = <0x0 0xfc840000 0x0 0x40000>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";
reg = <0x0 0xfc880000 0x0 0x40000>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";
reg = <0x0 0xfc8c0000 0x0 0x40000>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
clock-names = "usbhost", "arbiter";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
pmu1_grf: syscon@fd58a000 { pmu1_grf: syscon@fd58a000 {
bootph-all; bootph-all;
compatible = "rockchip,rk3588-pmu1-grf", "syscon"; compatible = "rockchip,rk3588-pmu1-grf", "syscon";
reg = <0x0 0xfd58a000 0x0 0x2000>; reg = <0x0 0xfd58a000 0x0 0x2000>;
}; };
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfd5bc000 0x0 0x100>;
};
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5d8000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy2: usb2-phy@8000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
status = "disabled";
u2phy2_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
reg = <0x0 0xfd5dc000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
u2phy3: usb2-phy@c000 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
status = "disabled";
u2phy3_host: host-port {
#phy-cells = <0>;
status = "disabled";
};
};
};
pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x40 0x4f>;
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux", "pipe";
device_type = "pci";
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
<0 0 0 2 &pcie2x1l2_intc 1>,
<0 0 0 3 &pcie2x1l2_intc 2>,
<0 0 0 4 &pcie2x1l2_intc 3>;
linux,pci-domain = <4>;
num-ib-windows = <8>;
num-ob-windows = <8>;
num-viewport = <4>;
max-link-speed = <2>;
msi-map = <0x4000 &gic 0x4000 0x1000>;
num-lanes = <1>;
phys = <&combphy0_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PCIE>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
reg = <0xa 0x41000000 0x0 0x00400000>,
<0x0 0xfe190000 0x0 0x00010000>,
<0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
reset-names = "pcie", "periph";
rockchip,pipe-grf = <&php_grf>;
status = "disabled";
pcie2x1l2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
};
};
sfc: spi@fe2b0000 {
compatible = "rockchip,sfc";
reg = <0x0 0xfe2b0000 0x0 0x4000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
status = "disabled";
};
otp: nvmem@fecc0000 { otp: nvmem@fecc0000 {
compatible = "rockchip,rk3588-otp"; compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc0000 0x0 0x400>; reg = <0x0 0xfecc0000 0x0 0x400>;
@ -35,6 +191,22 @@
reg = <0x0 0xfe378000 0x0 0x200>; reg = <0x0 0xfe378000 0x0 0x200>;
status = "disabled"; status = "disabled";
}; };
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
<&cru PCLK_PHP_ROOT>;
clock-names = "refclk", "apbclk", "phpclk";
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
status = "disabled";
};
}; };
&xin24m { &xin24m {
@ -67,6 +239,7 @@
&sdhci { &sdhci {
bootph-pre-ram; bootph-pre-ram;
u-boot,spl-fifo-mode;
}; };
&uart2 { &uart2 {
@ -78,3 +251,14 @@
&ioc { &ioc {
bootph-pre-ram; bootph-pre-ram;
}; };
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
&binman {
simple-bin-spi {
mkimage {
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
offset = <0x8000>;
};
};
};
#endif

1
arch/arm/dts/sun50i-a64.dtsi
View file

@ -1197,6 +1197,7 @@
compatible = "allwinner,sun50i-a64-mipi-dphy", compatible = "allwinner,sun50i-a64-mipi-dphy",
"allwinner,sun6i-a31-mipi-dphy"; "allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>; reg = <0x01ca1000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>, clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_DPHY>; <&ccu CLK_DSI_DPHY>;
clock-names = "bus", "mod"; clock-names = "bus", "mod";

1
arch/arm/dts/sun50i-h5-orangepi-pc2.dts
View file

@ -3,6 +3,7 @@
/dts-v1/; /dts-v1/;
#include "sun50i-h5.dtsi" #include "sun50i-h5.dtsi"
#include "sun50i-h5-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>

2
arch/arm/dts/sun5i-gr8-chip-pro.dts
View file

@ -70,7 +70,7 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
status { led-0 {
label = "chip-pro:white:status"; label = "chip-pro:white:status";
gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
default-state = "on"; default-state = "on";

2
arch/arm/dts/sun5i-r8-chip.dts
View file

@ -70,7 +70,7 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
status { led-0 {
label = "chip:white:status"; label = "chip:white:status";
gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
default-state = "on"; default-state = "on";

12
arch/arm/dts/sun6i-a31.dtsi
View file

@ -820,7 +820,7 @@
clocks = <&ccu CLK_APB2_UART0>; clocks = <&ccu CLK_APB2_UART0>;
resets = <&ccu RST_APB2_UART0>; resets = <&ccu RST_APB2_UART0>;
dmas = <&dma 6>, <&dma 6>; dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -833,7 +833,7 @@
clocks = <&ccu CLK_APB2_UART1>; clocks = <&ccu CLK_APB2_UART1>;
resets = <&ccu RST_APB2_UART1>; resets = <&ccu RST_APB2_UART1>;
dmas = <&dma 7>, <&dma 7>; dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -846,7 +846,7 @@
clocks = <&ccu CLK_APB2_UART2>; clocks = <&ccu CLK_APB2_UART2>;
resets = <&ccu RST_APB2_UART2>; resets = <&ccu RST_APB2_UART2>;
dmas = <&dma 8>, <&dma 8>; dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -859,7 +859,7 @@
clocks = <&ccu CLK_APB2_UART3>; clocks = <&ccu CLK_APB2_UART3>;
resets = <&ccu RST_APB2_UART3>; resets = <&ccu RST_APB2_UART3>;
dmas = <&dma 9>, <&dma 9>; dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -872,7 +872,7 @@
clocks = <&ccu CLK_APB2_UART4>; clocks = <&ccu CLK_APB2_UART4>;
resets = <&ccu RST_APB2_UART4>; resets = <&ccu RST_APB2_UART4>;
dmas = <&dma 10>, <&dma 10>; dmas = <&dma 10>, <&dma 10>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -885,7 +885,7 @@
clocks = <&ccu CLK_APB2_UART5>; clocks = <&ccu CLK_APB2_UART5>;
resets = <&ccu RST_APB2_UART5>; resets = <&ccu RST_APB2_UART5>;
dmas = <&dma 22>, <&dma 22>; dmas = <&dma 22>, <&dma 22>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };

2
arch/arm/dts/sun6i-a31s-sina31s.dts
View file

@ -67,7 +67,7 @@
leds { leds {
compatible = "gpio-leds"; compatible = "gpio-leds";
status { led-0 {
label = "sina31s:status:usr"; label = "sina31s:status:usr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
}; };

10
arch/arm/dts/sun8i-a23-a33.dtsi
View file

@ -488,7 +488,7 @@
clocks = <&ccu CLK_BUS_UART0>; clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>; resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>; dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -501,7 +501,7 @@
clocks = <&ccu CLK_BUS_UART1>; clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>; resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>; dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -514,7 +514,7 @@
clocks = <&ccu CLK_BUS_UART2>; clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>; resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>; dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -527,7 +527,7 @@
clocks = <&ccu CLK_BUS_UART3>; clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>; resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 9>, <&dma 9>; dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -540,7 +540,7 @@
clocks = <&ccu CLK_BUS_UART4>; clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>; resets = <&ccu RST_BUS_UART4>;
dmas = <&dma 10>, <&dma 10>; dmas = <&dma 10>, <&dma 10>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };

1
arch/arm/dts/sun8i-a33.dtsi
View file

@ -278,6 +278,7 @@
dphy: d-phy@1ca1000 { dphy: d-phy@1ca1000 {
compatible = "allwinner,sun6i-a31-mipi-dphy"; compatible = "allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>; reg = <0x01ca1000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>, clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_DPHY>; <&ccu CLK_DSI_DPHY>;
clock-names = "bus", "mod"; clock-names = "bus", "mod";

15
arch/arm/dts/sun8i-a83t-bananapi-m3.dts
View file

@ -105,6 +105,21 @@
/* enables internal regulator and de-asserts reset */ /* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
}; };
/*
* Power supply for the SATA disk, behind a USB-SATA bridge.
* Since it is a USB device, there is no consumer in the DT, so we
* have to keep this always on.
*/
regulator-sata-disk-pwr {
compatible = "regulator-fixed";
regulator-name = "sata-disk-pwr";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
enable-active-high;
gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
};
}; };
&cpu0 { &cpu0 {

2
arch/arm/dts/sun8i-h3-beelink-x2.dts
View file

@ -57,7 +57,7 @@
ethernet1 = &sdiowifi; ethernet1 = &sdiowifi;
}; };
cec-gpio { cec {
compatible = "cec-gpio"; compatible = "cec-gpio";
cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
hdmi-phandle = <&hdmi>; hdmi-phandle = <&hdmi>;

2
arch/arm/dts/sun8i-h3-nanopi-duo2.dts
View file

@ -57,7 +57,7 @@
regulator-ramp-delay = <50>; /* 4ms */ regulator-ramp-delay = <50>; /* 4ms */
enable-active-high; enable-active-high;
enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
gpios-states = <0x1>; gpios-states = <0x1>;
states = <1100000 0>, <1300000 1>; states = <1100000 0>, <1300000 1>;

6
arch/arm/dts/sun8i-v3s.dtsi
View file

@ -479,7 +479,7 @@
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>; clocks = <&ccu CLK_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>; dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART0>; resets = <&ccu RST_BUS_UART0>;
status = "disabled"; status = "disabled";
}; };
@ -492,7 +492,7 @@
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>; clocks = <&ccu CLK_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>; dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART1>; resets = <&ccu RST_BUS_UART1>;
status = "disabled"; status = "disabled";
}; };
@ -505,7 +505,7 @@
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>; clocks = <&ccu CLK_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>; dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
resets = <&ccu RST_BUS_UART2>; resets = <&ccu RST_BUS_UART2>;
pinctrl-0 = <&uart2_pins>; pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default"; pinctrl-names = "default";

16
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
View file

@ -6,6 +6,8 @@
/dts-v1/; /dts-v1/;
#include "suniv-f1c100s.dtsi" #include "suniv-f1c100s.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ { / {
model = "Lichee Pi Nano"; model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@ -50,8 +52,22 @@
}; };
}; };
&otg_sram {
status = "okay";
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>; pinctrl-0 = <&uart0_pe_pins>;
status = "okay"; status = "okay";
}; };
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
status = "okay";
};

32
arch/arm/dts/suniv-f1c100s.dtsi
View file

@ -133,6 +133,32 @@
#size-cells = <0>; #size-cells = <0>;
}; };
usb_otg: usb@1c13000 {
compatible = "allwinner,suniv-f1c100s-musb";
reg = <0x01c13000 0x0400>;
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
interrupts = <26>;
interrupt-names = "mc";
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
status = "disabled";
};
usbphy: phy@1c13400 {
compatible = "allwinner,suniv-f1c100s-usb-phy";
reg = <0x01c13400 0x10>;
reg-names = "phy_ctrl";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb0_phy";
resets = <&ccu RST_USB_PHY0>;
reset-names = "usb0_reset";
#phy-cells = <1>;
status = "disabled";
};
ccu: clock@1c20000 { ccu: clock@1c20000 {
compatible = "allwinner,suniv-f1c100s-ccu"; compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c20000 0x400>; reg = <0x01c20000 0x400>;
@ -181,6 +207,12 @@
pins = "PE0", "PE1"; pins = "PE0", "PE1";
function = "uart0"; function = "uart0";
}; };
/omit-if-no-ref/
uart1_pa_pins: uart1-pa-pins {
pins = "PA2", "PA3";
function = "uart1";
};
}; };
i2c0: i2c@1c27000 { i2c0: i2c@1c27000 {

76
arch/arm/dts/suniv-f1c200s-lctech-pi.dts Normal file
View file

@ -0,0 +1,76 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Arm Ltd,
* based on work:
* Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
*/
/dts-v1/;
#include "suniv-f1c100s.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Lctech Pi F1C200s";
compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s",
"allwinner,suniv-f1c100s";
aliases {
serial0 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_vcc3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
disable-wp;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&otg_sram {
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pc_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pa_pins>;
status = "okay";
};
/*
* This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected
* to Vin, which supplies the board. Host mode works (if the board is powered
* otherwise), but peripheral is probably the intention.
*/
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
status = "okay";
};

81
arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts Normal file
View file

@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Icenowy Zheng <uwu@icenowy.me>
*/
/dts-v1/;
#include "suniv-f1c100s.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Popcorn Computer PopStick v1.1";
compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
"allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
linux,default-trigger = "heartbeat";
};
};
reg_vcc3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&mmc0 {
cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */
bus-width = <4>;
disable-wp;
vmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&otg_sram {
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pc_pins>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
status = "okay";
};

8
arch/arm/dts/sunxi-h3-h5.dtsi
View file

@ -709,7 +709,7 @@
clocks = <&ccu CLK_BUS_UART0>; clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>; resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 6>, <&dma 6>; dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -722,7 +722,7 @@
clocks = <&ccu CLK_BUS_UART1>; clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>; resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 7>, <&dma 7>; dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -735,7 +735,7 @@
clocks = <&ccu CLK_BUS_UART2>; clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>; resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 8>, <&dma 8>; dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@ -748,7 +748,7 @@
clocks = <&ccu CLK_BUS_UART3>; clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>; resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 9>, <&dma 9>; dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };

2
arch/arm/dts/zynq-dlc20-rev1.0.dts
View file

@ -26,7 +26,7 @@
}; };
chosen { chosen {
bootargs = "earlyprintk"; bootargs = "earlycon";
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };

44
arch/arm/dts/zynq-microzed.dts
View file

@ -8,7 +8,7 @@
#include "zynq-7000.dtsi" #include "zynq-7000.dtsi"
/ { / {
model = "Zynq MicroZED Board"; model = "Avnet MicroZed board";
compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
aliases { aliases {
@ -19,11 +19,11 @@
memory@0 { memory@0 {
device_type = "memory"; device_type = "memory";
reg = <0 0x40000000>; reg = <0x0 0x40000000>;
}; };
chosen { chosen {
bootargs = "earlyprintk"; bootargs = "earlycon";
stdout-path = "serial0:115200n8"; stdout-path = "serial0:115200n8";
}; };
@ -42,11 +42,6 @@
status = "okay"; status = "okay";
}; };
&uart1 {
bootph-all;
status = "okay";
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
@ -62,8 +57,41 @@
status = "okay"; status = "okay";
}; };
&uart1 {
bootph-all;
status = "okay";
};
&usb0 { &usb0 {
status = "okay"; status = "okay";
dr_mode = "host"; dr_mode = "host";
usb-phy = <&usb_phy0>; usb-phy = <&usb_phy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
};
&pinctrl0 {
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO29", "MIO31", "MIO36";
bias-high-impedance;
};
conf-tx {
pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
"MIO35", "MIO37", "MIO38", "MIO39";
bias-disable;
};
};
}; };

2
arch/arm/dts/zynqmp-sm-k26-revA.dts
View file

@ -224,7 +224,7 @@
}; };
partition@22A0000 { partition@22A0000 {
label = "User"; label = "User";
reg = <0x22A0000 0x1db0000>; /* 29.5 MB */ reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
}; };
}; };
}; };

7
arch/arm/include/asm/arch-imx/cpu.h
View file

@ -61,6 +61,13 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_CPU_IMX93 0xC1 /* dummy ID */ #define MXC_CPU_IMX93 0xC1 /* dummy ID */
#define MXC_CPU_IMX9351 0xC2 /* dummy ID */
#define MXC_CPU_IMX9332 0xC3 /* dummy ID */
#define MXC_CPU_IMX9331 0xC4 /* dummy ID */
#define MXC_CPU_IMX9322 0xC5 /* dummy ID */
#define MXC_CPU_IMX9321 0xC6 /* dummy ID */
#define MXC_CPU_IMX9312 0xC7 /* dummy ID */
#define MXC_CPU_IMX9311 0xC8 /* dummy ID */
#define MXC_SOC_MX6 0x60 #define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70 #define MXC_SOC_MX7 0x70

2
arch/arm/include/asm/arch-imx8/power-domain.h
View file

@ -6,7 +6,7 @@
#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H #ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
#define _ASM_ARCH_IMX8_POWER_DOMAIN_H #define _ASM_ARCH_IMX8_POWER_DOMAIN_H
#include <asm/arch/sci/types.h> #include <firmware/imx/sci/types.h>
struct imx8_power_domain_plat { struct imx8_power_domain_plat {
sc_rsrc_t resource_id; sc_rsrc_t resource_id;

138
arch/arm/include/asm/arch-imx8/sci/sci.h
View file

@ -1,138 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef _SC_SCI_H
#define _SC_SCI_H
#include <log.h>
#include <asm/arch/sci/types.h>
#include <asm/arch/sci/svc/misc/api.h>
#include <asm/arch/sci/svc/pad/api.h>
#include <asm/arch/sci/svc/pm/api.h>
#include <asm/arch/sci/svc/rm/api.h>
#include <asm/arch/sci/svc/seco/api.h>
#include <asm/arch/sci/rpc.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <linux/errno.h>
static inline int sc_err_to_linux(sc_err_t err)
{
int ret;
switch (err) {
case SC_ERR_NONE:
return 0;
case SC_ERR_VERSION:
case SC_ERR_CONFIG:
case SC_ERR_PARM:
ret = -EINVAL;
break;
case SC_ERR_NOACCESS:
case SC_ERR_LOCKED:
case SC_ERR_UNAVAILABLE:
ret = -EACCES;
break;
case SC_ERR_NOTFOUND:
case SC_ERR_NOPOWER:
ret = -ENODEV;
break;
case SC_ERR_IPC:
ret = -EIO;
break;
case SC_ERR_BUSY:
ret = -EBUSY;
break;
case SC_ERR_FAIL:
ret = -EIO;
break;
default:
ret = 0;
break;
}
debug("%s %d %d\n", __func__, err, ret);
return ret;
}
/* PM API*/
int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t *mode);
int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_bool_t enable, sc_bool_t autog);
int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clk_parent_t parent);
int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address);
sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
/* MISC API */
int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
sc_ctrl_t ctrl, u32 val);
int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
u32 *val);
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx);
void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
s16 *celsius, s8 *tenths);
/* RM API */
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
sc_faddr_t addr_end);
int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_pt_t pt, sc_rm_perm_t perm);
int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
sc_faddr_t *addr_end);
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
sc_bool_t isolated, sc_bool_t restricted,
sc_bool_t grant, sc_bool_t coherent);
int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_pt_t *pt);
/* PAD API */
int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
/* SMMU API */
int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
/* SECO API */
int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
sc_faddr_t addr);
int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
u32 *uid_h);
void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
sc_faddr_t export_addr, u16 max_size);
int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
u32 *data0, u32 *data1, u32 *data2, u32 *data3,
u32 *data4, u8 size);
#endif

2
arch/arm/include/asm/arch-imx8/sys_proto.h
View file

@ -3,7 +3,7 @@
* Copyright 2018 NXP * Copyright 2018 NXP
*/ */
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/mach-imx/sys_proto.h> #include <asm/mach-imx/sys_proto.h>
#include <asm/arch/power-domain.h> #include <asm/arch/power-domain.h>
#include <dm/platdata.h> #include <dm/platdata.h>

2
arch/arm/include/asm/arch-imx8m/ddr.h
View file

@ -709,7 +709,7 @@ int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void); void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void dram_config_save(struct dram_timing_info *info, unsigned long base); void *dram_config_save(struct dram_timing_info *info, unsigned long base);
void board_dram_ecc_scrub(void); void board_dram_ecc_scrub(void);
void ddrc_inline_ecc_scrub(unsigned int start_address, void ddrc_inline_ecc_scrub(unsigned int start_address,
unsigned int range_address); unsigned int range_address);

6
arch/arm/include/asm/arch-imx9/clock.h
View file

@ -205,6 +205,12 @@ struct clk_root_map {
u32 mux_type; u32 mux_type;
}; };
struct imx_clk_setting {
u32 clk_root;
enum ccm_clk_src src;
u32 div;
};
int clock_init(void); int clock_init(void);
u32 get_clk_src_rate(enum ccm_clk_src source); u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void); u32 get_lpuart_clk(void);

23
arch/arm/include/asm/arch-imx9/ddr.h
View file

@ -13,9 +13,21 @@
#define DDR_PHY_BASE 0x4E100000 #define DDR_PHY_BASE 0x4E100000
#define DDRMIX_BLK_CTRL_BASE 0x4E010000 #define DDRMIX_BLK_CTRL_BASE 0x4E010000
#define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120)
#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0)
#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8)
#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
#define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260)
#define REG_DDR_SDRAM_CFG_4 (DDR_CTL_BASE + 0x264)
#define REG_DDR_SDRAM_MD_CNTL_2 (DDR_CTL_BASE + 0x270)
#define REG_DDR_SDRAM_MPR4 (DDR_CTL_BASE + 0x28C)
#define REG_DDR_SDRAM_MPR5 (DDR_CTL_BASE + 0x290)
#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000)
#define SRC_BASE_ADDR (0x44460000) #define SRC_BASE_ADDR (0x44460000)
#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) #define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
@ -50,6 +62,12 @@ struct dram_cfg_param {
unsigned int val; unsigned int val;
}; };
struct dram_fsp_cfg {
struct dram_cfg_param ddrc_cfg[20];
struct dram_cfg_param mr_cfg[10];
unsigned int bypass;
};
struct dram_fsp_msg { struct dram_fsp_msg {
unsigned int drate; unsigned int drate;
enum fw_type fw_type; enum fw_type fw_type;
@ -61,6 +79,9 @@ struct dram_timing_info {
/* umctl2 config */ /* umctl2 config */
struct dram_cfg_param *ddrc_cfg; struct dram_cfg_param *ddrc_cfg;
unsigned int ddrc_cfg_num; unsigned int ddrc_cfg_num;
/* fsp config */
struct dram_fsp_cfg *fsp_cfg;
unsigned int fsp_cfg_num;
/* ddrphy config */ /* ddrphy config */
struct dram_cfg_param *ddrphy_cfg; struct dram_cfg_param *ddrphy_cfg;
unsigned int ddrphy_cfg_num; unsigned int ddrphy_cfg_num;
@ -84,7 +105,7 @@ int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void); void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void dram_config_save(struct dram_timing_info *info, unsigned long base); void *dram_config_save(struct dram_timing_info *info, unsigned long base);
void board_dram_ecc_scrub(void); void board_dram_ecc_scrub(void);
void ddrc_inline_ecc_scrub(unsigned int start_address, void ddrc_inline_ecc_scrub(unsigned int start_address,
unsigned int range_address); unsigned int range_address);

3
arch/arm/include/asm/arch-imx9/imx-regs.h
View file

@ -48,6 +48,9 @@
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) #define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) #define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h> #include <asm/types.h>
#include <stdbool.h> #include <stdbool.h>

1
arch/arm/include/asm/arch-rockchip/bootrom.h
View file

@ -48,6 +48,7 @@ enum {
BROM_BOOTSOURCE_SPINOR = 3, BROM_BOOTSOURCE_SPINOR = 3,
BROM_BOOTSOURCE_SPINAND = 4, BROM_BOOTSOURCE_SPINAND = 4,
BROM_BOOTSOURCE_SD = 5, BROM_BOOTSOURCE_SD = 5,
BROM_BOOTSOURCE_SPINOR_RK3588 = 6,
BROM_BOOTSOURCE_USB = 10, BROM_BOOTSOURCE_USB = 10,
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
}; };

21
arch/arm/include/asm/arch-rockchip/clock.h
View file

@ -194,5 +194,26 @@ int rockchip_get_clk(struct udevice **devp);
* Return: 0 success, or error value * Return: 0 success, or error value
*/ */
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/*
* rockchip_reset_bind_lut() - Bind soft reset device as child of clock device
* using a dedicated SoC lookup table
* @pdev: clock udevice
* @lookup_table: register lookup_table dedicated to SoC
* @reg_offset: the first offset in cru for softreset registers
* @reg_number: the reg numbers of softreset registers
* Return: 0 success, or error value
*/
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
u32 reg_offset, u32 reg_number);
/*
* rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
* using dedicated RK3588 lookup table
*
* @pdev: clock udevice
* @reg_offset: the first offset in cru for softreset registers
* @reg_number: the reg numbers of softreset registers
* Return: 0 success, or error value
*/
int rk3588_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
#endif #endif

2
arch/arm/include/asm/arch-sunxi/pmic_bus.h
View file

@ -6,7 +6,7 @@
*/ */
#ifndef _SUNXI_PMIC_BUS_H #ifndef _SUNXI_PMIC_BUS_H
#define _SUNXI_PMIS_BUS_H #define _SUNXI_PMIC_BUS_H
int pmic_bus_init(void); int pmic_bus_init(void);
int pmic_bus_read(u8 reg, u8 *data); int pmic_bus_read(u8 reg, u8 *data);

12
arch/arm/include/asm/mach-imx/sys_proto.h
View file

@ -82,7 +82,17 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
#define is_imx93() (is_cpu_type(MXC_CPU_IMX93)) #define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331) || \
is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
#define is_imx9322() (is_cpu_type(MXC_CPU_IMX9322))
#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))

109
arch/arm/mach-apple/board.c
View file

@ -343,6 +343,107 @@ static struct mm_region t6002_mem_map[] = {
} }
}; };
/* Apple M2 Pro/Max */
static struct mm_region t6020_mem_map[] = {
{
/* I/O */
.virt = 0x280000000,
.phys = 0x280000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x340000000,
.phys = 0x340000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x380000000,
.phys = 0x380000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5a0000000,
.phys = 0x5a0000000,
.size = SZ_512M,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PCIE */
.virt = 0x5c0000000,
.phys = 0x5c0000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x700000000,
.phys = 0x700000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0xb00000000,
.phys = 0xb00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0xf00000000,
.phys = 0xf00000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
.virt = 0x1300000000,
.phys = 0x1300000000,
.size = SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* RAM */
.virt = 0x10000000000,
.phys = 0x10000000000,
.size = 16UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* Framebuffer */
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map; struct mm_region *mem_map;
int board_init(void) int board_init(void)
@ -379,12 +480,14 @@ void build_mem_map(void)
if (of_machine_is_compatible("apple,t8103") || if (of_machine_is_compatible("apple,t8103") ||
of_machine_is_compatible("apple,t8112")) of_machine_is_compatible("apple,t8112"))
mem_map = t8103_mem_map; mem_map = t8103_mem_map;
else if (of_machine_is_compatible("apple,t6000")) else if (of_machine_is_compatible("apple,t6000") ||
mem_map = t6000_mem_map; of_machine_is_compatible("apple,t6001"))
else if (of_machine_is_compatible("apple,t6001"))
mem_map = t6000_mem_map; mem_map = t6000_mem_map;
else if (of_machine_is_compatible("apple,t6002")) else if (of_machine_is_compatible("apple,t6002"))
mem_map = t6002_mem_map; mem_map = t6002_mem_map;
else if (of_machine_is_compatible("apple,t6020") ||
of_machine_is_compatible("apple,t6021"))
mem_map = t6020_mem_map;
else else
panic("Unsupported SoC\n"); panic("Unsupported SoC\n");

2
arch/arm/mach-imx/cmd_dek.c
View file

@ -17,7 +17,7 @@
#include <mapmem.h> #include <mapmem.h>
#include <tee.h> #include <tee.h>
#ifdef CONFIG_IMX_SECO_DEK_ENCAP #ifdef CONFIG_IMX_SECO_DEK_ENCAP
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/mach-imx/image.h> #include <asm/mach-imx/image.h>
#endif #endif
#include <cpu_func.h> #include <cpu_func.h>

2
arch/arm/mach-imx/imx8/ahab.c
View file

@ -9,7 +9,7 @@
#include <log.h> #include <log.h>
#include <asm/global_data.h> #include <asm/global_data.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/mach-imx/sys_proto.h> #include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h> #include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>

4
arch/arm/mach-imx/imx8/cpu.c
View file

@ -19,7 +19,7 @@
#include <errno.h> #include <errno.h>
#include <spl.h> #include <spl.h>
#include <thermal.h> #include <thermal.h>
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/arch-imx/cpu.h> #include <asm/arch-imx/cpu.h>
#include <asm/armv8/cpu.h> #include <asm/armv8/cpu.h>
@ -89,7 +89,7 @@ static int imx8_init_mu(void *ctx, struct event *event)
return 0; return 0;
} }
EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu); EVENT_SPY(EVT_DM_POST_INIT_F, imx8_init_mu);
#if defined(CONFIG_ARCH_MISC_INIT) #if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void) int arch_misc_init(void)

2
arch/arm/mach-imx/imx8/fdt.c
View file

@ -5,7 +5,7 @@
#include <common.h> #include <common.h>
#include <log.h> #include <log.h>
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/global_data.h> #include <asm/global_data.h>
#include <dm/ofnode.h> #include <dm/ofnode.h>

2
arch/arm/mach-imx/imx8/iomux.c
View file

@ -8,7 +8,7 @@
#include <asm/global_data.h> #include <asm/global_data.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/iomux.h> #include <asm/arch/iomux.h>
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;

2
arch/arm/mach-imx/imx8/misc.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
#include <common.h> #include <common.h>
#include <log.h> #include <log.h>
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/mach-imx/sys_proto.h> #include <asm/mach-imx/sys_proto.h>
#include <imx_sip.h> #include <imx_sip.h>
#include <linux/arm-smccc.h> #include <linux/arm-smccc.h>

2
arch/arm/mach-imx/imx8/snvs_security_sc.c
View file

@ -15,7 +15,7 @@
#include <log.h> #include <log.h>
#include <stddef.h> #include <stddef.h>
#include <common.h> #include <common.h>
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#include <asm/arch-imx8/imx8-pins.h> #include <asm/arch-imx8/imx8-pins.h>
#include <asm/arch-imx8/snvs_security_sc.h> #include <asm/arch-imx8/snvs_security_sc.h>
#include <asm/global_data.h> #include <asm/global_data.h>

76
arch/arm/mach-imx/imx8m/soc.c
View file

@ -549,7 +549,7 @@ static int imx8m_check_clock(void *ctx, struct event *event)
return 0; return 0;
} }
EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
static void imx8m_setup_snvs(void) static void imx8m_setup_snvs(void)
{ {
@ -671,6 +671,7 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
/* Log entries with 1 parameter, skip 1 */ /* Log entries with 1 parameter, skip 1 */
case 0x80: /* Start to perform the device initialization */ case 0x80: /* Start to perform the device initialization */
case 0x81: /* The boot device initialization completes */ case 0x81: /* The boot device initialization completes */
case 0x82: /* Starts to execute boot device driver pre-config */
case 0x8f: /* The boot device initialization fails */ case 0x8f: /* The boot device initialization fails */
case 0x90: /* Start to read data from boot device */ case 0x90: /* Start to read data from boot device */
case 0x91: /* Reading data from boot device completes */ case 0x91: /* Reading data from boot device completes */
@ -1429,79 +1430,6 @@ int arch_misc_init(void)
} }
#endif #endif
void imx_tmu_arch_init(void *reg_base)
{
if (is_imx8mm() || is_imx8mn()) {
/* Load TCALIV and TASR from fuses */
struct ocotp_regs *ocotp =
(struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[3];
struct fuse_bank3_regs *fuse =
(struct fuse_bank3_regs *)bank->fuse_regs;
u32 tca_rt, tca_hr, tca_en;
u32 buf_vref, buf_slope;
tca_rt = fuse->ana0 & 0xFF;
tca_hr = (fuse->ana0 & 0xFF00) >> 8;
tca_en = (fuse->ana0 & 0x2000000) >> 25;
buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
buf_slope = (fuse->ana0 & 0xF0000) >> 16;
writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
(ulong)reg_base + 0x30);
}
#ifdef CONFIG_IMX8MP
/* Load TCALIV0/1/m40 and TRIM from fuses */
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[38];
struct fuse_bank38_regs *fuse =
(struct fuse_bank38_regs *)bank->fuse_regs;
struct fuse_bank *bank2 = &ocotp->bank[39];
struct fuse_bank39_regs *fuse2 =
(struct fuse_bank39_regs *)bank2->fuse_regs;
u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
u32 reg;
u32 tca40[2], tca25[2], tca105[2];
/* For blank sample */
if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
!fuse->ana_trim4 && !fuse2->ana_trim5) {
/* Use a default 25C binary codes */
tca25[0] = 1596;
tca25[1] = 1596;
writel(tca25[0], (ulong)reg_base + 0x30);
writel(tca25[1], (ulong)reg_base + 0x34);
return;
}
buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
writel(reg, (ulong)reg_base + 0x3c);
tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
tca25[1] = fuse2->ana_trim5 & 0xFFF;
tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
/* use 25c for 1p calibration */
writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
#endif
}
#if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
bool serror_need_skip = true; bool serror_need_skip = true;

5
arch/arm/mach-imx/imx8ulp/Kconfig
View file

@ -1,5 +1,10 @@
if ARCH_IMX8ULP if ARCH_IMX8ULP
config AHAB_BOOT
bool "Support i.MX8ULP AHAB features"
help
This option enables the support for AHAB secure boot.
config IMX8ULP config IMX8ULP
bool bool

1
arch/arm/mach-imx/imx8ulp/Makefile
View file

@ -5,6 +5,7 @@
obj-y += lowlevel_init.o obj-y += lowlevel_init.o
obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
ifeq ($(CONFIG_SPL_BUILD),y) ifeq ($(CONFIG_SPL_BUILD),y)
obj-y += upower/ obj-y += upower/

2
arch/arm/mach-imx/imx8ulp/soc.c
View file

@ -808,7 +808,7 @@ static int imx8ulp_evt_dm_post_init(void *ctx, struct event *event)
{ {
return imx8ulp_dm_post_init(); return imx8ulp_dm_post_init();
} }
EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_evt_dm_post_init); EVENT_SPY(EVT_DM_POST_INIT_F, imx8ulp_evt_dm_post_init);
#if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)

5
arch/arm/mach-imx/imx9/Kconfig
View file

@ -5,6 +5,11 @@ config AHAB_BOOT
help help
This option enables the support for AHAB secure boot. This option enables the support for AHAB secure boot.
config IMX9_LOW_DRIVE_MODE
bool "Configure to i.MX9 low drive mode"
help
This option enables the settings for iMX9 low drive mode.
config IMX9 config IMX9
bool bool
select HAS_CAAM select HAS_CAAM

131
arch/arm/mach-imx/imx9/clock.c
View file

@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
static struct imx_intpll_rate_table imx9_intpll_tbl[] = { static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */ INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */ INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */
INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */ INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */ INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */ INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
@ -35,8 +36,11 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
}; };
/* return in khz */ /* return in khz */
@ -202,6 +206,9 @@ int configure_intpll(enum ccm_clk_src pll, u32 freq)
return -EPERM; return -EPERM;
} }
/* Clear PLL HW CTRL SEL */
setbits_le32(&reg->ctrl.reg_clr, PLL_CTRL_HW_CTRL_SEL);
/* Bypass the PLL to ref */ /* Bypass the PLL to ref */
writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set); writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
@ -570,7 +577,7 @@ u32 imx_get_i2cclk(u32 i2c_num)
if (i2c_num > 7) if (i2c_num > 7)
return -EINVAL; return -EINVAL;
return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num); return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num);
} }
u32 get_lpuart_clk(void) u32 get_lpuart_clk(void)
@ -594,21 +601,27 @@ void init_uart_clk(u32 index)
void init_clk_usdhc(u32 index) void init_clk_usdhc(u32 index)
{ {
/* 400 Mhz */ u32 div;
if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
div = 3; /* 266.67 Mhz */
else
div = 2; /* 400 Mhz */
switch (index) { switch (index) {
case 0: case 0:
ccm_lpcg_on(CCGR_USDHC1, 0); ccm_lpcg_on(CCGR_USDHC1, 0);
ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2); ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div);
ccm_lpcg_on(CCGR_USDHC1, 1); ccm_lpcg_on(CCGR_USDHC1, 1);
break; break;
case 1: case 1:
ccm_lpcg_on(CCGR_USDHC2, 0); ccm_lpcg_on(CCGR_USDHC2, 0);
ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2); ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div);
ccm_lpcg_on(CCGR_USDHC2, 1); ccm_lpcg_on(CCGR_USDHC2, 1);
break; break;
case 2: case 2:
ccm_lpcg_on(CCGR_USDHC3, 0); ccm_lpcg_on(CCGR_USDHC3, 0);
ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2); ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div);
ccm_lpcg_on(CCGR_USDHC3, 1); ccm_lpcg_on(CCGR_USDHC3, 1);
break; break;
default: default:
@ -635,6 +648,9 @@ void dram_pll_init(ulong pll_val)
void dram_enable_bypass(ulong clk_val) void dram_enable_bypass(ulong clk_val)
{ {
switch (clk_val) { switch (clk_val) {
case MHZ(625):
ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD2, 1);
break;
case MHZ(400): case MHZ(400):
ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2); ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
break; break;
@ -670,42 +686,95 @@ void set_arm_clk(ulong freq)
{ {
/* Increase ARM clock to 1.7Ghz */ /* Increase ARM clock to 1.7Ghz */
ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
configure_intpll(ARM_PLL_CLK, 1700000000); configure_intpll(ARM_PLL_CLK, freq);
ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
} }
void set_arm_core_max_clk(void)
{
/* Increase ARM clock to max rate according to speed grade */
u32 speed = get_cpu_speed_grade_hz();
set_arm_clk(speed);
}
#endif
#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
struct imx_clk_setting imx_clk_settings[] = {
/* Set A55 clk to 500M */
{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 200M */
{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4},
/* Set A55 mtr bus to 133M */
{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Sentinel to 133M */
{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_wakeup to 133M */
{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */
{BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 to 133M */
{M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* WAKEUP_AXI to 200M */
{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4},
/* SWO TRACE to 133M */
{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
/* NIC to 250M */
{NIC_CLK_ROOT, SYS_PLL_PFD0, 4},
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
#else
struct imx_clk_setting imx_clk_settings[] = {
/*
* Set A55 clk to 500M. This clock root is normally used as intermediate
* clock source for A55 core/DSU when doing ARM PLL reconfig. set it to
* 500MHz(LD mode frequency) should be ok.
*/
{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 333M */
{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
/* Set A55 mtr bus to 133M */
{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Sentinel to 200M */
{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* Bus_wakeup to 133M */
{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */
{BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 to 200M */
{M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/*
* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
* generating MII clock at 2.5M
*/
{WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
/* SWO TRACE to 133M */
{SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */
{M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
/* NIC to 400M */
{NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
#endif #endif
int clock_init(void) int clock_init(void)
{ {
int i; int i;
/* Set A55 periphal to 333M */ for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
/* Set A55 mtr bus to 133M */ imx_clk_settings[i].src, imx_clk_settings[i].div);
ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); }
/* Sentinel to 200M */ if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); set_arm_clk(MHZ(900));
/* Bus_wakeup to 133M */
ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
/* Bus_AON to 133M */
ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
/* M33 to 200M */
ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
/*
* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
* generating MII clock at 2.5M
*/
ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
/* SWO TRACE to 133M */
ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
/* M33 systetick to 133M */
ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
/* NIC to 400M */
ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
/* NIC_APB to 133M */
ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
/* allow for non-secure access */ /* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++) for (i = 0; i < OSCPLL_END; i++)

10
arch/arm/mach-imx/imx9/imx_bootaux.c
View file

@ -34,17 +34,13 @@ int arch_auxiliary_core_down(u32 core_id)
int arch_auxiliary_core_up(u32 core_id, ulong addr) int arch_auxiliary_core_up(u32 core_id, ulong addr)
{ {
struct arm_smccc_res res; struct arm_smccc_res res;
u32 stack, pc;
if (!addr) if (!addr)
return -EINVAL; return -EINVAL;
stack = *(u32 *)addr; printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
pc = *(u32 *)(addr + 4);
printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc); arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
0, 0, 0, 0, &res); 0, 0, 0, 0, &res);
return 0; return 0;
@ -129,5 +125,5 @@ U_BOOT_CMD(
"Start auxiliary core", "Start auxiliary core",
"<address> [<core>]\n" "<address> [<core>]\n"
" - start auxiliary core [<core>] (default 0),\n" " - start auxiliary core [<core>] (default 0),\n"
" at address <address>\n" " at address <address> of auxiliary core view\n"
); );

388
arch/arm/mach-imx/imx9/soc.c
View file

@ -19,17 +19,24 @@
#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/syscounter.h> #include <asm/mach-imx/syscounter.h>
#include <asm/armv8/mmu.h> #include <asm/armv8/mmu.h>
#include <dm/device.h>
#include <dm/device_compat.h>
#include <dm/uclass.h> #include <dm/uclass.h>
#include <env.h> #include <env.h>
#include <env_internal.h> #include <env_internal.h>
#include <errno.h> #include <errno.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <imx_thermal.h>
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <thermal.h>
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/bootm.h> #include <asm/bootm.h>
#include <asm/arch-imx/cpu.h> #include <asm/arch-imx/cpu.h>
#include <asm/mach-imx/s400_api.h> #include <asm/mach-imx/s400_api.h>
#include <linux/delay.h> #include <fuse.h>
#include <asm/arch/ddr.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -38,19 +45,17 @@ struct rom_api *g_rom_api = (struct rom_api *)0x1980;
#ifdef CONFIG_ENV_IS_IN_MMC #ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno) __weak int board_mmc_get_env_dev(int devno)
{ {
return devno; } return devno;
}
int mmc_get_env_dev(void) int mmc_get_env_dev(void)
{ {
volatile gd_t *pgd = gd;
int ret; int ret;
u32 boot; u32 boot;
u16 boot_type; u16 boot_type;
u8 boot_instance; u8 boot_instance;
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot, ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);
((uintptr_t)&boot) ^ QUERY_BT_DEV);
set_gd(pgd);
if (ret != ROM_API_OKAY) { if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n"); puts("ROMAPI: failure at query_boot_info\n");
@ -70,6 +75,82 @@ int mmc_get_env_dev(void)
} }
#endif #endif
/*
* SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz
* xx 0000 2300
* xx 0001 2200
* xx 0010 2100
* xx 0011 2000
* xx 0100 1900
* xx 0101 1800
* xx 0110 1700
* xx 0111 1600
* xx 1000 1500
* xx 1001 1400
* xx 1010 1300
* xx 1011 1200
* xx 1100 1100
* xx 1101 1000
* xx 1110 900
* xx 1111 800
*/
u32 get_cpu_speed_grade_hz(void)
{
u32 speed, max_speed;
u32 val;
fuse_read(2, 3, &val);
val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
speed = MHZ(2300) - val * MHZ(100);
if (is_imx93())
max_speed = MHZ(1700);
/* In case the fuse of speed grade not programmed */
if (speed > max_speed)
speed = max_speed;
return speed;
}
/*
* `00` - Consumer 0C to 95C
* `01` - Ext. Consumer -20C to 105C
* `10` - Industrial -40C to 105C
* `11` - Automotive -40C to 125C
*/
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
u32 val;
fuse_read(2, 3, &val);
val = FIELD_GET(MARKETING_GRADING_MASK, val);
if (minc && maxc) {
if (val == TEMP_AUTOMOTIVE) {
*minc = -40;
*maxc = 125;
} else if (val == TEMP_INDUSTRIAL) {
*minc = -40;
*maxc = 105;
} else if (val == TEMP_EXTCOMMERCIAL) {
if (is_imx93()) {
/* imx93 only has extended industrial*/
*minc = -40;
*maxc = 125;
} else {
*minc = -20;
*maxc = 105;
}
} else {
*minc = 0;
*maxc = 95;
}
}
return val;
}
static void set_cpu_info(struct sentinel_get_info_data *info) static void set_cpu_info(struct sentinel_get_info_data *info)
{ {
gd->arch.soc_rev = info->soc; gd->arch.soc_rev = info->soc;
@ -77,11 +158,34 @@ static void set_cpu_info(struct sentinel_get_info_data *info)
memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32)); memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
} }
static u32 get_cpu_variant_type(u32 type)
{
/* word 19 */
u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9322;
if (npu_disable && core1_disable)
return type + 3;
else if (npu_disable)
return type + 2;
else if (core1_disable)
return type + 1;
return type;
}
u32 get_cpu_rev(void) u32 get_cpu_rev(void)
{ {
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev); return (get_cpu_variant_type(MXC_CPU_IMX93) << 12) |
(CHIP_REV_1_0 + rev);
} }
#define UNLOCK_WORD 0xD928C520 /* unlock word */ #define UNLOCK_WORD 0xD928C520 /* unlock word */
@ -180,21 +284,216 @@ static struct mm_region imx93_mem_map[] = {
struct mm_region *mem_map = imx93_mem_map; struct mm_region *mem_map = imx93_mem_map;
int dram_init(void) static unsigned int imx9_find_dram_entry_in_mem_map(void)
{ {
gd->ram_size = PHYS_SDRAM_SIZE; int i;
for (i = 0; i < ARRAY_SIZE(imx93_mem_map); i++)
if (imx93_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
}
void enable_caches(void)
{
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
* If OPTEE does not run, still update the MMU table according to dram banks structure
* to set correct dram size from board_phys_sdram_size
*/
int i = 0;
/*
* please make sure that entry initial value matches
* imx93_mem_map for DRAM1
*/
int entry = imx9_find_dram_entry_in_mem_map();
u64 attrs = imx93_mem_map[entry].attrs;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx93_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx93_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx93_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx93_mem_map[entry].phys, imx93_mem_map[entry].size);
i++; entry++;
}
icache_enable();
dcache_enable();
}
__weak int board_phys_sdram_size(phys_size_t *size)
{
phys_size_t start, end;
phys_size_t val;
if (!size)
return -EINVAL;
val = readl(REG_DDR_CS0_BNDS);
start = (val >> 16) << 24;
end = (val & 0xFFFF);
end = end ? end + 1 : 0;
end = end << 24;
*size = end - start;
val = readl(REG_DDR_CS1_BNDS);
start = (val >> 16) << 24;
end = (val & 0xFFFF);
end = end ? end + 1 : 0;
end = end << 24;
*size += end - start;
return 0; return 0;
} }
int dram_init(void)
{
phys_size_t sdram_size;
int ret;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
return 0;
}
int dram_init_banksize(void)
{
int bank = 0;
int ret;
phys_size_t sdram_size;
phys_size_t sdram_b1_size, sdram_b2_size;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
/* Bank 1 can't cross over 4GB space */
if (sdram_size > 0x80000000) {
sdram_b1_size = 0x80000000;
sdram_b2_size = sdram_size - 0x80000000;
} else {
sdram_b1_size = sdram_size;
sdram_b2_size = 0;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_b1_size - gd->bd->bi_dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_b1_size;
}
if (sdram_b2_size) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
gd->bd->bi_dram[bank].start = 0x100000000UL;
gd->bd->bi_dram[bank].size = sdram_b2_size;
}
return 0;
}
phys_size_t get_effective_memsize(void)
{
int ret;
phys_size_t sdram_size;
phys_size_t sdram_b1_size;
ret = board_phys_sdram_size(&sdram_size);
if (!ret) {
/* Bank 1 can't cross over 4GB space */
if (sdram_size > 0x80000000)
sdram_b1_size = 0x80000000;
else
sdram_b1_size = sdram_size;
if (rom_pointer[1]) {
/* We will relocate u-boot to top of dram1. TEE position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
* 2. In the middle of dram1, return the size of dram1.
*/
if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
}
return sdram_b1_size;
} else {
return PHYS_SDRAM_SIZE;
}
}
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{ {
mac[0] = 0x1; u32 val[2] = {};
mac[1] = 0x2; int ret;
mac[2] = 0x3;
mac[3] = 0x4; if (dev_id == 0) {
mac[4] = 0x5; ret = fuse_read(39, 3, &val[0]);
mac[5] = 0x6; if (ret)
goto err;
ret = fuse_read(39, 4, &val[1]);
if (ret)
goto err;
mac[0] = val[1] >> 8;
mac[1] = val[1];
mac[2] = val[0] >> 24;
mac[3] = val[0] >> 16;
mac[4] = val[0] >> 8;
mac[5] = val[0];
} else {
ret = fuse_read(39, 5, &val[0]);
if (ret)
goto err;
ret = fuse_read(39, 4, &val[1]);
if (ret)
goto err;
mac[0] = val[1] >> 24;
mac[1] = val[1] >> 16;
mac[2] = val[0] >> 24;
mac[3] = val[0] >> 16;
mac[4] = val[0] >> 8;
mac[5] = val[0];
}
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
__func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
return;
err:
memset(mac, 0, 6);
printf("%s: fuse read err: %d\n", __func__, ret);
} }
int print_cpuinfo(void) int print_cpuinfo(void)
@ -224,6 +523,18 @@ void get_board_serial(struct tag_serialnr *serialnr)
} }
#endif #endif
static void save_reset_cause(void)
{
struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE;
u32 srsr = readl(&src->srsr);
/* clear srsr in sec mode */
writel(srsr, &src->srsr);
/* Save value to GPR1 to pass to nonsecure */
writel(srsr, &src->gpr[0]);
}
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
if (IS_ENABLED(CONFIG_SPL_BUILD)) { if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@ -233,6 +544,9 @@ int arch_cpu_init(void)
clock_init(); clock_init();
trdc_early_init(); trdc_early_init();
/* Save SRC SRSR to GPR1 and clear it */
save_reset_cause();
} }
return 0; return 0;
@ -262,7 +576,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
return 0; return 0;
} }
EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu); EVENT_SPY(EVT_DM_POST_INIT_F, imx9_probe_mu);
int timer_init(void) int timer_init(void)
{ {
@ -466,3 +780,45 @@ int m33_prepare(void)
return 0; return 0;
} }
int psci_sysreset_get_status(struct udevice *dev, char *buf, int size)
{
static const char *reset_cause[] = {
"POR ",
"JTAG ",
"IPP USER ",
"WDOG1 ",
"WDOG2 ",
"WDOG3 ",
"WDOG4 ",
"WDOG5 ",
"TEMPSENSE ",
"CSU ",
"JTAG_SW ",
"M33_REQ ",
"M33_LOCKUP ",
"UNK ",
"UNK ",
"UNK "
};
struct src_general_regs *src = (struct src_general_regs *)SRC_GLOBAL_RBASE;
u32 srsr;
u32 i;
int res;
srsr = readl(&src->gpr[0]);
for (i = ARRAY_SIZE(reset_cause); i > 0; i--) {
if (srsr & (BIT(i - 1)))
break;
}
res = snprintf(buf, size, "Reset Status: %s\n", i ? reset_cause[i - 1] : "unknown reset");
if (res < 0) {
dev_err(dev, "Could not write reset status message (err = %d)\n", res);
return -EIO;
}
return 0;
}

2
arch/arm/mach-imx/parse-container.c
View file

@ -9,7 +9,7 @@
#include <spl.h> #include <spl.h>
#include <asm/mach-imx/image.h> #include <asm/mach-imx/image.h>
#ifdef CONFIG_AHAB_BOOT #ifdef CONFIG_AHAB_BOOT
#include <asm/arch/sci/sci.h> #include <firmware/imx/sci/sci.h>
#endif #endif
#define SEC_SECURE_RAM_BASE 0x31800000UL #define SEC_SECURE_RAM_BASE 0x31800000UL

2
arch/arm/mach-imx/spl_imx_romapi.c
View file

@ -367,7 +367,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
printf("USB boot\n"); printf("USB boot\n");
break; break;
default: default:
printf("Unknow (0x%x)\n", bstage); printf("Unknown (0x%x)\n", bstage);
} }
if (is_boot_from_stream_device(boot)) if (is_boot_from_stream_device(boot))

6
arch/arm/mach-k3/Kconfig
View file

@ -52,7 +52,8 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE config SYS_K3_MCU_SCRATCHPAD_BASE
hex hex
default 0x40280000 if SOC_K3_AM654 default 0x40280000 if SOC_K3_AM654
default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 default 0x40280000 if SOC_K3_J721S2
default 0x41cff9fc if SOC_K3_J721E
help help
Describes the base address of MCU Scratchpad RAM. Describes the base address of MCU Scratchpad RAM.
@ -140,8 +141,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
config K3_SYSFW_IMAGE_SIZE_MAX config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob" int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW depends on K3_LOAD_SYSFW
default 163840 if SOC_K3_AM625 || SOC_K3_AM62A7 default 280000
default 278000
help help
Amount of memory (in bytes) reserved through dynamic allocation at Amount of memory (in bytes) reserved through dynamic allocation at
runtime for loading the combined System Firmware and configuration image runtime for loading the combined System Firmware and configuration image

5
arch/arm/mach-k3/common.c
View file

@ -347,8 +347,13 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE)) if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE))
#endif #endif
{ {
ti_secure_image_check_binary(p_image, p_size);
ti_secure_image_post_process(p_image, p_size); ti_secure_image_post_process(p_image, p_size);
} }
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
else
ti_secure_image_check_binary(p_image, p_size);
#endif
} }
#endif #endif

1
arch/arm/mach-k3/common.h
View file

@ -44,3 +44,4 @@ enum k3_device_type get_device_type(void);
void ti_secure_image_post_process(void **p_image, size_t *p_size); void ti_secure_image_post_process(void **p_image, size_t *p_size);
struct ti_sci_handle *get_ti_sci_handle(void); struct ti_sci_handle *get_ti_sci_handle(void);
void do_board_detect(void); void do_board_detect(void);
void ti_secure_image_check_binary(void **p_image, size_t *p_size);

2
arch/arm/mach-k3/config.mk
View file

@ -68,6 +68,8 @@ ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
SPL_ITS := u-boot-spl-k3_HS.its SPL_ITS := u-boot-spl-k3_HS.its
$(SPL_ITS): export IS_HS=1 $(SPL_ITS): export IS_HS=1
INPUTS-y += tispl.bin_HS INPUTS-y += tispl.bin_HS
INPUTS-y += tispl.bin
tispl.bin: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(subst ",,$(CONFIG_SPL_OF_LIST)))
else else
SPL_ITS := u-boot-spl-k3.its SPL_ITS := u-boot-spl-k3.its
INPUTS-y += tispl.bin INPUTS-y += tispl.bin

32
arch/arm/mach-k3/security.c
View file

@ -38,19 +38,16 @@ static size_t ti_secure_cert_length(void *p_image)
return seq_length + 4; return seq_length + 4;
} }
void ti_secure_image_post_process(void **p_image, size_t *p_size) void ti_secure_image_check_binary(void **p_image, size_t *p_size)
{ {
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
size_t cert_length;
u64 image_addr;
u32 image_size; u32 image_size;
int ret; size_t cert_length;
image_size = *p_size; image_size = *p_size;
if (!image_size) if (!image_size) {
debug("%s: Image size is %d\n", __func__, image_size);
return; return;
}
if (get_device_type() == K3_DEVICE_TYPE_GP) { if (get_device_type() == K3_DEVICE_TYPE_GP) {
if (ti_secure_cert_detected(*p_image)) { if (ti_secure_cert_detected(*p_image)) {
@ -78,6 +75,25 @@ void ti_secure_image_post_process(void **p_image, size_t *p_size)
"This will fail on Security Enforcing(HS-SE) devices\n"); "This will fail on Security Enforcing(HS-SE) devices\n");
return; return;
} }
}
void ti_secure_image_post_process(void **p_image, size_t *p_size)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
u64 image_addr;
u32 image_size;
int ret;
image_size = *p_size;
if (!image_size) {
debug("%s: Image size is %d\n", __func__, image_size);
return;
}
if (get_device_type() != K3_DEVICE_TYPE_HS_SE &&
get_device_type() != K3_DEVICE_TYPE_HS_FS)
return;
/* Clean out image so it can be seen by system firmware */ /* Clean out image so it can be seen by system firmware */
image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL); image_addr = dma_map_single(*p_image, *p_size, DMA_BIDIRECTIONAL);

2
arch/arm/mach-mvebu/cpu.c
View file

@ -630,7 +630,7 @@ int board_xhci_enable(fdt_addr_t base)
{ {
const struct mbus_dram_target_info *dram; const struct mbus_dram_target_info *dram;
printf("MVEBU XHCI INIT controller @ 0x%lx\n", base); printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);
dram = mvebu_mbus_dram_info(); dram = mvebu_mbus_dram_info();
xhci_mvebu_mbus_config((void __iomem *)base, dram); xhci_mvebu_mbus_config((void __iomem *)base, dram);

4
arch/arm/mach-mvebu/system-controller.c
View file

@ -71,8 +71,8 @@ static int mvebu_reset_of_to_plat(struct udevice *dev)
{ {
struct mvebu_reset_data *data = dev_get_priv(dev); struct mvebu_reset_data *data = dev_get_priv(dev);
data->base = (void *)dev_read_addr(dev); data->base = dev_read_addr_ptr(dev);
if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE) if (!data->base)
return -EINVAL; return -EINVAL;
return 0; return 0;

2
arch/arm/mach-omap2/am33xx/board.c
View file

@ -535,4 +535,4 @@ static int am33xx_dm_post_init(void *ctx, struct event *event)
#endif #endif
return 0; return 0;
} }
EVENT_SPY(EVT_DM_POST_INIT, am33xx_dm_post_init); EVENT_SPY(EVT_DM_POST_INIT_F, am33xx_dm_post_init);

2
arch/arm/mach-omap2/hwinit-common.c
View file

@ -246,7 +246,7 @@ static int omap2_system_init(void *ctx, struct event *event)
return 0; return 0;
} }
EVENT_SPY(EVT_DM_POST_INIT, omap2_system_init); EVENT_SPY(EVT_DM_POST_INIT_F, omap2_system_init);
/* /*
* Routine: wait_for_command_complete * Routine: wait_for_command_complete

19
arch/arm/mach-rmobile/Kconfig
View file

@ -48,6 +48,24 @@ config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)" prompt "Renesas ARM SoCs RZ/A1 (32bit)"
select CPU_V7A select CPU_V7A
config RZN1
prompt "Renesas ARM SoCs RZ/N1 (32bit)"
select CPU_V7A
select ARMV7_SET_CORTEX_SMPEN if !SPL
select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
select CLK
select CLK_RENESAS
select CLK_R9A06G032
select DM
select DM_ETH
select DM_SERIAL
select PINCTRL
select PINCONF
select REGMAP
select SYSRESET
select SYSRESET_SYSCON
imply CMD_DM
endchoice endchoice
config SYS_SOC config SYS_SOC
@ -56,5 +74,6 @@ config SYS_SOC
source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1" source "arch/arm/mach-rmobile/Kconfig.rza1"
source "arch/arm/mach-rmobile/Kconfig.rzn1"
endif endif

20
arch/arm/mach-rmobile/Kconfig.rzn1 Normal file
View file

@ -0,0 +1,20 @@
if RZN1
choice
prompt "Renesas RZ/N1 Board select"
default TARGET_SCHNEIDER_RZN1
config TARGET_SCHNEIDER_RZN1
bool "Schneider RZN1 board"
help
Support the Schneider RZN1D and RZN1S boards, which are based
on the Renesas RZ/N1 SoC.
endchoice
config SYS_SOC
default "rzn1"
source "board/schneider/rzn1-snarc/Kconfig"
endif

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