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ARM: k2g: Add ddr3 info

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Add ddr3 related info

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Vitaly Andrianov 2015-09-19 16:26:43 +05:30 • committed by Tom Rini
parent 0fba27b690
commit 235dd6e8d1
6 changed files with 85 additions and 5 deletions
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12
arch/arm/mach-keystone/ddr3.c
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@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
if (!cpu_is_k2g())
__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
/* Disable ECC for K2G */
if (cpu_is_k2g()) {
clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
}
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;