mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-18 02:44:37 +00:00
mailbox: add i.MX Messaging Unit (MU) driver
This patch provides a driver for i.MX Messaging Unit (MU) using the
commom mailbox framework.
This is ported from Linux (v6.12.8) driver
drivers/mailbox/imx-mailbox.c. Its commit SHA is:
39d7d6177f0c ("mailbox: imx: use device name in interrupt name")
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Peng Fan
Fabio Estevam
parent
a1cd1ac79a
commit
21a4ac55c0
4 changed files with 452 additions and 0 deletions
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@ -315,6 +315,7 @@ F: board/freescale/*mx*/
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F: board/freescale/common/
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F: common/spl/spl_imx_container.c
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F: doc/imx/
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F: drivers/mailbox/imx-mailbox.c
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F: drivers/serial/serial_mxc.c
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F: include/imx_container.h
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@ -21,6 +21,13 @@ config APPLE_MBOX
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such as the System Management Controller (SMC) and NVMe and this
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driver is required to get that functionality up and running.
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config IMX_MU_MBOX
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bool "Enable i.MX MU MBOX support"
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depends on DM_MAILBOX
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help
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Enable support for i.MX Messaging Unit for communication with other
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processors on the SoC using mailbox interface
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config SANDBOX_MBOX
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bool "Enable the sandbox mailbox test driver"
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depends on DM_MAILBOX && SANDBOX
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@ -5,6 +5,7 @@
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obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
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obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
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obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
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obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
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obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
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443
drivers/mailbox/imx-mailbox.c
Normal file
443
drivers/mailbox/imx-mailbox.c
Normal file
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@ -0,0 +1,443 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <mailbox-uclass.h>
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#include <linux/bitfield.h>
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#include <linux/bug.h>
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#include <linux/iopoll.h>
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#include <linux/compat.h>
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/* This driver only exposes the status bits to keep with the
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* polling methodology of u-boot.
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*/
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DECLARE_GLOBAL_DATA_PTR;
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#define IMX_MU_CHANS 24
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#define IMX_MU_V2_PAR_OFF 0x4
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#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
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#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
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enum imx_mu_chan_type {
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IMX_MU_TYPE_TX = 0, /* Tx */
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IMX_MU_TYPE_RX = 1, /* Rx */
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IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
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IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
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IMX_MU_TYPE_RST = 4, /* Reset */
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IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
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};
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enum imx_mu_xcr {
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IMX_MU_CR,
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IMX_MU_GIER,
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IMX_MU_GCR,
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IMX_MU_TCR,
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IMX_MU_RCR,
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IMX_MU_xCR_MAX,
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};
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enum imx_mu_xsr {
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IMX_MU_SR,
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IMX_MU_GSR,
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IMX_MU_TSR,
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IMX_MU_RSR,
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IMX_MU_xSR_MAX,
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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enum imx_mu_chan_type type;
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struct mbox_chan *chan;
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};
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enum imx_mu_type {
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IMX_MU_V1,
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IMX_MU_V2 = BIT(1),
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IMX_MU_V2_S4 = BIT(15),
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IMX_MU_V2_IRQ = BIT(16),
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};
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struct imx_mu {
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void __iomem *base;
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const struct imx_mu_dcfg *dcfg;
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u32 num_tr;
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u32 num_rr;
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/* use pointers to channel as a way to reserve channels */
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struct mbox_chan *channels[IMX_MU_CHANS];
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
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};
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struct imx_mu_dcfg {
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int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void *data);
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int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
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int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
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int (*init)(struct imx_mu *plat);
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int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args *args);
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enum imx_mu_type type;
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u32 xTR; /* Transmit Register0 */
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u32 xRR; /* Receive Register0 */
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u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
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u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
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};
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#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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/* Transmit Interrupt Enable */
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#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Request */
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#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
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/* MU reset */
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#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5))
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#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7))
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static void imx_mu_write(struct imx_mu *plat, u32 val, u32 offs)
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{
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iowrite32(val, plat->base + offs);
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}
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static u32 imx_mu_read(struct imx_mu *plat, u32 offs)
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{
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return ioread32(plat->base + offs);
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}
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static u32 imx_mu_xcr_rmw(struct imx_mu *plat, enum imx_mu_xcr type, u32 set, u32 clr)
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{
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u32 val;
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val = imx_mu_read(plat, plat->dcfg->xCR[type]);
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val &= ~clr;
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val |= set;
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imx_mu_write(plat, val, plat->dcfg->xCR[type]);
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return val;
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}
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/* check that the channel is open or owned by caller */
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static int imx_mu_check_channel(struct mbox_chan *chan)
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{
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struct imx_mu *plat = dev_get_plat(chan->dev);
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if (plat->channels[chan->id]) {
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/* if reserved check that caller owns */
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if (plat->channels[chan->id] == chan)
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return 1; /* caller owns the channel */
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return -EACCES;
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}
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return 0; /* channel empty */
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}
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static int imx_mu_chan_request(struct mbox_chan *chan)
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{
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struct imx_mu *plat = dev_get_plat(chan->dev);
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struct imx_mu_con_priv *cp;
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enum imx_mu_chan_type type;
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int idx;
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type = chan->id / 4;
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idx = chan->id % 4;
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if (imx_mu_check_channel(chan) < 0) /* check if channel already in use */
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return -EPERM;
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plat->channels[chan->id] = chan;
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chan->con_priv = kcalloc(1, sizeof(struct imx_mu_con_priv), 0);
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if (!chan->con_priv)
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return -ENOMEM;
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cp = chan->con_priv;
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cp->idx = idx;
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cp->type = type;
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cp->chan = chan;
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switch (type) {
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case IMX_MU_TYPE_RX:
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imx_mu_xcr_rmw(plat, IMX_MU_RCR, IMX_MU_xCR_RIEn(plat->dcfg->type, idx), 0);
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break;
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case IMX_MU_TYPE_TXDB_V2:
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case IMX_MU_TYPE_TXDB:
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case IMX_MU_TYPE_RXDB:
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imx_mu_xcr_rmw(plat, IMX_MU_GIER, IMX_MU_xCR_GIEn(plat->dcfg->type, idx), 0);
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break;
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default:
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break;
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}
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return 0;
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}
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static int imx_mu_chan_free(struct mbox_chan *chan)
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{
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struct imx_mu *plat = dev_get_plat(chan->dev);
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struct imx_mu_con_priv *cp = chan->con_priv;
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if (imx_mu_check_channel(chan) <= 0) /* check that the channel is also not empty */
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return -EINVAL;
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/* if you own channel and channel is NOT empty */
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plat->channels[chan->id] = NULL;
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_xcr_rmw(plat, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(plat->dcfg->type, cp->idx));
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break;
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case IMX_MU_TYPE_RX:
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imx_mu_xcr_rmw(plat, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(plat->dcfg->type, cp->idx));
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break;
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case IMX_MU_TYPE_TXDB_V2:
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case IMX_MU_TYPE_TXDB:
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case IMX_MU_TYPE_RXDB:
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imx_mu_xcr_rmw(plat, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx));
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break;
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default:
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break;
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}
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kfree(cp);
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return 0;
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}
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static int imx_mu_send(struct mbox_chan *chan, const void *data)
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{
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struct imx_mu *plat = dev_get_plat(chan->dev);
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struct imx_mu_con_priv *cp = chan->con_priv;
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if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */
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return -EPERM;
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return plat->dcfg->tx(plat, cp, data);
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}
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static int imx_mu_recv(struct mbox_chan *chan, void *data)
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{
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struct imx_mu *plat = dev_get_plat(chan->dev);
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struct imx_mu_con_priv *cp = chan->con_priv;
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u32 ctrl, val;
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if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */
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return -EPERM;
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switch (cp->type) {
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case IMX_MU_TYPE_TXDB_V2:
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case IMX_MU_TYPE_RXDB:
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/* check if GSR[GIRn] bit is set */
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if (readx_poll_timeout(ioread32, plat->base + plat->dcfg->xSR[IMX_MU_GSR],
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val, val & BIT(cp->idx), 1000000) < 0)
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return -EBUSY;
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ctrl = imx_mu_read(plat, plat->dcfg->xCR[IMX_MU_GIER]);
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val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]);
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val &= IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx) &
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(ctrl & IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx));
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break;
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default:
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dev_warn(chan->dev, "Unhandled channel type %d\n", cp->type);
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return -EOPNOTSUPP;
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};
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if (val == IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx))
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plat->dcfg->rxdb(plat, cp);
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return 0;
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}
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static int imx_mu_of_to_plat(struct udevice *dev)
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{
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struct imx_mu *plat = dev_get_plat(dev);
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -ENODEV;
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plat->base = (struct mu_type *)addr;
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return 0;
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}
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static int imx_mu_init_generic(struct imx_mu *plat)
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{
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unsigned int i;
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unsigned int val;
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if (plat->num_rr > 4 || plat->num_tr > 4) {
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WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
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return -EOPNOTSUPP;
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}
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/* Set default MU configuration */
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for (i = 0; i < IMX_MU_xCR_MAX; i++)
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imx_mu_write(plat, 0, plat->dcfg->xCR[i]);
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/* Clear any pending GIP */
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val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]);
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imx_mu_write(plat, val, plat->dcfg->xSR[IMX_MU_GSR]);
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/* Clear any pending RSR */
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for (i = 0; i < plat->num_rr; i++)
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imx_mu_read(plat, plat->dcfg->xRR + i * 4);
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return 0;
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}
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static int imx_mu_generic_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args)
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{
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enum imx_mu_chan_type type;
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int idx, cid;
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if (args->args_count != 2) {
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dev_err(chan->dev, "Invalid argument count %d\n", args->args_count);
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return -EINVAL;
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}
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type = args->args[0]; /* channel type */
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idx = args->args[1]; /* index */
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cid = type * 4 + idx;
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if (cid >= IMX_MU_CHANS) {
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dev_err(chan->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n",
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cid, type, idx);
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return -EINVAL;
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}
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chan->id = cid;
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return 0;
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}
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static int imx_mu_generic_tx(struct imx_mu *plat, struct imx_mu_con_priv *cp,
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const void *data)
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{
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switch (cp->type) {
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case IMX_MU_TYPE_TXDB_V2:
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imx_mu_xcr_rmw(plat, IMX_MU_GCR, IMX_MU_xCR_GIRn(plat->dcfg->type, cp->idx), 0);
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break;
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default:
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dev_warn(cp->chan->dev, "Send data on wrong channel type: %d\n", cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_generic_rxdb(struct imx_mu *plat, struct imx_mu_con_priv *cp)
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{
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imx_mu_write(plat, IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx),
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plat->dcfg->xSR[IMX_MU_GSR]);
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return 0;
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}
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.tx = imx_mu_generic_tx,
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.rxdb = imx_mu_generic_rxdb,
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.init = imx_mu_init_generic,
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.of_xlate = imx_mu_generic_of_xlate,
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.type = IMX_MU_V1,
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.xTR = 0x0,
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.xRR = 0x10,
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.xSR = {0x20, 0x20, 0x20, 0x20},
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.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.tx = imx_mu_generic_tx,
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.rxdb = imx_mu_generic_rxdb,
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.init = imx_mu_init_generic,
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.of_xlate = imx_mu_generic_of_xlate,
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.type = IMX_MU_V1,
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.xTR = 0x20,
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.xRR = 0x40,
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.xSR = {0x60, 0x60, 0x60, 0x60},
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.xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx95 = {
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.tx = imx_mu_generic_tx,
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.rxdb = imx_mu_generic_rxdb,
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.init = imx_mu_init_generic,
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.of_xlate = imx_mu_generic_of_xlate,
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.type = IMX_MU_V2,
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.xTR = 0x200,
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.xRR = 0x280,
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.xSR = {0xC, 0x118, 0x124, 0x12C},
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.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
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};
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||||
static const struct udevice_id ids[] = {
|
||||
{ .compatible = "fsl,imx6sx-mu", .data = (ulong)&imx_mu_cfg_imx6sx },
|
||||
{ .compatible = "fsl,imx7ulp-mu", .data = (ulong)&imx_mu_cfg_imx7ulp },
|
||||
{ .compatible = "fsl,imx95-mu", .data = (ulong)&imx_mu_cfg_imx95 },
|
||||
{ }
|
||||
};
|
||||
|
||||
int imx_mu_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args)
|
||||
{
|
||||
struct imx_mu *plat = dev_get_plat(chan->dev);
|
||||
|
||||
return plat->dcfg->of_xlate(chan, args);
|
||||
}
|
||||
|
||||
struct mbox_ops imx_mu_ops = {
|
||||
.of_xlate = imx_mu_of_xlate,
|
||||
.request = imx_mu_chan_request,
|
||||
.rfree = imx_mu_chan_free,
|
||||
.send = imx_mu_send,
|
||||
.recv = imx_mu_recv,
|
||||
};
|
||||
|
||||
static void imx_mu_get_tr_rr(struct imx_mu *plat)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (plat->dcfg->type & IMX_MU_V2) {
|
||||
val = imx_mu_read(plat, IMX_MU_V2_PAR_OFF);
|
||||
plat->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
|
||||
plat->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
|
||||
} else {
|
||||
plat->num_tr = 4;
|
||||
plat->num_rr = 4;
|
||||
}
|
||||
}
|
||||
|
||||
static int imx_mu_probe(struct udevice *dev)
|
||||
{
|
||||
struct imx_mu *plat = dev_get_plat(dev);
|
||||
int ret;
|
||||
|
||||
debug("%s(dev=%p)\n", __func__, dev);
|
||||
|
||||
plat->dcfg = (void *)dev_get_driver_data(dev);
|
||||
|
||||
imx_mu_get_tr_rr(plat);
|
||||
|
||||
ret = plat->dcfg->init(plat);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to init MU\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(imx_mu) = {
|
||||
.name = "imx-mu",
|
||||
.id = UCLASS_MAILBOX,
|
||||
.of_match = ids,
|
||||
.of_to_plat = imx_mu_of_to_plat,
|
||||
.plat_auto = sizeof(struct imx_mu),
|
||||
.probe = imx_mu_probe,
|
||||
.ops = &imx_mu_ops,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue