mirror of
https://github.com/u-boot/u-boot.git
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Merge patch series "Introduce basic support for TI's AM62Px SoC family"
Bryan Brattlof <bb@ti.com> says: Hello Again Everyone! The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Proof-of-Life: https://paste.sr.ht/~bryanb/af2ac108a9362549aa326f182e87918d52bf2d71
This commit is contained in:
Tom Rini
commit
213ffd49bd
48 changed files with 7325 additions and 14 deletions
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@ -1437,6 +1437,8 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
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dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
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dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \
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k3-am62a7-r5-sk.dtb
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k3-am62a7-r5-sk.dtb
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dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-rfb.dtb \
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mt7622-rfb.dtb \
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mt7623a-unielec-u7623-02-emmc.dtb \
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mt7623a-unielec-u7623-02-emmc.dtb \
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2800
arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
Normal file
2800
arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
Normal file
File diff suppressed because it is too large
Load diff
173
arch/arm/dts/k3-am62p-sk-binman.dtsi
Normal file
173
arch/arm/dts/k3-am62p-sk-binman.dtsi
Normal file
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@ -0,0 +1,173 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-binman.dtsi"
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#if IS_ENABLED(CONFIG_TARGET_AM62P5_R5_EVM)
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&binman {
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tiboot3-am62px-hs-fs-evm.bin {
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filename = "tiboot3-am62px-hs-fs-evm.bin";
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symlink = "tiboot3.bin";
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ti-secure-rom {
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content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
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<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
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combined;
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dm-data;
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sysfw-inner-cert;
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keyfile = "custMpk.pem";
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sw-rev = <1>;
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content-sbl = <&u_boot_spl_fs>;
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content-sysfw = <&ti_fs_enc_fs>;
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content-sysfw-data = <&combined_tifs_cfg_fs>;
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content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
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content-dm-data = <&combined_dm_cfg_fs>;
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load = <0x43c00000>;
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load-sysfw = <0x40000>;
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load-sysfw-data = <0x67000>;
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load-dm-data = <0x43c4a800>;
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};
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u_boot_spl_fs: u-boot-spl {
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no-expanded;
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};
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ti_fs_enc_fs: ti-fs-enc.bin {
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filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin";
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type = "blob-ext";
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optional;
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};
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combined_tifs_cfg_fs: combined-tifs-cfg.bin {
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filename = "combined-tifs-cfg.bin";
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type = "blob-ext";
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};
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sysfw_inner_cert_fs: sysfw-inner-cert {
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filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin";
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type = "blob-ext";
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optional;
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};
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combined_dm_cfg_fs: combined-dm-cfg.bin {
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filename = "combined-dm-cfg.bin";
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type = "blob-ext";
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};
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};
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};
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#endif /* CONFIG_TARGET_AM62P5_R5_EVM */
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#if IS_ENABLED(CONFIG_TARGET_AM62P5_A53_EVM)
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#define SPL_AM62PX_SK_DTB "spl/dts/ti/k3-am62p5-sk.dtb"
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#define AM62PX_SK_DTB "u-boot.dtb"
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&binman {
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ti-dm {
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filename = "ti-dm.bin";
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blob-ext {
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filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
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};
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};
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ti-spl {
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insert-template = <&ti_spl_template>;
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fit {
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images {
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dm {
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ti-secure {
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content = <&dm>;
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keyfile = "custMpk.pem";
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};
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dm: ti-dm {
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filename = "ti-dm.bin";
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};
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};
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fdt-0 {
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description = "k3-am62p5-sk";
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type = "flat_dt";
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arch = "arm";
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compression = "none";
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ti-secure {
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content = <&spl_am62p5_sk_dtb>;
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keyfile = "custMpk.pem";
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};
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spl_am62p5_sk_dtb: blob-ext {
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filename = SPL_AM62PX_SK_DTB;
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};
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};
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};
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configurations {
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default = "conf-0";
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conf-0 {
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description = "k3-am62px-sk";
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firmware = "atf";
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loadables = "tee", "dm", "spl";
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fdt = "fdt-0";
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};
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};
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};
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};
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};
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&binman {
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u-boot {
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insert-template = <&u_boot_template>;
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fit {
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images {
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uboot {
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description = "U-Boot for AM62P5 Boards";
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};
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fdt-0 {
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description = "k3-am62px-sk";
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type = "flat_dt";
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arch = "arm";
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compression = "none";
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ti-secure {
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content = <&am62px_sk_dtb>;
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keyfile = "custMpk.pem";
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};
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am62px_sk_dtb: blob-ext {
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filename = AM62PX_SK_DTB;
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};
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hash {
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algo = "crc32";
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};
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};
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};
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configurations {
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default = "conf-0";
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conf-0 {
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description = "k3-am62px-sk";
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firmware = "uboot";
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loadables = "uboot";
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fdt = "fdt-0";
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};
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};
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};
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};
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};
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#endif /* CONFIG_TARGET_AM62P5_A53_EVM */
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101
arch/arm/dts/k3-am62p5-r5-sk.dts
Normal file
101
arch/arm/dts/k3-am62p5-r5-sk.dts
Normal file
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@ -0,0 +1,101 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* AM62P5 SK dts file for R5 SPL
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* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am62p5-sk.dts"
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#include "k3-am62p5-sk-u-boot.dtsi"
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#include "k3-am62p-ddr-lp4-50-1600.dtsi"
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#include "k3-am62a-ddr.dtsi"
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/ {
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a53_0;
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serial0 = &wkup_uart0;
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serial2 = &main_uart0;
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serial3 = &main_uart1;
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};
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a53_0: a53@0 {
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compatible = "ti,am654-rproc";
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reg = <0x00 0x00a90000 0x00 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 135 0>;
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clocks = <&k3_clks 61 0>;
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assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
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assigned-clock-parents = <&k3_clks 61 2>;
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assigned-clock-rates = <200000000>, <1200000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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bootph-all;
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};
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dm_tifs: dm-tifs {
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compatible = "ti,j721e-dm-sci";
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ti,host-id = <36>;
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ti,secure-host;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 20>,
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<&secure_proxy_main 21>;
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bootph-all;
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};
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};
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&dmsc {
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mboxes= <&secure_proxy_main 0>,
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<&secure_proxy_main 1>,
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<&secure_proxy_main 0>;
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mbox-names = "rx", "tx", "notify";
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ti,host-id = <35>;
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ti,secure-host;
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};
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&cbass_main {
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sa3_secproxy: secproxy@44880000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg = <0x00 0x44880000 0x00 0x20000>,
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<0x00 0x44860000 0x00 0x20000>,
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<0x00 0x43600000 0x00 0x10000>;
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reg-names = "rt", "scfg", "target_data";
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bootph-all;
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};
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sysctrler: sysctrler {
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compatible = "ti,am654-system-controller";
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mboxes= <&secure_proxy_main 1>,
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<&secure_proxy_main 0>,
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<&sa3_secproxy 0>;
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mbox-names = "tx", "rx", "boot_notify";
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bootph-all;
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};
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};
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/* WKUP UART0 is used for DM firmware logs */
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&wkup_uart0 {
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status = "okay";
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};
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|
||||||
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/* Main UART1 is used for TIFS firmware logs */
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&main_uart1 {
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status = "okay";
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};
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|
|
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|
&main_pktdma {
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ti,sci = <&dm_tifs>;
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|
};
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|
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|
&main_bcdma {
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ti,sci = <&dm_tifs>;
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};
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&ospi0 {
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reg = <0x00 0x0fc40000 0x00 0x100>,
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<0x00 0x60000000 0x00 0x08000000>;
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};
|
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23
arch/arm/dts/k3-am62p5-sk-u-boot.dtsi
Normal file
23
arch/arm/dts/k3-am62p5-sk-u-boot.dtsi
Normal file
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|
@ -0,0 +1,23 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
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|
/*
|
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* Common AM62Px EVM dts file for SPLs
|
||||||
|
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "k3-am62p-sk-binman.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
tick-timer = &main_timer0;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&dmsc {
|
||||||
|
bootph-pre-ram;
|
||||||
|
|
||||||
|
k3_sysreset: sysreset-controller {
|
||||||
|
compatible = "ti,sci-sysreset";
|
||||||
|
bootph-pre-ram;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -10,6 +10,9 @@ config SOC_K3_AM625
|
||||||
config SOC_K3_AM62A7
|
config SOC_K3_AM62A7
|
||||||
bool "TI's K3 based AM62A7 SoC Family Support"
|
bool "TI's K3 based AM62A7 SoC Family Support"
|
||||||
|
|
||||||
|
config SOC_K3_AM62P5
|
||||||
|
bool "TI's K3 based AM62P5 SoC Family Support"
|
||||||
|
|
||||||
config SOC_K3_AM642
|
config SOC_K3_AM642
|
||||||
bool "TI's K3 based AM642 SoC Family Support"
|
bool "TI's K3 based AM642 SoC Family Support"
|
||||||
|
|
||||||
|
|
@ -80,6 +83,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
|
||||||
default 0x43c3f290 if SOC_K3_AM625
|
default 0x43c3f290 if SOC_K3_AM625
|
||||||
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
|
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
|
||||||
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
|
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
|
||||||
|
default 0x43c4f290 if SOC_K3_AM62P5
|
||||||
help
|
help
|
||||||
Address at which ROM stores the value which determines if SPL
|
Address at which ROM stores the value which determines if SPL
|
||||||
is booted up by primary boot media or secondary boot media.
|
is booted up by primary boot media or secondary boot media.
|
||||||
|
|
@ -118,7 +122,7 @@ config K3_EARLY_CONS_IDX
|
||||||
|
|
||||||
config K3_ATF_LOAD_ADDR
|
config K3_ATF_LOAD_ADDR
|
||||||
hex "Load address of ATF image"
|
hex "Load address of ATF image"
|
||||||
default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7)
|
default 0x80000000 if (SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_AM62P5)
|
||||||
default 0x70000000
|
default 0x70000000
|
||||||
help
|
help
|
||||||
The load address for the ATF image. This value is used to build the
|
The load address for the ATF image. This value is used to build the
|
||||||
|
|
@ -133,7 +137,7 @@ config K3_OPTEE_LOAD_ADDR
|
||||||
|
|
||||||
config K3_DM_FW
|
config K3_DM_FW
|
||||||
bool "Separate DM firmware image"
|
bool "Separate DM firmware image"
|
||||||
depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_J784S4) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
|
depends on CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
|
||||||
default y
|
default y
|
||||||
help
|
help
|
||||||
Enabling this will indicate that the system has separate DM
|
Enabling this will indicate that the system has separate DM
|
||||||
|
|
@ -156,6 +160,7 @@ source "arch/arm/mach-k3/am65x/Kconfig"
|
||||||
source "arch/arm/mach-k3/am64x/Kconfig"
|
source "arch/arm/mach-k3/am64x/Kconfig"
|
||||||
source "arch/arm/mach-k3/am62x/Kconfig"
|
source "arch/arm/mach-k3/am62x/Kconfig"
|
||||||
source "arch/arm/mach-k3/am62ax/Kconfig"
|
source "arch/arm/mach-k3/am62ax/Kconfig"
|
||||||
|
source "arch/arm/mach-k3/am62px/Kconfig"
|
||||||
source "arch/arm/mach-k3/j721e/Kconfig"
|
source "arch/arm/mach-k3/j721e/Kconfig"
|
||||||
source "arch/arm/mach-k3/j721s2/Kconfig"
|
source "arch/arm/mach-k3/j721s2/Kconfig"
|
||||||
source "arch/arm/mach-k3/j784s4/Kconfig"
|
source "arch/arm/mach-k3/j784s4/Kconfig"
|
||||||
|
|
|
||||||
|
|
@ -22,5 +22,6 @@ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
|
||||||
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
|
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
|
||||||
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
|
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
|
||||||
obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
|
obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
|
||||||
|
obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o
|
||||||
endif
|
endif
|
||||||
obj-y += common.o security.o
|
obj-y += common.o security.o
|
||||||
|
|
|
||||||
281
arch/arm/mach-k3/am62p5_init.c
Normal file
281
arch/arm/mach-k3/am62p5_init.c
Normal file
|
|
@ -0,0 +1,281 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* AM62P5: SoC specific initialization
|
||||||
|
*
|
||||||
|
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <spl.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/hardware.h>
|
||||||
|
#include "sysfw-loader.h"
|
||||||
|
#include "common.h"
|
||||||
|
#include <dm.h>
|
||||||
|
#include <dm/uclass-internal.h>
|
||||||
|
#include <dm/pinctrl.h>
|
||||||
|
|
||||||
|
struct fwl_data cbass_main_fwls[] = {
|
||||||
|
{ "FSS_DAT_REG3", 7, 8 },
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This uninitialized global variable would normal end up in the .bss section,
|
||||||
|
* but the .bss is cleared between writing and reading this variable, so move
|
||||||
|
* it to the .data section.
|
||||||
|
*/
|
||||||
|
u32 bootindex __section(".data");
|
||||||
|
static struct rom_extended_boot_data bootdata __section(".data");
|
||||||
|
|
||||||
|
static void store_boot_info_from_rom(void)
|
||||||
|
{
|
||||||
|
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
||||||
|
memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
|
||||||
|
sizeof(struct rom_extended_boot_data));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void ctrl_mmr_unlock(void)
|
||||||
|
{
|
||||||
|
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
|
||||||
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
|
||||||
|
|
||||||
|
/* Unlock all CTRL_MMR0 module registers */
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 0);
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 1);
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 2);
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 4);
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 5);
|
||||||
|
mmr_unlock(CTRL_MMR0_BASE, 6);
|
||||||
|
|
||||||
|
/* Unlock all MCU_CTRL_MMR0 module registers */
|
||||||
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
|
||||||
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
|
||||||
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
|
||||||
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
|
||||||
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
|
||||||
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
|
||||||
|
|
||||||
|
/* Unlock PADCFG_CTRL_MMR padconf registers */
|
||||||
|
mmr_unlock(PADCFG_MMR0_BASE, 1);
|
||||||
|
mmr_unlock(PADCFG_MMR1_BASE, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void board_init_f(ulong dummy)
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_CPU_V7R))
|
||||||
|
setup_k3_mpu_regions();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Cannot delay this further as there is a chance that
|
||||||
|
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
||||||
|
*/
|
||||||
|
store_boot_info_from_rom();
|
||||||
|
|
||||||
|
ctrl_mmr_unlock();
|
||||||
|
|
||||||
|
/* Init DM early */
|
||||||
|
ret = spl_early_init();
|
||||||
|
if (ret)
|
||||||
|
panic("spl_early_init() failed: %d\n", ret);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and
|
||||||
|
* MAIN_UART1 modules and continue regardless of the result of pinctrl.
|
||||||
|
* Do this without probing the device, but instead by searching the
|
||||||
|
* device that would request the given sequence number if probed. The
|
||||||
|
* UARTs will be used by the DM firmware and TIFS firmware images
|
||||||
|
* respectively and the firmware depend on SPL to initialize the pin
|
||||||
|
* settings.
|
||||||
|
*/
|
||||||
|
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
|
||||||
|
if (!ret)
|
||||||
|
pinctrl_select_state(dev, "default");
|
||||||
|
|
||||||
|
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
|
||||||
|
if (!ret)
|
||||||
|
pinctrl_select_state(dev, "default");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Allow establishing an early console as required for example when
|
||||||
|
* doing a UART-based boot. Note that this console may not "survive"
|
||||||
|
* through a SYSFW PM-init step and will need a re-init in some way
|
||||||
|
* due to changing module clock frequencies.
|
||||||
|
*/
|
||||||
|
if (IS_ENABLED(CONFIG_K3_EARLY_CONS)) {
|
||||||
|
ret = early_console_init();
|
||||||
|
if (ret)
|
||||||
|
panic("early_console_init() failed: %d\n", ret);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure and start up system controller firmware. Provide
|
||||||
|
* the U-Boot console init function to the SYSFW post-PM configuration
|
||||||
|
* callback hook, effectively switching on (or over) the console
|
||||||
|
* output.
|
||||||
|
*/
|
||||||
|
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
|
||||||
|
ret = is_rom_loaded_sysfw(&bootdata);
|
||||||
|
if (!ret)
|
||||||
|
panic("ROM has not loaded TIFS firmware\n");
|
||||||
|
|
||||||
|
k3_sysfw_loader(true, NULL, NULL);
|
||||||
|
|
||||||
|
/* Disable ROM configured firewalls */
|
||||||
|
remove_fwl_configs(cbass_main_fwls,
|
||||||
|
ARRAY_SIZE(cbass_main_fwls));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Force probe of clk_k3 driver here to ensure basic default clock
|
||||||
|
* configuration is always done.
|
||||||
|
*/
|
||||||
|
if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
|
||||||
|
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||||
|
DM_DRIVER_GET(ti_clk),
|
||||||
|
&dev);
|
||||||
|
if (ret)
|
||||||
|
printf("Failed to initialize clk-k3!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
preloader_console_init();
|
||||||
|
|
||||||
|
/* Output System Firmware version info */
|
||||||
|
k3_sysfw_print_ver();
|
||||||
|
|
||||||
|
if (IS_ENABLED(CONFIG_K3_AM62A_DDRSS)) {
|
||||||
|
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||||
|
if (ret)
|
||||||
|
panic("DRAM init failed: %d\n", ret);
|
||||||
|
}
|
||||||
|
|
||||||
|
spl_enable_cache();
|
||||||
|
debug("am62px_init: %s done\n", __func__);
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
|
||||||
|
{
|
||||||
|
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
||||||
|
u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
||||||
|
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
|
||||||
|
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||||
|
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||||
|
|
||||||
|
switch (bootmode) {
|
||||||
|
case BOOT_DEVICE_EMMC:
|
||||||
|
return MMCSD_MODE_EMMCBOOT;
|
||||||
|
case BOOT_DEVICE_MMC:
|
||||||
|
if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)
|
||||||
|
return MMCSD_MODE_RAW;
|
||||||
|
default:
|
||||||
|
return MMCSD_MODE_FS;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 __get_backup_bootmedia(u32 devstat)
|
||||||
|
{
|
||||||
|
u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
|
||||||
|
MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
|
||||||
|
u32 bkup_bootmode_cfg =
|
||||||
|
(devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
|
||||||
|
MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
|
||||||
|
|
||||||
|
switch (bkup_bootmode) {
|
||||||
|
case BACKUP_BOOT_DEVICE_UART:
|
||||||
|
return BOOT_DEVICE_UART;
|
||||||
|
|
||||||
|
case BACKUP_BOOT_DEVICE_USB:
|
||||||
|
return BOOT_DEVICE_USB;
|
||||||
|
|
||||||
|
case BACKUP_BOOT_DEVICE_ETHERNET:
|
||||||
|
return BOOT_DEVICE_ETHERNET;
|
||||||
|
|
||||||
|
case BACKUP_BOOT_DEVICE_MMC:
|
||||||
|
if (bkup_bootmode_cfg)
|
||||||
|
return BOOT_DEVICE_MMC2;
|
||||||
|
return BOOT_DEVICE_MMC1;
|
||||||
|
|
||||||
|
case BACKUP_BOOT_DEVICE_SPI:
|
||||||
|
return BOOT_DEVICE_SPI;
|
||||||
|
|
||||||
|
case BACKUP_BOOT_DEVICE_I2C:
|
||||||
|
return BOOT_DEVICE_I2C;
|
||||||
|
|
||||||
|
case BACKUP_BOOT_DEVICE_DFU:
|
||||||
|
if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
|
||||||
|
return BOOT_DEVICE_USB;
|
||||||
|
return BOOT_DEVICE_DFU;
|
||||||
|
};
|
||||||
|
|
||||||
|
return BOOT_DEVICE_RAM;
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 __get_primary_bootmedia(u32 devstat)
|
||||||
|
{
|
||||||
|
u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
||||||
|
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
|
||||||
|
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
|
||||||
|
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
|
||||||
|
|
||||||
|
switch (bootmode) {
|
||||||
|
case BOOT_DEVICE_OSPI:
|
||||||
|
fallthrough;
|
||||||
|
case BOOT_DEVICE_QSPI:
|
||||||
|
fallthrough;
|
||||||
|
case BOOT_DEVICE_XSPI:
|
||||||
|
fallthrough;
|
||||||
|
case BOOT_DEVICE_SPI:
|
||||||
|
return BOOT_DEVICE_SPI;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_ETHERNET_RGMII:
|
||||||
|
fallthrough;
|
||||||
|
case BOOT_DEVICE_ETHERNET_RMII:
|
||||||
|
return BOOT_DEVICE_ETHERNET;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_EMMC:
|
||||||
|
return BOOT_DEVICE_MMC1;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_SPI_NAND:
|
||||||
|
return BOOT_DEVICE_SPINAND;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_MMC:
|
||||||
|
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
|
||||||
|
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
|
||||||
|
return BOOT_DEVICE_MMC2;
|
||||||
|
return BOOT_DEVICE_MMC1;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_DFU:
|
||||||
|
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
|
||||||
|
MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
|
||||||
|
return BOOT_DEVICE_USB;
|
||||||
|
return BOOT_DEVICE_DFU;
|
||||||
|
|
||||||
|
case BOOT_DEVICE_NOBOOT:
|
||||||
|
return BOOT_DEVICE_RAM;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bootmode;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32 spl_boot_device(void)
|
||||||
|
{
|
||||||
|
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
||||||
|
u32 bootmedia;
|
||||||
|
|
||||||
|
if (bootindex == K3_PRIMARY_BOOTMODE)
|
||||||
|
bootmedia = __get_primary_bootmedia(devstat);
|
||||||
|
else
|
||||||
|
bootmedia = __get_backup_bootmedia(devstat);
|
||||||
|
|
||||||
|
debug("am62px_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n",
|
||||||
|
__func__, devstat, bootmedia, bootindex);
|
||||||
|
return bootmedia;
|
||||||
|
}
|
||||||
32
arch/arm/mach-k3/am62px/Kconfig
Normal file
32
arch/arm/mach-k3/am62px/Kconfig
Normal file
|
|
@ -0,0 +1,32 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
|
||||||
|
if SOC_K3_AM62P5
|
||||||
|
|
||||||
|
choice
|
||||||
|
prompt "TI K3 AM62Px based boards"
|
||||||
|
optional
|
||||||
|
|
||||||
|
config TARGET_AM62P5_A53_EVM
|
||||||
|
bool "TI K3 based AM62P5 EVM running on A53"
|
||||||
|
select ARM64
|
||||||
|
select BINMAN
|
||||||
|
|
||||||
|
config TARGET_AM62P5_R5_EVM
|
||||||
|
bool "TI K3 based AM62P5 EVM running on R5"
|
||||||
|
select CPU_V7R
|
||||||
|
select SYS_THUMB_BUILD
|
||||||
|
select K3_LOAD_SYSFW
|
||||||
|
select RAM
|
||||||
|
select SPL_RAM
|
||||||
|
select K3_DDRSS
|
||||||
|
select BINMAN
|
||||||
|
imply SYS_K3_SPL_ATF
|
||||||
|
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
source "board/ti/am62px/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
83
arch/arm/mach-k3/include/mach/am62p_hardware.h
Normal file
83
arch/arm/mach-k3/include/mach/am62p_hardware.h
Normal file
|
|
@ -0,0 +1,83 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* K3: AM62Px SoC definitions, structures etc.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM_ARCH_AM62P_HARDWARE_H
|
||||||
|
#define __ASM_ARCH_AM62P_HARDWARE_H
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
#include <linux/bitops.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define PADCFG_MMR0_BASE 0x04080000
|
||||||
|
#define PADCFG_MMR1_BASE 0x000f0000
|
||||||
|
#define CTRL_MMR0_BASE 0x00100000
|
||||||
|
#define MCU_CTRL_MMR0_BASE 0x04500000
|
||||||
|
#define WKUP_CTRL_MMR0_BASE 0x43000000
|
||||||
|
|
||||||
|
#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3)
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7)
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
|
||||||
|
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10)
|
||||||
|
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
|
||||||
|
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13)
|
||||||
|
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
|
||||||
|
|
||||||
|
/* Primary Bootmode MMC Config macros */
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0
|
||||||
|
|
||||||
|
/* Primary Bootmode USB Config macros */
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
|
||||||
|
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
|
||||||
|
|
||||||
|
/* Backup Bootmode USB Config macros */
|
||||||
|
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CTRL_MMR0 memory space is divided into several equally-spaced
|
||||||
|
* partitions, so defining the partition size allows us to determine
|
||||||
|
* register addresses common to those partitions.
|
||||||
|
*/
|
||||||
|
#define CTRL_MMR0_PARTITION_SIZE 0x4000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
|
||||||
|
* shared register definitions. The same registers are also used for
|
||||||
|
* PADCFG_MMR lock/kick-mechanism.
|
||||||
|
*/
|
||||||
|
#define CTRLMMR_LOCK_KICK0 0x1008
|
||||||
|
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
|
||||||
|
#define CTRLMMR_LOCK_KICK1 0x100c
|
||||||
|
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
|
||||||
|
|
||||||
|
#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038)
|
||||||
|
#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c)
|
||||||
|
#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7)
|
||||||
|
|
||||||
|
#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058)
|
||||||
|
#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3)
|
||||||
|
|
||||||
|
#define ROM_EXTENDED_BOOT_DATA_INFO 0x43c4f1e0
|
||||||
|
|
||||||
|
#define K3_BOOT_PARAM_TABLE_INDEX_OCRAM 0x7000F290
|
||||||
|
|
||||||
|
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__)
|
||||||
|
|
||||||
|
static const u32 put_device_ids[] = {};
|
||||||
|
|
||||||
|
static const u32 put_core_ids[] = {};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASM_ARCH_AM62P_HARDWARE_H */
|
||||||
49
arch/arm/mach-k3/include/mach/am62p_spl.h
Normal file
49
arch/arm/mach-k3/include/mach/am62p_spl.h
Normal file
|
|
@ -0,0 +1,49 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _ASM_ARCH_AM62P_SPL_H_
|
||||||
|
#define _ASM_ARCH_AM62P_SPL_H_
|
||||||
|
|
||||||
|
/* Primary BootMode devices */
|
||||||
|
#define BOOT_DEVICE_SPI_NAND 0x00
|
||||||
|
#define BOOT_DEVICE_RAM 0xFF
|
||||||
|
#define BOOT_DEVICE_OSPI 0x01
|
||||||
|
#define BOOT_DEVICE_QSPI 0x02
|
||||||
|
#define BOOT_DEVICE_SPI 0x03
|
||||||
|
#define BOOT_DEVICE_CPGMAC 0x04
|
||||||
|
#define BOOT_DEVICE_ETHERNET_RGMII 0x04
|
||||||
|
#define BOOT_DEVICE_ETHERNET_RMII 0x05
|
||||||
|
#define BOOT_DEVICE_I2C 0x06
|
||||||
|
#define BOOT_DEVICE_UART 0x07
|
||||||
|
#define BOOT_DEVICE_MMC 0x08
|
||||||
|
#define BOOT_DEVICE_EMMC 0x09
|
||||||
|
|
||||||
|
#define BOOT_DEVICE_USB 0x2A
|
||||||
|
#define BOOT_DEVICE_DFU 0x0A
|
||||||
|
#define BOOT_DEVICE_GPMC_NAND 0x0B
|
||||||
|
#define BOOT_DEVICE_GPMC_NOR 0x0C
|
||||||
|
#define BOOT_DEVICE_XSPI 0x0E
|
||||||
|
#define BOOT_DEVICE_NOBOOT 0x0F
|
||||||
|
|
||||||
|
/* U-Boot used aliases */
|
||||||
|
#define BOOT_DEVICE_ETHERNET 0x04
|
||||||
|
#define BOOT_DEVICE_SPINAND 0x10
|
||||||
|
#define BOOT_DEVICE_MMC2 0x08
|
||||||
|
#define BOOT_DEVICE_MMC1 0x09
|
||||||
|
/* Invalid */
|
||||||
|
#define BOOT_DEVICE_MMC2_2 0x1F
|
||||||
|
|
||||||
|
/* Backup BootMode devices */
|
||||||
|
#define BACKUP_BOOT_DEVICE_DFU 0x01
|
||||||
|
#define BACKUP_BOOT_DEVICE_UART 0x03
|
||||||
|
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
|
||||||
|
#define BACKUP_BOOT_DEVICE_MMC 0x05
|
||||||
|
#define BACKUP_BOOT_DEVICE_SPI 0x06
|
||||||
|
#define BACKUP_BOOT_DEVICE_I2C 0x07
|
||||||
|
#define BACKUP_BOOT_DEVICE_USB 0x09
|
||||||
|
|
||||||
|
#define K3_PRIMARY_BOOTMODE 0x0
|
||||||
|
|
||||||
|
#endif /* _ASM_ARCH_AM62P_SPL_H_ */
|
||||||
|
|
@ -36,6 +36,10 @@
|
||||||
#include "j784s4_hardware.h"
|
#include "j784s4_hardware.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOC_K3_AM62P5
|
||||||
|
#include "am62p_hardware.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Assuming these addresses and definitions stay common across K3 devices */
|
/* Assuming these addresses and definitions stay common across K3 devices */
|
||||||
#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
|
#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
|
||||||
#define JTAG_ID_VARIANT_SHIFT 28
|
#define JTAG_ID_VARIANT_SHIFT 28
|
||||||
|
|
@ -43,6 +47,7 @@
|
||||||
#define JTAG_ID_PARTNO_SHIFT 12
|
#define JTAG_ID_PARTNO_SHIFT 12
|
||||||
#define JTAG_ID_PARTNO_MASK (0xffff << 12)
|
#define JTAG_ID_PARTNO_MASK (0xffff << 12)
|
||||||
#define JTAG_ID_PARTNO_AM62AX 0xbb8d
|
#define JTAG_ID_PARTNO_AM62AX 0xbb8d
|
||||||
|
#define JTAG_ID_PARTNO_AM62PX 0xbb9d
|
||||||
#define JTAG_ID_PARTNO_AM62X 0xbb7e
|
#define JTAG_ID_PARTNO_AM62X 0xbb7e
|
||||||
#define JTAG_ID_PARTNO_AM64X 0xbb38
|
#define JTAG_ID_PARTNO_AM64X 0xbb38
|
||||||
#define JTAG_ID_PARTNO_AM65X 0xbb5a
|
#define JTAG_ID_PARTNO_AM65X 0xbb5a
|
||||||
|
|
@ -65,6 +70,7 @@ K3_SOC_ID(am64x, AM64X)
|
||||||
K3_SOC_ID(j721s2, J721S2)
|
K3_SOC_ID(j721s2, J721S2)
|
||||||
K3_SOC_ID(am62x, AM62X)
|
K3_SOC_ID(am62x, AM62X)
|
||||||
K3_SOC_ID(am62ax, AM62AX)
|
K3_SOC_ID(am62ax, AM62AX)
|
||||||
|
K3_SOC_ID(am62px, AM62PX)
|
||||||
|
|
||||||
#define K3_SEC_MGR_SYS_STATUS 0x44234100
|
#define K3_SEC_MGR_SYS_STATUS 0x44234100
|
||||||
#define SYS_STATUS_DEV_TYPE_SHIFT 0
|
#define SYS_STATUS_DEV_TYPE_SHIFT 0
|
||||||
|
|
|
||||||
|
|
@ -34,4 +34,8 @@
|
||||||
#include "j784s4_spl.h"
|
#include "j784s4_spl.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOC_K3_AM62P5
|
||||||
|
#include "am62p_spl.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* _ASM_ARCH_SPL_H_ */
|
#endif /* _ASM_ARCH_SPL_H_ */
|
||||||
|
|
|
||||||
|
|
@ -9,6 +9,7 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
|
||||||
obj-$(CONFIG_SOC_K3_AM625) += am62x/
|
obj-$(CONFIG_SOC_K3_AM625) += am62x/
|
||||||
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
|
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
|
||||||
obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
|
obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
|
||||||
|
obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
|
||||||
|
|
||||||
obj-y += common.o
|
obj-y += common.o
|
||||||
obj-y += lowlevel_init.o
|
obj-y += lowlevel_init.o
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
|
||||||
|
|
|
||||||
6
arch/arm/mach-k3/r5/am62px/Makefile
Normal file
6
arch/arm/mach-k3/r5/am62px/Makefile
Normal file
|
|
@ -0,0 +1,6 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
|
||||||
|
obj-y += clk-data.o
|
||||||
|
obj-y += dev-data.o
|
||||||
325
arch/arm/mach-k3/r5/am62px/clk-data.c
Normal file
325
arch/arm/mach-k3/r5/am62px/clk-data.c
Normal file
|
|
@ -0,0 +1,325 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* AM62PX specific clock platform data
|
||||||
|
*
|
||||||
|
* This file is auto generated. Please do not hand edit and report any issues
|
||||||
|
* to Bryan Brattlof <bb@ti.com>.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/clk-provider.h>
|
||||||
|
#include "k3-clk.h"
|
||||||
|
|
||||||
|
static const char * const gluelogic_hfosc0_clkout_parents[] = {
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
"osc_24_mhz",
|
||||||
|
"osc_25_mhz",
|
||||||
|
"osc_26_mhz",
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const clk_32k_rc_sel_out0_parents[] = {
|
||||||
|
"gluelogic_rcosc_clk_1p0v_97p65k",
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
"gluelogic_rcosc_clk_1p0v_97p65k",
|
||||||
|
"gluelogic_lfosc0_clkout",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
|
||||||
|
"board_0_mmc1_clklb_out",
|
||||||
|
"board_0_mmc1_clk_out",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
|
||||||
|
"board_0_ospi0_dqs_out",
|
||||||
|
"board_0_ospi0_lbclko_out",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_usb0_refclk_sel_out0_parents[] = {
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
"postdiv4_16ff_main_0_hsdivout8_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_usb1_refclk_sel_out0_parents[] = {
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
"postdiv4_16ff_main_0_hsdivout8_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
"hsdiv4_16fft_main_0_hsdivout0_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
"hsdiv4_16fft_mcu_0_hsdivout0_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const clkout0_ctrl_out0_parents[] = {
|
||||||
|
"hsdiv4_16fft_main_2_hsdivout1_clk",
|
||||||
|
"hsdiv4_16fft_main_2_hsdivout1_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
|
||||||
|
"postdiv4_16ff_main_0_hsdivout5_clk",
|
||||||
|
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
|
||||||
|
"postdiv4_16ff_main_0_hsdivout5_clk",
|
||||||
|
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_gtcclk_sel_out0_parents[] = {
|
||||||
|
"postdiv4_16ff_main_2_hsdivout5_clk",
|
||||||
|
"postdiv4_16ff_main_0_hsdivout6_clk",
|
||||||
|
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||||
|
NULL,
|
||||||
|
"board_0_mcu_ext_refclk0_out",
|
||||||
|
"board_0_ext_refclk1_out",
|
||||||
|
"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
|
||||||
|
"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
|
||||||
|
"hsdiv4_16fft_main_0_hsdivout1_clk",
|
||||||
|
"postdiv1_16fft_main_1_hsdivout5_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_timerclkn_sel_out0_parents[] = {
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
"clk_32k_rc_sel_out0",
|
||||||
|
"postdiv4_16ff_main_0_hsdivout7_clk",
|
||||||
|
"gluelogic_rcosc_clkout",
|
||||||
|
"board_0_mcu_ext_refclk0_out",
|
||||||
|
"board_0_ext_refclk1_out",
|
||||||
|
NULL,
|
||||||
|
"board_0_cp_gemac_cpts0_rft_clk_out",
|
||||||
|
"hsdiv4_16fft_main_1_hsdivout3_clk",
|
||||||
|
"postdiv4_16ff_main_2_hsdivout6_clk",
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const wkup_clkout_sel_out0_parents[] = {
|
||||||
|
NULL,
|
||||||
|
"gluelogic_lfosc0_clkout",
|
||||||
|
"hsdiv4_16fft_main_0_hsdivout2_clk",
|
||||||
|
"hsdiv4_16fft_main_1_hsdivout2_clk",
|
||||||
|
"postdiv4_16ff_main_2_hsdivout9_clk",
|
||||||
|
"clk_32k_rc_sel_out0",
|
||||||
|
"gluelogic_rcosc_clkout",
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const wkup_clkout_sel_io_out0_parents[] = {
|
||||||
|
"wkup_clkout_sel_out0",
|
||||||
|
"gluelogic_hfosc0_clkout",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const wkup_clksel_out0_parents[] = {
|
||||||
|
"hsdiv3_16fft_main_15_hsdivout0_clk",
|
||||||
|
"hsdiv4_16fft_mcu_0_hsdivout0_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const main_usart0_fclk_sel_out0_parents[] = {
|
||||||
|
"usart_programmable_clock_divider_out0",
|
||||||
|
"hsdiv4_16fft_main_1_hsdivout1_clk",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct clk_data clk_list[] = {
|
||||||
|
CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
|
||||||
|
CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
|
||||||
|
CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
|
||||||
|
CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
|
||||||
|
CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
|
||||||
|
CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
|
||||||
|
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
|
||||||
|
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
|
||||||
|
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||||
|
CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
|
||||||
|
CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
|
||||||
|
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||||
|
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||||
|
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0, 1920000000),
|
||||||
|
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||||
|
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||||
|
CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
|
||||||
|
CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
|
||||||
|
CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
|
||||||
|
CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||||
|
CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||||
|
CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
|
||||||
|
CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
|
||||||
|
CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_0_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x68009c, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_2_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x682098, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
|
||||||
|
CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
|
||||||
|
CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
|
||||||
|
CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
|
||||||
|
CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
|
||||||
|
CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
|
||||||
|
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
|
||||||
|
CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x68108c, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
|
||||||
|
CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
|
||||||
|
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
|
||||||
|
CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
|
||||||
|
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
|
||||||
|
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
|
||||||
|
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
|
||||||
|
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
|
||||||
|
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
|
||||||
|
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
|
||||||
|
CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
|
||||||
|
CLK_MUX("main_timerclkn_sel_out0", main_timerclkn_sel_out0_parents, 16, 0x1081b0, 0, 4, 0),
|
||||||
|
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
|
||||||
|
CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
|
||||||
|
CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
|
||||||
|
CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
|
||||||
|
CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
|
||||||
|
CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
|
||||||
|
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct dev_clk soc_dev_clk_data[] = {
|
||||||
|
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
|
||||||
|
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||||
|
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||||
|
DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
|
||||||
|
DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
|
||||||
|
DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
|
||||||
|
DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
|
||||||
|
DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
|
||||||
|
DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
|
||||||
|
DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
|
||||||
|
DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(36, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(36, 2, "main_timerclkn_sel_out0"),
|
||||||
|
DEV_CLK(36, 3, "gluelogic_hfosc0_clkout"),
|
||||||
|
DEV_CLK(36, 4, "clk_32k_rc_sel_out0"),
|
||||||
|
DEV_CLK(36, 5, "postdiv4_16ff_main_0_hsdivout7_clk"),
|
||||||
|
DEV_CLK(36, 6, "gluelogic_rcosc_clkout"),
|
||||||
|
DEV_CLK(36, 7, "board_0_mcu_ext_refclk0_out"),
|
||||||
|
DEV_CLK(36, 8, "board_0_ext_refclk1_out"),
|
||||||
|
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||||
|
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
|
||||||
|
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
|
||||||
|
DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
|
||||||
|
DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
|
||||||
|
DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||||
|
DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
|
||||||
|
DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
|
||||||
|
DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
|
||||||
|
DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
|
||||||
|
DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
|
||||||
|
DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||||
|
DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
|
||||||
|
DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
|
||||||
|
DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
|
||||||
|
DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
|
||||||
|
DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
|
||||||
|
DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
|
||||||
|
DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(61, 9, "wkup_clksel_out0"),
|
||||||
|
DEV_CLK(61, 10, "hsdiv3_16fft_main_15_hsdivout0_clk"),
|
||||||
|
DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
|
||||||
|
DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
|
||||||
|
DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
|
||||||
|
DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
|
||||||
|
DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
|
||||||
|
DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
|
||||||
|
DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
|
||||||
|
DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
|
||||||
|
DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
|
||||||
|
DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
|
||||||
|
DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||||
|
DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
|
||||||
|
DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
|
||||||
|
DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
|
||||||
|
DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(157, 36, "clkout0_ctrl_out0"),
|
||||||
|
DEV_CLK(157, 37, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||||
|
DEV_CLK(157, 38, "hsdiv4_16fft_main_2_hsdivout1_clk"),
|
||||||
|
DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
|
||||||
|
DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
|
||||||
|
DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||||
|
DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||||
|
DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
|
||||||
|
DEV_CLK(157, 145, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
|
||||||
|
DEV_CLK(157, 161, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
|
||||||
|
DEV_CLK(157, 163, "dmtimer_dmc1ms_main_0_timer_pwm"),
|
||||||
|
DEV_CLK(157, 174, "wkup_clkout_sel_io_out0"),
|
||||||
|
DEV_CLK(157, 175, "wkup_clkout_sel_out0"),
|
||||||
|
DEV_CLK(157, 176, "gluelogic_hfosc0_clkout"),
|
||||||
|
DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
|
||||||
|
DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
|
||||||
|
DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
|
||||||
|
DEV_CLK(161, 10, "board_0_tck_out"),
|
||||||
|
DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
|
||||||
|
DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
|
||||||
|
DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
|
||||||
|
DEV_CLK(162, 10, "board_0_tck_out"),
|
||||||
|
DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||||
|
DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
|
||||||
|
DEV_CLK(170, 2, "board_0_tck_out"),
|
||||||
|
DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct ti_k3_clk_platdata am62px_clk_platdata = {
|
||||||
|
.clk_list = clk_list,
|
||||||
|
.clk_list_cnt = ARRAY_SIZE(clk_list),
|
||||||
|
.soc_dev_clk_data = soc_dev_clk_data,
|
||||||
|
.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
|
||||||
|
};
|
||||||
71
arch/arm/mach-k3/r5/am62px/dev-data.c
Normal file
71
arch/arm/mach-k3/r5/am62px/dev-data.c
Normal file
|
|
@ -0,0 +1,71 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* AM62PX specific device platform data
|
||||||
|
*
|
||||||
|
* This file is auto generated. Please do not hand edit and report any issues
|
||||||
|
* to Bryan Brattlof <bb@ti.com>.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "k3-dev.h"
|
||||||
|
|
||||||
|
static struct ti_psc soc_psc_list[] = {
|
||||||
|
[0] = PSC(0, 0x00400000),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct ti_pd soc_pd_list[] = {
|
||||||
|
[0] = PSC_PD(0, &soc_psc_list[0], NULL),
|
||||||
|
[1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]),
|
||||||
|
[2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]),
|
||||||
|
[3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct ti_lpsc soc_lpsc_list[] = {
|
||||||
|
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||||
|
[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
|
||||||
|
[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
|
||||||
|
[3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||||
|
[4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||||
|
[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||||
|
[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||||
|
[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||||
|
[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
|
||||||
|
[9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
|
||||||
|
[10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
|
||||||
|
[11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
|
||||||
|
[12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
|
||||||
|
[13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct ti_dev soc_dev_list[] = {
|
||||||
|
PSC_DEV(16, &soc_lpsc_list[0]),
|
||||||
|
PSC_DEV(77, &soc_lpsc_list[0]),
|
||||||
|
PSC_DEV(61, &soc_lpsc_list[0]),
|
||||||
|
PSC_DEV(178, &soc_lpsc_list[1]),
|
||||||
|
PSC_DEV(179, &soc_lpsc_list[2]),
|
||||||
|
PSC_DEV(57, &soc_lpsc_list[3]),
|
||||||
|
PSC_DEV(58, &soc_lpsc_list[4]),
|
||||||
|
PSC_DEV(161, &soc_lpsc_list[5]),
|
||||||
|
PSC_DEV(162, &soc_lpsc_list[6]),
|
||||||
|
PSC_DEV(75, &soc_lpsc_list[7]),
|
||||||
|
PSC_DEV(36, &soc_lpsc_list[8]),
|
||||||
|
PSC_DEV(102, &soc_lpsc_list[8]),
|
||||||
|
PSC_DEV(146, &soc_lpsc_list[8]),
|
||||||
|
PSC_DEV(166, &soc_lpsc_list[9]),
|
||||||
|
PSC_DEV(135, &soc_lpsc_list[10]),
|
||||||
|
PSC_DEV(170, &soc_lpsc_list[11]),
|
||||||
|
PSC_DEV(177, &soc_lpsc_list[12]),
|
||||||
|
PSC_DEV(55, &soc_lpsc_list[13]),
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct ti_k3_pd_platdata am62px_pd_platdata = {
|
||||||
|
.psc = soc_psc_list,
|
||||||
|
.pd = soc_pd_list,
|
||||||
|
.lpsc = soc_lpsc_list,
|
||||||
|
.devs = soc_dev_list,
|
||||||
|
.num_psc = ARRAY_SIZE(soc_psc_list),
|
||||||
|
.num_pd = ARRAY_SIZE(soc_pd_list),
|
||||||
|
.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
|
||||||
|
.num_devs = ARRAY_SIZE(soc_dev_list),
|
||||||
|
};
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
obj-y += clk-data.o
|
obj-y += clk-data.o
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
obj-y += clk-data.o
|
obj-y += clk-data.o
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,4 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
#
|
#
|
||||||
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
obj-y += clk-data.o
|
obj-y += clk-data.o
|
||||||
|
|
|
||||||
26
board/ti/am62px/Kconfig
Normal file
26
board/ti/am62px/Kconfig
Normal file
|
|
@ -0,0 +1,26 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
|
||||||
|
if TARGET_AM62P5_R5_EVM || TARGET_AM62P5_A53_EVM
|
||||||
|
|
||||||
|
config SYS_BOARD
|
||||||
|
default "am62px"
|
||||||
|
|
||||||
|
config SYS_VENDOR
|
||||||
|
default "ti"
|
||||||
|
|
||||||
|
config SYS_CONFIG_NAME
|
||||||
|
default "am62px_evm"
|
||||||
|
|
||||||
|
source "board/ti/common/Kconfig"
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
||||||
|
if TARGET_AM62P5_R5_EVM
|
||||||
|
|
||||||
|
config SPL_LDSCRIPT
|
||||||
|
default "arch/arm/mach-omap2/u-boot-spl.lds"
|
||||||
|
|
||||||
|
endif
|
||||||
9
board/ti/am62px/MAINTAINERS
Normal file
9
board/ti/am62px/MAINTAINERS
Normal file
|
|
@ -0,0 +1,9 @@
|
||||||
|
AM62Px BOARD
|
||||||
|
M: Vignesh Raghavendra <vigneshr@ti.com>
|
||||||
|
M: Bryan Brattlof <bb@ti.com>
|
||||||
|
M: Tom Rini <trini@konsulko.com>
|
||||||
|
S: Maintained
|
||||||
|
F: board/ti/am62px/
|
||||||
|
F: include/configs/am62p5_evm.h
|
||||||
|
F: configs/am62px_evm_r5_defconfig
|
||||||
|
F: configs/am62px_evm_a53_defconfig
|
||||||
7
board/ti/am62px/Makefile
Normal file
7
board/ti/am62px/Makefile
Normal file
|
|
@ -0,0 +1,7 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y += evm.o
|
||||||
15
board/ti/am62px/am62px.env
Normal file
15
board/ti/am62px/am62px.env
Normal file
|
|
@ -0,0 +1,15 @@
|
||||||
|
#include <env/ti/ti_common.env>
|
||||||
|
#include <env/ti/mmc.env>
|
||||||
|
|
||||||
|
name_kern=Image
|
||||||
|
console=ttyS2,115200n8
|
||||||
|
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
|
||||||
|
${mtdparts}
|
||||||
|
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
|
||||||
|
|
||||||
|
boot_targets=mmc1 mmc0 pxe dhcp
|
||||||
|
boot=mmc
|
||||||
|
mmcdev=1
|
||||||
|
bootpart=1:2
|
||||||
|
bootdir=/boot
|
||||||
|
rd_spec=-
|
||||||
37
board/ti/am62px/board-cfg.yaml
Normal file
37
board/ti/am62px/board-cfg.yaml
Normal file
|
|
@ -0,0 +1,37 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
# Board configuration for AM62Px SoCs
|
||||||
|
#
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
board-cfg:
|
||||||
|
rev:
|
||||||
|
boardcfg_abi_maj: 0x0
|
||||||
|
boardcfg_abi_min: 0x1
|
||||||
|
control:
|
||||||
|
subhdr:
|
||||||
|
magic: 0xC1D3
|
||||||
|
size: 7
|
||||||
|
main_isolation_enable: 0x5A
|
||||||
|
main_isolation_hostid: 0x2
|
||||||
|
secproxy:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x1207
|
||||||
|
size: 7
|
||||||
|
scaling_factor: 0x1
|
||||||
|
scaling_profile: 0x1
|
||||||
|
disable_main_nav_secure_proxy: 0
|
||||||
|
msmc:
|
||||||
|
subhdr:
|
||||||
|
magic: 0xA5C3
|
||||||
|
size: 5
|
||||||
|
msmc_cache_size: 0x10
|
||||||
|
debug_cfg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x020C
|
||||||
|
size: 8
|
||||||
|
trace_dst_enables: 0x00
|
||||||
|
trace_src_enables: 0x00
|
||||||
29
board/ti/am62px/evm.c
Normal file
29
board/ti/am62px/evm.c
Normal file
|
|
@ -0,0 +1,29 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
/*
|
||||||
|
* Board specific initialization for AM62Px platforms
|
||||||
|
*
|
||||||
|
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <asm/arch/hardware.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <dm/uclass.h>
|
||||||
|
#include <env.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
#include <spl.h>
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
return fdtdec_setup_mem_size_base();
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init_banksize(void)
|
||||||
|
{
|
||||||
|
return fdtdec_setup_memory_banksize();
|
||||||
|
}
|
||||||
12
board/ti/am62px/pm-cfg.yaml
Normal file
12
board/ti/am62px/pm-cfg.yaml
Normal file
|
|
@ -0,0 +1,12 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
# Power management configuration for AM62Px
|
||||||
|
#
|
||||||
|
#
|
||||||
|
---
|
||||||
|
pm-cfg:
|
||||||
|
rev:
|
||||||
|
boardcfg_abi_maj: 0x0
|
||||||
|
boardcfg_abi_min: 0x1
|
||||||
987
board/ti/am62px/rm-cfg.yaml
Normal file
987
board/ti/am62px/rm-cfg.yaml
Normal file
|
|
@ -0,0 +1,987 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
# Resource management configuration for AM62P
|
||||||
|
#
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
rm-cfg:
|
||||||
|
rm_boardcfg:
|
||||||
|
rev:
|
||||||
|
boardcfg_abi_maj: 0x0
|
||||||
|
boardcfg_abi_min: 0x1
|
||||||
|
host_cfg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x4C41
|
||||||
|
size: 356
|
||||||
|
host_cfg_entries:
|
||||||
|
- # 1
|
||||||
|
host_id: 12
|
||||||
|
allowed_atype: 0x2A
|
||||||
|
allowed_qos: 0xAAAA
|
||||||
|
allowed_orderid: 0xAAAAAAAA
|
||||||
|
allowed_priority: 0xAAAA
|
||||||
|
allowed_sched_priority: 0xAA
|
||||||
|
- # 2
|
||||||
|
host_id: 30
|
||||||
|
allowed_atype: 0x2A
|
||||||
|
allowed_qos: 0xAAAA
|
||||||
|
allowed_orderid: 0xAAAAAAAA
|
||||||
|
allowed_priority: 0xAAAA
|
||||||
|
allowed_sched_priority: 0xAA
|
||||||
|
- # 3
|
||||||
|
host_id: 36
|
||||||
|
allowed_atype: 0x2A
|
||||||
|
allowed_qos: 0xAAAA
|
||||||
|
allowed_orderid: 0xAAAAAAAA
|
||||||
|
allowed_priority: 0xAAAA
|
||||||
|
allowed_sched_priority: 0xAA
|
||||||
|
- # 4
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 5
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 6
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 7
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 8
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 9
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 10
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 11
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 12
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 13
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 14
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 15
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 16
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 17
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 18
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 19
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 20
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 21
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 22
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 23
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 24
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 25
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 26
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 27
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 28
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 29
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 30
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 31
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- # 32
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
resasg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x7B25
|
||||||
|
size: 8
|
||||||
|
resasg_entries_size: 984
|
||||||
|
reserved: 0
|
||||||
|
resasg_entries:
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 16
|
||||||
|
type: 192
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 34
|
||||||
|
num_resource: 2
|
||||||
|
type: 192
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 2
|
||||||
|
type: 320
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 2
|
||||||
|
num_resource: 2
|
||||||
|
type: 320
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 2
|
||||||
|
num_resource: 2
|
||||||
|
type: 320
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 4
|
||||||
|
num_resource: 4
|
||||||
|
type: 320
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 26
|
||||||
|
type: 384
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 50176
|
||||||
|
num_resource: 164
|
||||||
|
type: 1666
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 1
|
||||||
|
type: 1667
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 18
|
||||||
|
type: 1677
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 6
|
||||||
|
type: 1677
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 6
|
||||||
|
type: 1677
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 24
|
||||||
|
num_resource: 2
|
||||||
|
type: 1677
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 26
|
||||||
|
num_resource: 6
|
||||||
|
type: 1677
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 57
|
||||||
|
num_resource: 18
|
||||||
|
type: 1678
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 75
|
||||||
|
num_resource: 5
|
||||||
|
type: 1678
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 75
|
||||||
|
num_resource: 5
|
||||||
|
type: 1678
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 80
|
||||||
|
num_resource: 2
|
||||||
|
type: 1678
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 32
|
||||||
|
num_resource: 12
|
||||||
|
type: 1679
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 44
|
||||||
|
num_resource: 6
|
||||||
|
type: 1679
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 44
|
||||||
|
num_resource: 6
|
||||||
|
type: 1679
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 50
|
||||||
|
num_resource: 2
|
||||||
|
type: 1679
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 52
|
||||||
|
num_resource: 5
|
||||||
|
type: 1679
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 18
|
||||||
|
type: 1696
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 6
|
||||||
|
type: 1696
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 6
|
||||||
|
type: 1696
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 24
|
||||||
|
num_resource: 2
|
||||||
|
type: 1696
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 26
|
||||||
|
num_resource: 6
|
||||||
|
type: 1696
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 18
|
||||||
|
type: 1697
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 5
|
||||||
|
type: 1697
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 5
|
||||||
|
type: 1697
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 23
|
||||||
|
num_resource: 2
|
||||||
|
type: 1697
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 12
|
||||||
|
type: 1698
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 12
|
||||||
|
num_resource: 6
|
||||||
|
type: 1698
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 12
|
||||||
|
num_resource: 6
|
||||||
|
type: 1698
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 18
|
||||||
|
num_resource: 2
|
||||||
|
type: 1698
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 20
|
||||||
|
num_resource: 5
|
||||||
|
type: 1698
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 5
|
||||||
|
num_resource: 35
|
||||||
|
type: 1802
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 45
|
||||||
|
num_resource: 35
|
||||||
|
type: 1802
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 45
|
||||||
|
num_resource: 35
|
||||||
|
type: 1802
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 168
|
||||||
|
num_resource: 8
|
||||||
|
type: 1802
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 14
|
||||||
|
num_resource: 512
|
||||||
|
type: 1805
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 526
|
||||||
|
num_resource: 256
|
||||||
|
type: 1805
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 526
|
||||||
|
num_resource: 256
|
||||||
|
type: 1805
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 782
|
||||||
|
num_resource: 128
|
||||||
|
type: 1805
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 910
|
||||||
|
num_resource: 626
|
||||||
|
type: 1805
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 4096
|
||||||
|
num_resource: 29
|
||||||
|
type: 1807
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 4608
|
||||||
|
num_resource: 99
|
||||||
|
type: 1808
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 5120
|
||||||
|
num_resource: 24
|
||||||
|
type: 1809
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 5632
|
||||||
|
num_resource: 51
|
||||||
|
type: 1810
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 6144
|
||||||
|
num_resource: 51
|
||||||
|
type: 1811
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 8192
|
||||||
|
num_resource: 32
|
||||||
|
type: 1812
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 8704
|
||||||
|
num_resource: 32
|
||||||
|
type: 1813
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 9216
|
||||||
|
num_resource: 32
|
||||||
|
type: 1814
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 9728
|
||||||
|
num_resource: 25
|
||||||
|
type: 1815
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10240
|
||||||
|
num_resource: 25
|
||||||
|
type: 1816
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10752
|
||||||
|
num_resource: 25
|
||||||
|
type: 1817
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 11264
|
||||||
|
num_resource: 25
|
||||||
|
type: 1818
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 11776
|
||||||
|
num_resource: 25
|
||||||
|
type: 1819
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 12288
|
||||||
|
num_resource: 25
|
||||||
|
type: 1820
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 1
|
||||||
|
type: 1923
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1936
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 64
|
||||||
|
type: 1937
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 64
|
||||||
|
type: 1937
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 83
|
||||||
|
num_resource: 8
|
||||||
|
type: 1938
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 91
|
||||||
|
num_resource: 8
|
||||||
|
type: 1939
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 99
|
||||||
|
num_resource: 10
|
||||||
|
type: 1942
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 109
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 109
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 112
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 115
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 118
|
||||||
|
num_resource: 16
|
||||||
|
type: 1943
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 118
|
||||||
|
num_resource: 16
|
||||||
|
type: 1943
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 134
|
||||||
|
num_resource: 8
|
||||||
|
type: 1944
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 134
|
||||||
|
num_resource: 8
|
||||||
|
type: 1945
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 142
|
||||||
|
num_resource: 8
|
||||||
|
type: 1946
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 142
|
||||||
|
num_resource: 8
|
||||||
|
type: 1947
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1955
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 8
|
||||||
|
type: 1956
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 8
|
||||||
|
type: 1956
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 27
|
||||||
|
num_resource: 1
|
||||||
|
type: 1957
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 28
|
||||||
|
num_resource: 1
|
||||||
|
type: 1958
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1961
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1962
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 1
|
||||||
|
type: 1963
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 1
|
||||||
|
type: 1963
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 16
|
||||||
|
type: 1964
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 16
|
||||||
|
type: 1964
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 20
|
||||||
|
num_resource: 1
|
||||||
|
type: 1965
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 35
|
||||||
|
num_resource: 8
|
||||||
|
type: 1966
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 21
|
||||||
|
num_resource: 1
|
||||||
|
type: 1967
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 35
|
||||||
|
num_resource: 8
|
||||||
|
type: 1968
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 22
|
||||||
|
num_resource: 1
|
||||||
|
type: 1969
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 43
|
||||||
|
num_resource: 8
|
||||||
|
type: 1970
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 23
|
||||||
|
num_resource: 1
|
||||||
|
type: 1971
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 43
|
||||||
|
num_resource: 8
|
||||||
|
type: 1972
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 1
|
||||||
|
type: 2112
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 2
|
||||||
|
num_resource: 2
|
||||||
|
type: 2122
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 51200
|
||||||
|
num_resource: 12
|
||||||
|
type: 12738
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 1
|
||||||
|
type: 12739
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 6
|
||||||
|
type: 12750
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 6
|
||||||
|
type: 12769
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 8
|
||||||
|
type: 12810
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 12288
|
||||||
|
num_resource: 128
|
||||||
|
type: 12813
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 3072
|
||||||
|
num_resource: 6
|
||||||
|
type: 12826
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 3584
|
||||||
|
num_resource: 6
|
||||||
|
type: 12827
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 4096
|
||||||
|
num_resource: 6
|
||||||
|
type: 12828
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
378
board/ti/am62px/sec-cfg.yaml
Normal file
378
board/ti/am62px/sec-cfg.yaml
Normal file
|
|
@ -0,0 +1,378 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
# Security configuration for AM62Px
|
||||||
|
#
|
||||||
|
---
|
||||||
|
sec-cfg:
|
||||||
|
rev:
|
||||||
|
boardcfg_abi_maj: 0x0
|
||||||
|
boardcfg_abi_min: 0x1
|
||||||
|
processor_acl_list:
|
||||||
|
subhdr:
|
||||||
|
magic: 0xF1EA
|
||||||
|
size: 164
|
||||||
|
proc_acl_entries:
|
||||||
|
- # 1
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 2
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 3
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 4
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 5
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 6
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 7
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 8
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 9
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 10
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 11
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 12
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 13
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 14
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 15
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 16
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 17
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 18
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 19
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 20
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 21
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 22
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 23
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 24
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 25
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 26
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 27
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 28
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 29
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 30
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 31
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
- # 32
|
||||||
|
processor_id: 0
|
||||||
|
proc_access_master: 0
|
||||||
|
proc_access_secondary: [0, 0, 0]
|
||||||
|
host_hierarchy:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x8D27
|
||||||
|
size: 68
|
||||||
|
host_hierarchy_entries:
|
||||||
|
- # 1
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 2
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 3
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 4
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 5
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 6
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 7
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 8
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 9
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 10
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 11
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 12
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 13
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 14
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 15
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 16
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 17
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 18
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 19
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 20
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 21
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 22
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 23
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 24
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 25
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 26
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 27
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 28
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 29
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 30
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 31
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
- # 32
|
||||||
|
host_id: 0
|
||||||
|
supervisor_host_id: 0
|
||||||
|
otp_config:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x4081
|
||||||
|
size: 69
|
||||||
|
write_host_id: 0
|
||||||
|
otp_entry:
|
||||||
|
- # 1
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 2
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 3
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 4
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 5
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 6
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 7
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 8
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 9
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 10
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 11
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 12
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 13
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 14
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 15
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 16
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 17
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 18
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 19
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 20
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 21
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 22
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 23
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 24
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 25
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 26
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 27
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 28
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 29
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 30
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 31
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
- # 32
|
||||||
|
host_id: 0
|
||||||
|
host_perms: 0
|
||||||
|
dkek_config:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x5170
|
||||||
|
size: 12
|
||||||
|
allowed_hosts: [128, 0, 0, 0]
|
||||||
|
allow_dkek_export_tisci: 0x5A
|
||||||
|
rsvd: [0, 0, 0]
|
||||||
|
sa2ul_cfg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x23BE
|
||||||
|
size: 0
|
||||||
|
auth_resource_owner: 0
|
||||||
|
enable_saul_psil_global_config_writes: 0x5A
|
||||||
|
rsvd: [0, 0]
|
||||||
|
sec_dbg_config:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x42AF
|
||||||
|
size: 16
|
||||||
|
allow_jtag_unlock: 0x5A
|
||||||
|
allow_wildcard_unlock: 0x5A
|
||||||
|
allowed_debug_level_rsvd: 0
|
||||||
|
rsvd: 0
|
||||||
|
min_cert_rev: 0x0
|
||||||
|
jtag_unlock_hosts: [0, 0, 0, 0]
|
||||||
|
sec_handover_cfg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x608F
|
||||||
|
size: 10
|
||||||
|
handover_msg_sender: 0
|
||||||
|
handover_to_host_id: 0
|
||||||
|
rsvd: [0, 0, 0, 0]
|
||||||
879
board/ti/am62px/tifs-rm-cfg.yaml
Normal file
879
board/ti/am62px/tifs-rm-cfg.yaml
Normal file
|
|
@ -0,0 +1,879 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
#
|
||||||
|
# Resource management configuration for AM62P
|
||||||
|
#
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
tifs-rm-cfg:
|
||||||
|
rm_boardcfg:
|
||||||
|
rev:
|
||||||
|
boardcfg_abi_maj : 0x0
|
||||||
|
boardcfg_abi_min : 0x1
|
||||||
|
host_cfg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x4C41
|
||||||
|
size : 356
|
||||||
|
host_cfg_entries:
|
||||||
|
- #1
|
||||||
|
host_id: 12
|
||||||
|
allowed_atype: 0x2A
|
||||||
|
allowed_qos: 0xAAAA
|
||||||
|
allowed_orderid: 0xAAAAAAAA
|
||||||
|
allowed_priority: 0xAAAA
|
||||||
|
allowed_sched_priority: 0xAA
|
||||||
|
- #2
|
||||||
|
host_id: 30
|
||||||
|
allowed_atype: 0x2A
|
||||||
|
allowed_qos: 0xAAAA
|
||||||
|
allowed_orderid: 0xAAAAAAAA
|
||||||
|
allowed_priority: 0xAAAA
|
||||||
|
allowed_sched_priority: 0xAA
|
||||||
|
- #3
|
||||||
|
host_id: 36
|
||||||
|
allowed_atype: 0x2A
|
||||||
|
allowed_qos: 0xAAAA
|
||||||
|
allowed_orderid: 0xAAAAAAAA
|
||||||
|
allowed_priority: 0xAAAA
|
||||||
|
allowed_sched_priority: 0xAA
|
||||||
|
- #4
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #5
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #6
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #7
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #8
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #9
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #10
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #11
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #12
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #13
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #14
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #15
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #16
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #17
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #18
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #19
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #20
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #21
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #22
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #23
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #24
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #25
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #26
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #27
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #28
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #29
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #30
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #31
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
- #32
|
||||||
|
host_id: 0
|
||||||
|
allowed_atype: 0
|
||||||
|
allowed_qos: 0
|
||||||
|
allowed_orderid: 0
|
||||||
|
allowed_priority: 0
|
||||||
|
allowed_sched_priority: 0
|
||||||
|
resasg:
|
||||||
|
subhdr:
|
||||||
|
magic: 0x7B25
|
||||||
|
size: 8
|
||||||
|
resasg_entries_size: 840
|
||||||
|
reserved: 0
|
||||||
|
resasg_entries:
|
||||||
|
-
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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|
||||||
|
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||||||
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|
||||||
|
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|
||||||
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|
||||||
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||||||
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|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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||||||
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|
||||||
|
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||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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||||||
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||||||
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||||||
|
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
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|
||||||
|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1936
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1936
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 64
|
||||||
|
type: 1937
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 64
|
||||||
|
type: 1937
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 83
|
||||||
|
num_resource: 8
|
||||||
|
type: 1938
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 91
|
||||||
|
num_resource: 8
|
||||||
|
type: 1939
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 99
|
||||||
|
num_resource: 10
|
||||||
|
type: 1942
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 109
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 109
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 112
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 115
|
||||||
|
num_resource: 3
|
||||||
|
type: 1942
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 118
|
||||||
|
num_resource: 16
|
||||||
|
type: 1943
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 118
|
||||||
|
num_resource: 16
|
||||||
|
type: 1943
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 134
|
||||||
|
num_resource: 8
|
||||||
|
type: 1944
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 134
|
||||||
|
num_resource: 8
|
||||||
|
type: 1945
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 142
|
||||||
|
num_resource: 8
|
||||||
|
type: 1946
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 142
|
||||||
|
num_resource: 8
|
||||||
|
type: 1947
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1955
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1955
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 8
|
||||||
|
type: 1956
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 8
|
||||||
|
type: 1956
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 27
|
||||||
|
num_resource: 1
|
||||||
|
type: 1957
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 28
|
||||||
|
num_resource: 1
|
||||||
|
type: 1958
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1961
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1961
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 10
|
||||||
|
type: 1962
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 35
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 10
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 13
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 30
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 16
|
||||||
|
num_resource: 3
|
||||||
|
type: 1962
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 1
|
||||||
|
type: 1963
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 1
|
||||||
|
type: 1963
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 16
|
||||||
|
type: 1964
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 19
|
||||||
|
num_resource: 16
|
||||||
|
type: 1964
|
||||||
|
host_id: 36
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 20
|
||||||
|
num_resource: 1
|
||||||
|
type: 1965
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 35
|
||||||
|
num_resource: 8
|
||||||
|
type: 1966
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 21
|
||||||
|
num_resource: 1
|
||||||
|
type: 1967
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 35
|
||||||
|
num_resource: 8
|
||||||
|
type: 1968
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 22
|
||||||
|
num_resource: 1
|
||||||
|
type: 1969
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 43
|
||||||
|
num_resource: 8
|
||||||
|
type: 1970
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 23
|
||||||
|
num_resource: 1
|
||||||
|
type: 1971
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 43
|
||||||
|
num_resource: 8
|
||||||
|
type: 1972
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 1
|
||||||
|
type: 2112
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 2
|
||||||
|
num_resource: 2
|
||||||
|
type: 2122
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 6
|
||||||
|
type: 12750
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 6
|
||||||
|
type: 12769
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 0
|
||||||
|
num_resource: 8
|
||||||
|
type: 12810
|
||||||
|
host_id: 12
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 3072
|
||||||
|
num_resource: 6
|
||||||
|
type: 12826
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 3584
|
||||||
|
num_resource: 6
|
||||||
|
type: 12827
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
|
-
|
||||||
|
start_resource: 4096
|
||||||
|
num_resource: 6
|
||||||
|
type: 12828
|
||||||
|
host_id: 128
|
||||||
|
reserved: 0
|
||||||
177
configs/am62px_evm_a53_defconfig
Normal file
177
configs/am62px_evm_a53_defconfig
Normal file
|
|
@ -0,0 +1,177 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_K3=y
|
||||||
|
CONFIG_TI_SECURE_DEVICE=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||||
|
CONFIG_SPL_GPIO=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_NR_DRAM_BANKS=2
|
||||||
|
CONFIG_SOC_K3_AM62P5=y
|
||||||
|
CONFIG_TARGET_AM62P5_A53_EVM=y
|
||||||
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||||
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
|
||||||
|
CONFIG_SF_DEFAULT_SPEED=25000000
|
||||||
|
CONFIG_ENV_SIZE=0x40000
|
||||||
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_SPL_DM_SPI=y
|
||||||
|
CONFIG_OF_UPSTREAM=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk"
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||||
|
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
|
CONFIG_SPL_MMC=y
|
||||||
|
CONFIG_SPL_SERIAL=y
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_SPL_FS_FAT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI=y
|
||||||
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||||
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
|
||||||
|
CONFIG_BOOTSTD_FULL=y
|
||||||
|
CONFIG_BOOTSTD_DEFAULTS=y
|
||||||
|
CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
|
||||||
|
CONFIG_SPL_MAX_SIZE=0x58000
|
||||||
|
CONFIG_SPL_PAD_TO=0x0
|
||||||
|
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||||
|
CONFIG_SPL_BSS_START_ADDR=0x80a00000
|
||||||
|
CONFIG_SPL_BSS_MAX_SIZE=0x80000
|
||||||
|
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
|
||||||
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_ENV_SUPPORT=y
|
||||||
|
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||||
|
CONFIG_SPL_I2C=y
|
||||||
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
|
CONFIG_SPL_MTD_SUPPORT=y
|
||||||
|
CONFIG_SPL_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
|
CONFIG_SPL_RAM_DEVICE=y
|
||||||
|
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||||
|
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_LOAD=y
|
||||||
|
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
|
||||||
|
CONFIG_SPL_THERMAL=y
|
||||||
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
|
CONFIG_SYS_MAXARGS=64
|
||||||
|
CONFIG_CMD_CLK=y
|
||||||
|
CONFIG_CMD_DFU=y
|
||||||
|
CONFIG_CMD_DM=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_MTD=y
|
||||||
|
CONFIG_CMD_REMOTEPROC=y
|
||||||
|
CONFIG_CMD_USB=y
|
||||||
|
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
|
CONFIG_CMD_MTDPARTS=y
|
||||||
|
CONFIG_CMD_UBI=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT=y
|
||||||
|
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
|
||||||
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_DEVICE_REMOVE=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SPL_SYSCON=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_CLK=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_CLK_TI_SCI=y
|
||||||
|
CONFIG_DFU_MMC=y
|
||||||
|
CONFIG_DFU_MTD=y
|
||||||
|
CONFIG_DFU_RAM=y
|
||||||
|
CONFIG_DFU_SF=y
|
||||||
|
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
|
||||||
|
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
|
||||||
|
CONFIG_DMA_CHANNELS=y
|
||||||
|
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||||
|
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||||
|
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
|
||||||
|
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
|
||||||
|
CONFIG_TI_SCI_PROTOCOL=y
|
||||||
|
CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y
|
||||||
|
CONFIG_DA8XX_GPIO=y
|
||||||
|
CONFIG_DM_PCA953X=y
|
||||||
|
CONFIG_SPL_DM_PCA953X=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SYS_I2C_OMAP24XX=y
|
||||||
|
CONFIG_DM_MAILBOX=y
|
||||||
|
CONFIG_K3_SEC_PROXY=y
|
||||||
|
CONFIG_I2C_EEPROM=y
|
||||||
|
CONFIG_SPL_I2C_EEPROM=y
|
||||||
|
CONFIG_FS_LOADER=y
|
||||||
|
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||||
|
CONFIG_MMC_IO_VOLTAGE=y
|
||||||
|
CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_MMC_SDHCI=y
|
||||||
|
CONFIG_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_MMC_SDHCI_AM654=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_MTD=y
|
||||||
|
CONFIG_MTD_SPI_NAND=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPI_FLASH_SOFT_RESET=y
|
||||||
|
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
|
||||||
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
CONFIG_SPI_FLASH_S28HX_T=y
|
||||||
|
CONFIG_PHY_TI_DP83867=y
|
||||||
|
CONFIG_TI_AM65_CPSW_NUSS=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_SINGLE=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_TI_SCI_POWER_DOMAIN=y
|
||||||
|
CONFIG_DM_REGULATOR=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR=y
|
||||||
|
CONFIG_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||||
|
CONFIG_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||||
|
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_DSP=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_R5F=y
|
||||||
|
CONFIG_RESET_TI_SCI=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SOC_DEVICE=y
|
||||||
|
CONFIG_SOC_DEVICE_TI_K3=y
|
||||||
|
CONFIG_SOC_TI=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_CADENCE_QSPI=y
|
||||||
|
CONFIG_SYSRESET=y
|
||||||
|
CONFIG_SPL_SYSRESET=y
|
||||||
|
CONFIG_SYSRESET_TI_SCI=y
|
||||||
|
CONFIG_DM_THERMAL=y
|
||||||
|
CONFIG_USB=y
|
||||||
|
CONFIG_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_DM_USB_GADGET=y
|
||||||
|
CONFIG_SPL_USB_HOST=y
|
||||||
|
CONFIG_USB_XHCI_HCD=y
|
||||||
|
CONFIG_USB_DWC3=y
|
||||||
|
CONFIG_USB_DWC3_GENERIC=y
|
||||||
|
CONFIG_SPL_USB_DWC3_GENERIC=y
|
||||||
|
CONFIG_SPL_USB_STORAGE=y
|
||||||
|
CONFIG_USB_GADGET=y
|
||||||
|
CONFIG_SPL_USB_GADGET=y
|
||||||
|
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||||
|
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||||
|
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
|
||||||
|
CONFIG_SPL_DFU=y
|
||||||
|
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
|
||||||
137
configs/am62px_evm_r5_defconfig
Normal file
137
configs/am62px_evm_r5_defconfig
Normal file
|
|
@ -0,0 +1,137 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_K3=y
|
||||||
|
CONFIG_TI_SECURE_DEVICE=y
|
||||||
|
CONFIG_SYS_MALLOC_F_LEN=0x9000
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_SOC_K3_AM62P5=y
|
||||||
|
CONFIG_TARGET_AM62P5_R5_EVM=y
|
||||||
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||||
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0
|
||||||
|
CONFIG_SF_DEFAULT_SPEED=25000000
|
||||||
|
CONFIG_SF_DEFAULT_MODE=0
|
||||||
|
CONFIG_ENV_SIZE=0x20000
|
||||||
|
CONFIG_ENV_OFFSET=0x680000
|
||||||
|
CONFIG_SPL_DM_SPI=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk"
|
||||||
|
CONFIG_SPL_TEXT_BASE=0x43c00000
|
||||||
|
CONFIG_DM_RESET=y
|
||||||
|
CONFIG_SPL_MMC=y
|
||||||
|
CONFIG_SPL_SERIAL=y
|
||||||
|
CONFIG_SPL_STACK_R_ADDR=0x82000000
|
||||||
|
CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
|
||||||
|
CONFIG_SPL_SIZE_LIMIT=0x3C000
|
||||||
|
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000
|
||||||
|
CONFIG_SPL_FS_FAT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI=y
|
||||||
|
CONFIG_SPL_LOAD_FIT=y
|
||||||
|
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
|
||||||
|
# CONFIG_DISPLAY_CPUINFO is not set
|
||||||
|
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
|
||||||
|
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
|
||||||
|
CONFIG_SPL_MAX_SIZE=0x3B000
|
||||||
|
CONFIG_SPL_PAD_TO=0x0
|
||||||
|
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||||
|
CONFIG_SPL_BSS_START_ADDR=0x43c4b000
|
||||||
|
CONFIG_SPL_BSS_MAX_SIZE=0x3000
|
||||||
|
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
|
||||||
|
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||||
|
CONFIG_SPL_STACK_R=y
|
||||||
|
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
|
||||||
|
CONFIG_SPL_SEPARATE_BSS=y
|
||||||
|
CONFIG_SYS_SPL_MALLOC=y
|
||||||
|
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||||
|
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
|
||||||
|
CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
|
||||||
|
CONFIG_SPL_EARLY_BSS=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||||
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
|
||||||
|
CONFIG_SPL_DMA=y
|
||||||
|
CONFIG_SPL_DM_MAILBOX=y
|
||||||
|
CONFIG_SPL_MTD_SUPPORT=y
|
||||||
|
CONFIG_SPL_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPL_DM_RESET=y
|
||||||
|
CONFIG_SPL_POWER_DOMAIN=y
|
||||||
|
CONFIG_SPL_RAM_SUPPORT=y
|
||||||
|
CONFIG_SPL_RAM_DEVICE=y
|
||||||
|
CONFIG_SPL_REMOTEPROC=y
|
||||||
|
# CONFIG_SPL_SPI_FLASH_TINY is not set
|
||||||
|
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPL_SPI_LOAD=y
|
||||||
|
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
|
||||||
|
CONFIG_SPL_THERMAL=y
|
||||||
|
CONFIG_SPL_YMODEM_SUPPORT=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_CMD_ASKENV=y
|
||||||
|
CONFIG_CMD_DFU=y
|
||||||
|
CONFIG_CMD_GPT=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_REMOTEPROC=y
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
|
CONFIG_CMD_TIME=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_OF_CONTROL=y
|
||||||
|
CONFIG_SPL_OF_CONTROL=y
|
||||||
|
CONFIG_ENV_IS_NOWHERE=y
|
||||||
|
CONFIG_ENV_IS_IN_MMC=y
|
||||||
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||||
|
CONFIG_SYS_MMC_ENV_PART=1
|
||||||
|
# CONFIG_NET is not set
|
||||||
|
CONFIG_SPL_DM=y
|
||||||
|
CONFIG_SPL_DM_DEVICE_REMOVE=y
|
||||||
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||||
|
CONFIG_REGMAP=y
|
||||||
|
CONFIG_SPL_REGMAP=y
|
||||||
|
CONFIG_SPL_OF_TRANSLATE=y
|
||||||
|
CONFIG_CLK=y
|
||||||
|
CONFIG_SPL_CLK=y
|
||||||
|
CONFIG_SPL_CLK_CCF=y
|
||||||
|
CONFIG_SPL_CLK_K3_PLL=y
|
||||||
|
CONFIG_SPL_CLK_K3=y
|
||||||
|
CONFIG_DMA_CHANNELS=y
|
||||||
|
CONFIG_TI_K3_NAVSS_UDMA=y
|
||||||
|
CONFIG_TI_SCI_PROTOCOL=y
|
||||||
|
# CONFIG_GPIO is not set
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SYS_I2C_OMAP24XX=y
|
||||||
|
CONFIG_DM_MAILBOX=y
|
||||||
|
CONFIG_K3_SEC_PROXY=y
|
||||||
|
CONFIG_MMC_HS400_SUPPORT=y
|
||||||
|
CONFIG_MMC_SDHCI=y
|
||||||
|
CONFIG_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_SPL_MMC_SDHCI_ADMA=y
|
||||||
|
CONFIG_MMC_SDHCI_AM654=y
|
||||||
|
CONFIG_MTD=y
|
||||||
|
CONFIG_DM_MTD=y
|
||||||
|
CONFIG_MTD_SPI_NAND=y
|
||||||
|
CONFIG_DM_SPI_FLASH=y
|
||||||
|
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||||
|
CONFIG_SPI_FLASH_SOFT_RESET=y
|
||||||
|
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
|
||||||
|
CONFIG_SPI_FLASH_SPANSION=y
|
||||||
|
CONFIG_SPI_FLASH_S28HX_T=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
# CONFIG_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_SPL_PINCTRL=y
|
||||||
|
# CONFIG_SPL_PINCTRL_GENERIC is not set
|
||||||
|
CONFIG_PINCTRL_SINGLE=y
|
||||||
|
CONFIG_POWER_DOMAIN=y
|
||||||
|
CONFIG_TI_POWER_DOMAIN=y
|
||||||
|
CONFIG_K3_SYSTEM_CONTROLLER=y
|
||||||
|
CONFIG_REMOTEPROC_TI_K3_ARM64=y
|
||||||
|
CONFIG_RESET_TI_SCI=y
|
||||||
|
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||||
|
CONFIG_DM_SERIAL=y
|
||||||
|
CONFIG_SOC_DEVICE=y
|
||||||
|
CONFIG_SOC_DEVICE_TI_K3=y
|
||||||
|
CONFIG_SOC_TI=y
|
||||||
|
CONFIG_SPI=y
|
||||||
|
CONFIG_DM_SPI=y
|
||||||
|
CONFIG_CADENCE_QSPI=y
|
||||||
|
CONFIG_TIMER=y
|
||||||
|
CONFIG_SPL_TIMER=y
|
||||||
|
CONFIG_OMAP_TIMER=y
|
||||||
|
CONFIG_LIB_RATIONAL=y
|
||||||
|
CONFIG_SPL_LIB_RATIONAL=y
|
||||||
289
doc/board/ti/am62px_sk.rst
Normal file
289
doc/board/ti/am62px_sk.rst
Normal file
|
|
@ -0,0 +1,289 @@
|
||||||
|
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
||||||
|
.. sectionauthor:: Bryan Brattlof <bb@ti.com>
|
||||||
|
|
||||||
|
AM62Px Platforms
|
||||||
|
================
|
||||||
|
|
||||||
|
The AM62Px is an extension of the existing Sitara AM62x low-cost family
|
||||||
|
of application processors built for Automotive and Linux Application
|
||||||
|
development. Scalable Arm Cortex-A53 performance and embedded features,
|
||||||
|
such as: multi high-definition display support, 3D-graphics
|
||||||
|
acceleration, 4K video acceleration, and extensive peripherals make the
|
||||||
|
AM62Px well-suited for a broad range of automation and industrial
|
||||||
|
application, including automotive digital instrumentation, automotive
|
||||||
|
displays, industrial HMI, and more.
|
||||||
|
|
||||||
|
Some highlights of AM62P SoC are:
|
||||||
|
|
||||||
|
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
|
||||||
|
Dual/Single core variants are provided in the same package to allow HW
|
||||||
|
compatible designs.
|
||||||
|
|
||||||
|
* One Device manager Cortex-R5F for system power and resource
|
||||||
|
management, and one Cortex-R5F for Functional Safety or
|
||||||
|
general-purpose usage.
|
||||||
|
|
||||||
|
* One 3D GPU up to 50 GLFOPS
|
||||||
|
|
||||||
|
* H.264/H.265 Video Encode/Decode.
|
||||||
|
|
||||||
|
* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or
|
||||||
|
2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution
|
||||||
|
|
||||||
|
* Integrated Giga-bit Ethernet switch supporting up to a total of two
|
||||||
|
external ports (TSN capable).
|
||||||
|
|
||||||
|
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for
|
||||||
|
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
|
||||||
|
1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
|
||||||
|
|
||||||
|
* Dedicated Centralized Hardware Security Module with support for secure
|
||||||
|
boot, debug security and crypto acceleration and trusted execution
|
||||||
|
environment.
|
||||||
|
|
||||||
|
* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
|
||||||
|
|
||||||
|
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
|
||||||
|
enabling battery powered system design.
|
||||||
|
|
||||||
|
For those interested, more details about this SoC can be found in the
|
||||||
|
Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83
|
||||||
|
|
||||||
|
Boot Flow:
|
||||||
|
----------
|
||||||
|
|
||||||
|
The bootflow is exactly the same as all SoCs in the am62xxx extended SoC
|
||||||
|
family. Below is the pictorial representation:
|
||||||
|
|
||||||
|
.. image:: img/boot_diagram_k3_current.svg
|
||||||
|
:alt: Boot flow diagram
|
||||||
|
|
||||||
|
- Here TIFS acts as master and provides all the critical services. R5/A53
|
||||||
|
requests TIFS to get these services done as shown in the above diagram.
|
||||||
|
|
||||||
|
Sources:
|
||||||
|
--------
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_boot_sources
|
||||||
|
:end-before: .. k3_rst_include_end_boot_sources
|
||||||
|
|
||||||
|
Build procedure:
|
||||||
|
----------------
|
||||||
|
|
||||||
|
0. Setup the environment variables:
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_common_env_vars_desc
|
||||||
|
:end-before: .. k3_rst_include_end_common_env_vars_desc
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_board_env_vars_desc
|
||||||
|
:end-before: .. k3_rst_include_end_board_env_vars_desc
|
||||||
|
|
||||||
|
Set the variables corresponding to this platform:
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_common_env_vars_defn
|
||||||
|
:end-before: .. k3_rst_include_end_common_env_vars_defn
|
||||||
|
|
||||||
|
.. code-block:: bash
|
||||||
|
|
||||||
|
$ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig
|
||||||
|
$ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig
|
||||||
|
$ export TFA_BOARD=lite
|
||||||
|
$ # we dont use any extra TFA parameters
|
||||||
|
$ unset TFA_EXTRA_ARGS
|
||||||
|
$ export OPTEE_PLATFORM=k3-am62x
|
||||||
|
$ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
|
||||||
|
|
||||||
|
.. am62px_evm_rst_include_start_build_steps
|
||||||
|
|
||||||
|
1. Trusted Firmware-A:
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_build_steps_tfa
|
||||||
|
:end-before: .. k3_rst_include_end_build_steps_tfa
|
||||||
|
|
||||||
|
|
||||||
|
2. OP-TEE:
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_build_steps_optee
|
||||||
|
:end-before: .. k3_rst_include_end_build_steps_optee
|
||||||
|
|
||||||
|
3. U-Boot:
|
||||||
|
|
||||||
|
* 3.1 R5:
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_build_steps_spl_r5
|
||||||
|
:end-before: .. k3_rst_include_end_build_steps_spl_r5
|
||||||
|
|
||||||
|
* 3.2 A53:
|
||||||
|
|
||||||
|
.. include:: ../ti/k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_build_steps_uboot
|
||||||
|
:end-before: .. k3_rst_include_end_build_steps_uboot
|
||||||
|
.. am62px_evm_rst_include_end_build_steps
|
||||||
|
|
||||||
|
Target Images
|
||||||
|
--------------
|
||||||
|
|
||||||
|
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
|
||||||
|
variant (HS-FS, HS-SE) requires a different source for these files.
|
||||||
|
|
||||||
|
- HS-FS
|
||||||
|
|
||||||
|
* tiboot3-am62px-hs-fs-evm.bin from step 3.1
|
||||||
|
* tispl.bin, u-boot.img from step 3.2
|
||||||
|
|
||||||
|
- HS-SE
|
||||||
|
|
||||||
|
* tiboot3-am62px-hs-evm.bin from step 3.1
|
||||||
|
* tispl.bin, u-boot.img from step 3.2
|
||||||
|
|
||||||
|
Image formats:
|
||||||
|
--------------
|
||||||
|
|
||||||
|
- tiboot3.bin
|
||||||
|
|
||||||
|
.. image:: img/multi_cert_tiboot3.bin.svg
|
||||||
|
:alt: tiboot3.bin image format
|
||||||
|
|
||||||
|
- tispl.bin
|
||||||
|
|
||||||
|
.. image:: img/dm_tispl.bin.svg
|
||||||
|
:alt: tispl.bin image format
|
||||||
|
|
||||||
|
A53 SPL DDR Memory Layout
|
||||||
|
-------------------------
|
||||||
|
|
||||||
|
.. am62px_evm_rst_include_start_ddr_mem_layout
|
||||||
|
|
||||||
|
This provides an overview memory usage in A53 SPL stage.
|
||||||
|
|
||||||
|
.. list-table::
|
||||||
|
:widths: 16 16 16
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Region
|
||||||
|
- Start Address
|
||||||
|
- End Address
|
||||||
|
|
||||||
|
* - EMPTY
|
||||||
|
- 0x80000000
|
||||||
|
- 0x80080000
|
||||||
|
|
||||||
|
* - TEXT BASE
|
||||||
|
- 0x80080000
|
||||||
|
- 0x800d8000
|
||||||
|
|
||||||
|
* - EMPTY
|
||||||
|
- 0x800d8000
|
||||||
|
- 0x80200000
|
||||||
|
|
||||||
|
* - BMP IMAGE
|
||||||
|
- 0x80200000
|
||||||
|
- 0x80b77660
|
||||||
|
|
||||||
|
* - STACK
|
||||||
|
- 0x80b77660
|
||||||
|
- 0x80b77e60
|
||||||
|
|
||||||
|
* - GD
|
||||||
|
- 0x80b77e60
|
||||||
|
- 0x80b78000
|
||||||
|
|
||||||
|
* - MALLOC
|
||||||
|
- 0x80b78000
|
||||||
|
- 0x80b80000
|
||||||
|
|
||||||
|
* - EMPTY
|
||||||
|
- 0x80b80000
|
||||||
|
- 0x80c80000
|
||||||
|
|
||||||
|
* - BSS
|
||||||
|
- 0x80c80000
|
||||||
|
- 0x80d00000
|
||||||
|
|
||||||
|
* - BLOBS
|
||||||
|
- 0x80d00000
|
||||||
|
- 0x80d00400
|
||||||
|
|
||||||
|
* - EMPTY
|
||||||
|
- 0x80d00400
|
||||||
|
- 0x81000000
|
||||||
|
.. am62px_evm_rst_include_end_ddr_mem_layout
|
||||||
|
|
||||||
|
Switch Setting for Boot Mode
|
||||||
|
----------------------------
|
||||||
|
|
||||||
|
Boot Mode pins provide means to select the boot mode and options before the
|
||||||
|
device is powered up. After every POR, they are the main source to populate
|
||||||
|
the Boot Parameter Tables.
|
||||||
|
|
||||||
|
The following table shows some common boot modes used on AM62Px
|
||||||
|
platforms. More details can be found in the Technical Reference Manual:
|
||||||
|
https://www.ti.com/lit/pdf/spruj83 under the `Boot Mode Pins` section.
|
||||||
|
|
||||||
|
.. note::
|
||||||
|
|
||||||
|
This device is very new. Currently only UART boot is available while
|
||||||
|
we continue to add support for the other bootmodes.
|
||||||
|
|
||||||
|
.. list-table:: Boot Modes
|
||||||
|
:widths: 16 16 16
|
||||||
|
:header-rows: 1
|
||||||
|
|
||||||
|
* - Switch Label
|
||||||
|
- SW2: 12345678
|
||||||
|
- SW3: 12345678
|
||||||
|
|
||||||
|
* - SD
|
||||||
|
- 01000000
|
||||||
|
- 11000010
|
||||||
|
|
||||||
|
* - OSPI
|
||||||
|
- 00000000
|
||||||
|
- 11001110
|
||||||
|
|
||||||
|
* - EMMC
|
||||||
|
- 00000000
|
||||||
|
- 11010010
|
||||||
|
|
||||||
|
* - UART
|
||||||
|
- 00000000
|
||||||
|
- 11011100
|
||||||
|
|
||||||
|
* - USB DFU
|
||||||
|
- 00000000
|
||||||
|
- 11001010
|
||||||
|
|
||||||
|
For SW2 and SW1, the switch state in the "ON" position = 1.
|
||||||
|
|
||||||
|
Debugging U-Boot
|
||||||
|
----------------
|
||||||
|
|
||||||
|
See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
|
||||||
|
detailed setup information.
|
||||||
|
|
||||||
|
.. warning::
|
||||||
|
|
||||||
|
**OpenOCD support after**: v0.12.0
|
||||||
|
|
||||||
|
While support for the entire K3 generation including the am62xxx
|
||||||
|
extended family was added before v0.12.0, the tcl scripts for the
|
||||||
|
am62px have been accepted and will be available in the next release of
|
||||||
|
OpenOCD. It may be necessary to build OpenOCD from source depending on
|
||||||
|
the version your distribution has packaged.
|
||||||
|
|
||||||
|
.. include:: k3.rst
|
||||||
|
:start-after: .. k3_rst_include_start_openocd_connect_XDS110
|
||||||
|
:end-before: .. k3_rst_include_end_openocd_connect_XDS110
|
||||||
|
|
||||||
|
To start OpenOCD and connect to the board
|
||||||
|
|
||||||
|
.. code-block:: bash
|
||||||
|
|
||||||
|
openocd -f board/ti_am62pevm.cfg
|
||||||
|
|
@ -35,6 +35,7 @@ K3 Based SoCs
|
||||||
../beagle/am62x_beagleplay
|
../beagle/am62x_beagleplay
|
||||||
../phytec/phycore-am62x
|
../phytec/phycore-am62x
|
||||||
../toradex/verdin-am62
|
../toradex/verdin-am62
|
||||||
|
am62px_sk
|
||||||
am64x_evm
|
am64x_evm
|
||||||
am65x_evm
|
am65x_evm
|
||||||
j7200_evm
|
j7200_evm
|
||||||
|
|
|
||||||
|
|
@ -92,6 +92,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
|
||||||
.family = "J784S4",
|
.family = "J784S4",
|
||||||
.data = &j784s4_clk_platdata,
|
.data = &j784s4_clk_platdata,
|
||||||
},
|
},
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SOC_K3_AM62P5
|
||||||
|
{
|
||||||
|
.family = "AM62PX",
|
||||||
|
.data = &am62px_clk_platdata,
|
||||||
|
},
|
||||||
#endif
|
#endif
|
||||||
{ /* sentinel */ }
|
{ /* sentinel */ }
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -10,3 +10,5 @@ k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
|
||||||
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
|
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
|
||||||
k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
|
k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
|
||||||
k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o
|
k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o
|
||||||
|
k3-psil-data-$(CONFIG_SOC_K3_AM62P5) += k3-psil-am62p.o
|
||||||
|
k3-psil-data-$(CONFIG_SOC_K3_J722S) += k3-psil-am62p.o
|
||||||
|
|
|
||||||
325
drivers/dma/ti/k3-psil-am62p.c
Normal file
325
drivers/dma/ti/k3-psil-am62p.c
Normal file
|
|
@ -0,0 +1,325 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
|
||||||
|
#include "k3-psil-priv.h"
|
||||||
|
|
||||||
|
#define PSIL_PDMA_XY_TR(x) \
|
||||||
|
{ \
|
||||||
|
.thread_id = x, \
|
||||||
|
.ep_config = { \
|
||||||
|
.ep_type = PSIL_EP_PDMA_XY, \
|
||||||
|
.mapped_channel_id = -1, \
|
||||||
|
.default_flow_id = -1, \
|
||||||
|
}, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PSIL_PDMA_XY_PKT(x) \
|
||||||
|
{ \
|
||||||
|
.thread_id = x, \
|
||||||
|
.ep_config = { \
|
||||||
|
.ep_type = PSIL_EP_PDMA_XY, \
|
||||||
|
.mapped_channel_id = -1, \
|
||||||
|
.default_flow_id = -1, \
|
||||||
|
.pkt_mode = 1, \
|
||||||
|
}, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
|
||||||
|
{ \
|
||||||
|
.thread_id = x, \
|
||||||
|
.ep_config = { \
|
||||||
|
.ep_type = PSIL_EP_NATIVE, \
|
||||||
|
.pkt_mode = 1, \
|
||||||
|
.needs_epib = 1, \
|
||||||
|
.psd_size = 16, \
|
||||||
|
.mapped_channel_id = ch, \
|
||||||
|
.flow_start = flow_base, \
|
||||||
|
.flow_num = flow_cnt, \
|
||||||
|
.default_flow_id = flow_base, \
|
||||||
|
}, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
|
||||||
|
{ \
|
||||||
|
.thread_id = x, \
|
||||||
|
.ep_config = { \
|
||||||
|
.ep_type = PSIL_EP_NATIVE, \
|
||||||
|
.pkt_mode = 1, \
|
||||||
|
.needs_epib = 1, \
|
||||||
|
.psd_size = 64, \
|
||||||
|
.mapped_channel_id = ch, \
|
||||||
|
.flow_start = flow_base, \
|
||||||
|
.flow_num = flow_cnt, \
|
||||||
|
.default_flow_id = default_flow, \
|
||||||
|
.notdpkt = tx, \
|
||||||
|
}, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PSIL_PDMA_MCASP(x) \
|
||||||
|
{ \
|
||||||
|
.thread_id = x, \
|
||||||
|
.ep_config = { \
|
||||||
|
.ep_type = PSIL_EP_PDMA_XY, \
|
||||||
|
.pdma_acc32 = 1, \
|
||||||
|
.pdma_burst = 1, \
|
||||||
|
}, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PSIL_CSI2RX(x) \
|
||||||
|
{ \
|
||||||
|
.thread_id = x, \
|
||||||
|
.ep_config = { \
|
||||||
|
.ep_type = PSIL_EP_NATIVE, \
|
||||||
|
}, \
|
||||||
|
}
|
||||||
|
|
||||||
|
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
|
||||||
|
static struct psil_ep am62p_src_ep_map[] = {
|
||||||
|
/* SAUL */
|
||||||
|
PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
|
||||||
|
PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
|
||||||
|
PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
|
||||||
|
PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
|
||||||
|
/* PDMA_MAIN0 - SPI0-3 */
|
||||||
|
PSIL_PDMA_XY_PKT(0x4302),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4303),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4304),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4305),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4306),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4307),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4308),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4309),
|
||||||
|
PSIL_PDMA_XY_PKT(0x430a),
|
||||||
|
PSIL_PDMA_XY_PKT(0x430b),
|
||||||
|
PSIL_PDMA_XY_PKT(0x430c),
|
||||||
|
PSIL_PDMA_XY_PKT(0x430d),
|
||||||
|
/* PDMA_MAIN1 - UART0-6 */
|
||||||
|
PSIL_PDMA_XY_PKT(0x4400),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4401),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4402),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4403),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4404),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4405),
|
||||||
|
PSIL_PDMA_XY_PKT(0x4406),
|
||||||
|
/* PDMA_MAIN2 - MCASP0-2 */
|
||||||
|
PSIL_PDMA_MCASP(0x4500),
|
||||||
|
PSIL_PDMA_MCASP(0x4501),
|
||||||
|
PSIL_PDMA_MCASP(0x4502),
|
||||||
|
/* CPSW3G */
|
||||||
|
PSIL_ETHERNET(0x4600, 19, 19, 16),
|
||||||
|
/* CSI2RX */
|
||||||
|
PSIL_CSI2RX(0x5000),
|
||||||
|
PSIL_CSI2RX(0x5001),
|
||||||
|
PSIL_CSI2RX(0x5002),
|
||||||
|
PSIL_CSI2RX(0x5003),
|
||||||
|
PSIL_CSI2RX(0x5004),
|
||||||
|
PSIL_CSI2RX(0x5005),
|
||||||
|
PSIL_CSI2RX(0x5006),
|
||||||
|
PSIL_CSI2RX(0x5007),
|
||||||
|
PSIL_CSI2RX(0x5008),
|
||||||
|
PSIL_CSI2RX(0x5009),
|
||||||
|
PSIL_CSI2RX(0x500a),
|
||||||
|
PSIL_CSI2RX(0x500b),
|
||||||
|
PSIL_CSI2RX(0x500c),
|
||||||
|
PSIL_CSI2RX(0x500d),
|
||||||
|
PSIL_CSI2RX(0x500e),
|
||||||
|
PSIL_CSI2RX(0x500f),
|
||||||
|
PSIL_CSI2RX(0x5010),
|
||||||
|
PSIL_CSI2RX(0x5011),
|
||||||
|
PSIL_CSI2RX(0x5012),
|
||||||
|
PSIL_CSI2RX(0x5013),
|
||||||
|
PSIL_CSI2RX(0x5014),
|
||||||
|
PSIL_CSI2RX(0x5015),
|
||||||
|
PSIL_CSI2RX(0x5016),
|
||||||
|
PSIL_CSI2RX(0x5017),
|
||||||
|
PSIL_CSI2RX(0x5018),
|
||||||
|
PSIL_CSI2RX(0x5019),
|
||||||
|
PSIL_CSI2RX(0x501a),
|
||||||
|
PSIL_CSI2RX(0x501b),
|
||||||
|
PSIL_CSI2RX(0x501c),
|
||||||
|
PSIL_CSI2RX(0x501d),
|
||||||
|
PSIL_CSI2RX(0x501e),
|
||||||
|
PSIL_CSI2RX(0x501f),
|
||||||
|
PSIL_CSI2RX(0x5000),
|
||||||
|
PSIL_CSI2RX(0x5001),
|
||||||
|
PSIL_CSI2RX(0x5002),
|
||||||
|
PSIL_CSI2RX(0x5003),
|
||||||
|
PSIL_CSI2RX(0x5004),
|
||||||
|
PSIL_CSI2RX(0x5005),
|
||||||
|
PSIL_CSI2RX(0x5006),
|
||||||
|
PSIL_CSI2RX(0x5007),
|
||||||
|
PSIL_CSI2RX(0x5008),
|
||||||
|
PSIL_CSI2RX(0x5009),
|
||||||
|
PSIL_CSI2RX(0x500a),
|
||||||
|
PSIL_CSI2RX(0x500b),
|
||||||
|
PSIL_CSI2RX(0x500c),
|
||||||
|
PSIL_CSI2RX(0x500d),
|
||||||
|
PSIL_CSI2RX(0x500e),
|
||||||
|
PSIL_CSI2RX(0x500f),
|
||||||
|
PSIL_CSI2RX(0x5010),
|
||||||
|
PSIL_CSI2RX(0x5011),
|
||||||
|
PSIL_CSI2RX(0x5012),
|
||||||
|
PSIL_CSI2RX(0x5013),
|
||||||
|
PSIL_CSI2RX(0x5014),
|
||||||
|
PSIL_CSI2RX(0x5015),
|
||||||
|
PSIL_CSI2RX(0x5016),
|
||||||
|
PSIL_CSI2RX(0x5017),
|
||||||
|
PSIL_CSI2RX(0x5018),
|
||||||
|
PSIL_CSI2RX(0x5019),
|
||||||
|
PSIL_CSI2RX(0x501a),
|
||||||
|
PSIL_CSI2RX(0x501b),
|
||||||
|
PSIL_CSI2RX(0x501c),
|
||||||
|
PSIL_CSI2RX(0x501d),
|
||||||
|
PSIL_CSI2RX(0x501e),
|
||||||
|
PSIL_CSI2RX(0x501f),
|
||||||
|
/* CSIRX 1-3 (only for J722S) */
|
||||||
|
PSIL_CSI2RX(0x5100),
|
||||||
|
PSIL_CSI2RX(0x5101),
|
||||||
|
PSIL_CSI2RX(0x5102),
|
||||||
|
PSIL_CSI2RX(0x5103),
|
||||||
|
PSIL_CSI2RX(0x5104),
|
||||||
|
PSIL_CSI2RX(0x5105),
|
||||||
|
PSIL_CSI2RX(0x5106),
|
||||||
|
PSIL_CSI2RX(0x5107),
|
||||||
|
PSIL_CSI2RX(0x5108),
|
||||||
|
PSIL_CSI2RX(0x5109),
|
||||||
|
PSIL_CSI2RX(0x510a),
|
||||||
|
PSIL_CSI2RX(0x510b),
|
||||||
|
PSIL_CSI2RX(0x510c),
|
||||||
|
PSIL_CSI2RX(0x510d),
|
||||||
|
PSIL_CSI2RX(0x510e),
|
||||||
|
PSIL_CSI2RX(0x510f),
|
||||||
|
PSIL_CSI2RX(0x5110),
|
||||||
|
PSIL_CSI2RX(0x5111),
|
||||||
|
PSIL_CSI2RX(0x5112),
|
||||||
|
PSIL_CSI2RX(0x5113),
|
||||||
|
PSIL_CSI2RX(0x5114),
|
||||||
|
PSIL_CSI2RX(0x5115),
|
||||||
|
PSIL_CSI2RX(0x5116),
|
||||||
|
PSIL_CSI2RX(0x5117),
|
||||||
|
PSIL_CSI2RX(0x5118),
|
||||||
|
PSIL_CSI2RX(0x5119),
|
||||||
|
PSIL_CSI2RX(0x511a),
|
||||||
|
PSIL_CSI2RX(0x511b),
|
||||||
|
PSIL_CSI2RX(0x511c),
|
||||||
|
PSIL_CSI2RX(0x511d),
|
||||||
|
PSIL_CSI2RX(0x511e),
|
||||||
|
PSIL_CSI2RX(0x511f),
|
||||||
|
PSIL_CSI2RX(0x5200),
|
||||||
|
PSIL_CSI2RX(0x5201),
|
||||||
|
PSIL_CSI2RX(0x5202),
|
||||||
|
PSIL_CSI2RX(0x5203),
|
||||||
|
PSIL_CSI2RX(0x5204),
|
||||||
|
PSIL_CSI2RX(0x5205),
|
||||||
|
PSIL_CSI2RX(0x5206),
|
||||||
|
PSIL_CSI2RX(0x5207),
|
||||||
|
PSIL_CSI2RX(0x5208),
|
||||||
|
PSIL_CSI2RX(0x5209),
|
||||||
|
PSIL_CSI2RX(0x520a),
|
||||||
|
PSIL_CSI2RX(0x520b),
|
||||||
|
PSIL_CSI2RX(0x520c),
|
||||||
|
PSIL_CSI2RX(0x520d),
|
||||||
|
PSIL_CSI2RX(0x520e),
|
||||||
|
PSIL_CSI2RX(0x520f),
|
||||||
|
PSIL_CSI2RX(0x5210),
|
||||||
|
PSIL_CSI2RX(0x5211),
|
||||||
|
PSIL_CSI2RX(0x5212),
|
||||||
|
PSIL_CSI2RX(0x5213),
|
||||||
|
PSIL_CSI2RX(0x5214),
|
||||||
|
PSIL_CSI2RX(0x5215),
|
||||||
|
PSIL_CSI2RX(0x5216),
|
||||||
|
PSIL_CSI2RX(0x5217),
|
||||||
|
PSIL_CSI2RX(0x5218),
|
||||||
|
PSIL_CSI2RX(0x5219),
|
||||||
|
PSIL_CSI2RX(0x521a),
|
||||||
|
PSIL_CSI2RX(0x521b),
|
||||||
|
PSIL_CSI2RX(0x521c),
|
||||||
|
PSIL_CSI2RX(0x521d),
|
||||||
|
PSIL_CSI2RX(0x521e),
|
||||||
|
PSIL_CSI2RX(0x521f),
|
||||||
|
PSIL_CSI2RX(0x5300),
|
||||||
|
PSIL_CSI2RX(0x5301),
|
||||||
|
PSIL_CSI2RX(0x5302),
|
||||||
|
PSIL_CSI2RX(0x5303),
|
||||||
|
PSIL_CSI2RX(0x5304),
|
||||||
|
PSIL_CSI2RX(0x5305),
|
||||||
|
PSIL_CSI2RX(0x5306),
|
||||||
|
PSIL_CSI2RX(0x5307),
|
||||||
|
PSIL_CSI2RX(0x5308),
|
||||||
|
PSIL_CSI2RX(0x5309),
|
||||||
|
PSIL_CSI2RX(0x530a),
|
||||||
|
PSIL_CSI2RX(0x530b),
|
||||||
|
PSIL_CSI2RX(0x530c),
|
||||||
|
PSIL_CSI2RX(0x530d),
|
||||||
|
PSIL_CSI2RX(0x530e),
|
||||||
|
PSIL_CSI2RX(0x530f),
|
||||||
|
PSIL_CSI2RX(0x5310),
|
||||||
|
PSIL_CSI2RX(0x5311),
|
||||||
|
PSIL_CSI2RX(0x5312),
|
||||||
|
PSIL_CSI2RX(0x5313),
|
||||||
|
PSIL_CSI2RX(0x5314),
|
||||||
|
PSIL_CSI2RX(0x5315),
|
||||||
|
PSIL_CSI2RX(0x5316),
|
||||||
|
PSIL_CSI2RX(0x5317),
|
||||||
|
PSIL_CSI2RX(0x5318),
|
||||||
|
PSIL_CSI2RX(0x5319),
|
||||||
|
PSIL_CSI2RX(0x531a),
|
||||||
|
PSIL_CSI2RX(0x531b),
|
||||||
|
PSIL_CSI2RX(0x531c),
|
||||||
|
PSIL_CSI2RX(0x531d),
|
||||||
|
PSIL_CSI2RX(0x531e),
|
||||||
|
PSIL_CSI2RX(0x531f),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
|
||||||
|
static struct psil_ep am62p_dst_ep_map[] = {
|
||||||
|
/* SAUL */
|
||||||
|
PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
|
||||||
|
PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
|
||||||
|
/* PDMA_MAIN0 - SPI0-3 */
|
||||||
|
PSIL_PDMA_XY_PKT(0xc302),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc303),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc304),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc305),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc306),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc307),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc308),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc309),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc30a),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc30b),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc30c),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc30d),
|
||||||
|
/* PDMA_MAIN1 - UART0-6 */
|
||||||
|
PSIL_PDMA_XY_PKT(0xc400),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc401),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc402),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc403),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc404),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc405),
|
||||||
|
PSIL_PDMA_XY_PKT(0xc406),
|
||||||
|
/* PDMA_MAIN2 - MCASP0-2 */
|
||||||
|
PSIL_PDMA_MCASP(0xc500),
|
||||||
|
PSIL_PDMA_MCASP(0xc501),
|
||||||
|
PSIL_PDMA_MCASP(0xc502),
|
||||||
|
/* CPSW3G */
|
||||||
|
PSIL_ETHERNET(0xc600, 19, 19, 8),
|
||||||
|
PSIL_ETHERNET(0xc601, 20, 27, 8),
|
||||||
|
PSIL_ETHERNET(0xc602, 21, 35, 8),
|
||||||
|
PSIL_ETHERNET(0xc603, 22, 43, 8),
|
||||||
|
PSIL_ETHERNET(0xc604, 23, 51, 8),
|
||||||
|
PSIL_ETHERNET(0xc605, 24, 59, 8),
|
||||||
|
PSIL_ETHERNET(0xc606, 25, 67, 8),
|
||||||
|
PSIL_ETHERNET(0xc607, 26, 75, 8),
|
||||||
|
};
|
||||||
|
|
||||||
|
struct psil_ep_map am62p_ep_map = {
|
||||||
|
.name = "am62p",
|
||||||
|
.src = am62p_src_ep_map,
|
||||||
|
.src_count = ARRAY_SIZE(am62p_src_ep_map),
|
||||||
|
.dst = am62p_dst_ep_map,
|
||||||
|
.dst_count = ARRAY_SIZE(am62p_dst_ep_map),
|
||||||
|
};
|
||||||
|
|
@ -44,5 +44,6 @@ extern struct psil_ep_map am64_ep_map;
|
||||||
extern struct psil_ep_map am62_ep_map;
|
extern struct psil_ep_map am62_ep_map;
|
||||||
extern struct psil_ep_map am62a_ep_map;
|
extern struct psil_ep_map am62a_ep_map;
|
||||||
extern struct psil_ep_map j784s4_ep_map;
|
extern struct psil_ep_map j784s4_ep_map;
|
||||||
|
extern struct psil_ep_map am62p_ep_map;
|
||||||
|
|
||||||
#endif /* K3_PSIL_PRIV_H_ */
|
#endif /* K3_PSIL_PRIV_H_ */
|
||||||
|
|
|
||||||
|
|
@ -30,6 +30,10 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
|
||||||
soc_ep_map = &am62a_ep_map;
|
soc_ep_map = &am62a_ep_map;
|
||||||
else if (IS_ENABLED(CONFIG_SOC_K3_J784S4))
|
else if (IS_ENABLED(CONFIG_SOC_K3_J784S4))
|
||||||
soc_ep_map = &j784s4_ep_map;
|
soc_ep_map = &j784s4_ep_map;
|
||||||
|
else if (IS_ENABLED(CONFIG_SOC_K3_AM62P5))
|
||||||
|
soc_ep_map = &am62p_ep_map;
|
||||||
|
else if (IS_ENABLED(CONFIG_SOC_K3_J722S))
|
||||||
|
soc_ep_map = &am62p_ep_map;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
|
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
|
||||||
|
|
|
||||||
|
|
@ -84,7 +84,8 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
|
||||||
};
|
};
|
||||||
#endif /* CONFIG_SOC_K3_J721S2 */
|
#endif /* CONFIG_SOC_K3_J721S2 */
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7)
|
#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
|
||||||
|
IS_ENABLED(CONFIG_SOC_K3_AM62P5)
|
||||||
static struct ti_sci_resource_static_data rm_static_data[] = {
|
static struct ti_sci_resource_static_data rm_static_data[] = {
|
||||||
/* BC channels */
|
/* BC channels */
|
||||||
{
|
{
|
||||||
|
|
@ -95,7 +96,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
|
||||||
},
|
},
|
||||||
{ },
|
{ },
|
||||||
};
|
};
|
||||||
#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
|
#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || CONFIG_SOC_K3_AM62P5 */
|
||||||
|
|
||||||
#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
|
#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
|
||||||
static struct ti_sci_resource_static_data rm_static_data[] = {
|
static struct ti_sci_resource_static_data rm_static_data[] = {
|
||||||
|
|
|
||||||
|
|
@ -81,29 +81,36 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
|
||||||
.family = "J7200",
|
.family = "J7200",
|
||||||
.data = &j7200_pd_platdata,
|
.data = &j7200_pd_platdata,
|
||||||
},
|
},
|
||||||
#elif CONFIG_SOC_K3_J721S2
|
#endif
|
||||||
|
#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
|
||||||
{
|
{
|
||||||
.family = "J721S2",
|
.family = "J721S2",
|
||||||
.data = &j721s2_pd_platdata,
|
.data = &j721s2_pd_platdata,
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_SOC_K3_AM625
|
#if IS_ENABLED(CONFIG_SOC_K3_AM625)
|
||||||
{
|
{
|
||||||
.family = "AM62X",
|
.family = "AM62X",
|
||||||
.data = &am62x_pd_platdata,
|
.data = &am62x_pd_platdata,
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_SOC_K3_AM62A7
|
#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
|
||||||
{
|
{
|
||||||
.family = "AM62AX",
|
.family = "AM62AX",
|
||||||
.data = &am62ax_pd_platdata,
|
.data = &am62ax_pd_platdata,
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_SOC_K3_J784S4
|
#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
|
||||||
{
|
{
|
||||||
.family = "J784S4",
|
.family = "J784S4",
|
||||||
.data = &j784s4_pd_platdata,
|
.data = &j784s4_pd_platdata,
|
||||||
},
|
},
|
||||||
|
#endif
|
||||||
|
#if IS_ENABLED(CONFIG_SOC_K3_AM62P5)
|
||||||
|
{
|
||||||
|
.family = "AM62PX",
|
||||||
|
.data = &am62px_pd_platdata,
|
||||||
|
},
|
||||||
#endif
|
#endif
|
||||||
{ /* sentinel */ }
|
{ /* sentinel */ }
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -65,7 +65,7 @@ choice
|
||||||
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
|
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
|
||||||
default K3_AM64_DDRSS if SOC_K3_AM642
|
default K3_AM64_DDRSS if SOC_K3_AM642
|
||||||
default K3_AM64_DDRSS if SOC_K3_AM625
|
default K3_AM64_DDRSS if SOC_K3_AM625
|
||||||
default K3_AM62A_DDRSS if SOC_K3_AM62A7
|
default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5
|
||||||
|
|
||||||
config K3_J721E_DDRSS
|
config K3_J721E_DDRSS
|
||||||
bool "Enable J721E DDRSS support"
|
bool "Enable J721E DDRSS support"
|
||||||
|
|
|
||||||
|
|
@ -48,6 +48,9 @@ static const char *get_family_string(u32 idreg)
|
||||||
case JTAG_ID_PARTNO_J784S4:
|
case JTAG_ID_PARTNO_J784S4:
|
||||||
family = "J784S4";
|
family = "J784S4";
|
||||||
break;
|
break;
|
||||||
|
case JTAG_ID_PARTNO_AM62PX:
|
||||||
|
family = "AM62PX";
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
family = "Unknown Silicon";
|
family = "Unknown Silicon";
|
||||||
};
|
};
|
||||||
|
|
|
||||||
14
include/configs/am62px_evm.h
Normal file
14
include/configs/am62px_evm.h
Normal file
|
|
@ -0,0 +1,14 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Configuration header file for K3 AM62Px SoC family
|
||||||
|
*
|
||||||
|
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_AM62PX_EVM_H
|
||||||
|
#define __CONFIG_AM62PX_EVM_H
|
||||||
|
|
||||||
|
/* Now for the remaining common defines */
|
||||||
|
#include <configs/ti_armv7_common.h>
|
||||||
|
|
||||||
|
#endif /* __CONFIG_AM62PX_EVM_H */
|
||||||
|
|
@ -177,6 +177,7 @@ extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
|
||||||
extern const struct ti_k3_clk_platdata am62x_clk_platdata;
|
extern const struct ti_k3_clk_platdata am62x_clk_platdata;
|
||||||
extern const struct ti_k3_clk_platdata am62ax_clk_platdata;
|
extern const struct ti_k3_clk_platdata am62ax_clk_platdata;
|
||||||
extern const struct ti_k3_clk_platdata j784s4_clk_platdata;
|
extern const struct ti_k3_clk_platdata j784s4_clk_platdata;
|
||||||
|
extern const struct ti_k3_clk_platdata am62px_clk_platdata;
|
||||||
|
|
||||||
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
|
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
|
||||||
void __iomem *reg);
|
void __iomem *reg);
|
||||||
|
|
|
||||||
|
|
@ -81,6 +81,7 @@ extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
|
||||||
extern const struct ti_k3_pd_platdata am62x_pd_platdata;
|
extern const struct ti_k3_pd_platdata am62x_pd_platdata;
|
||||||
extern const struct ti_k3_pd_platdata am62ax_pd_platdata;
|
extern const struct ti_k3_pd_platdata am62ax_pd_platdata;
|
||||||
extern const struct ti_k3_pd_platdata j784s4_pd_platdata;
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extern const struct ti_k3_pd_platdata j784s4_pd_platdata;
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extern const struct ti_k3_pd_platdata am62px_pd_platdata;
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|
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||||||
u8 ti_pd_state(struct ti_pd *pd);
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u8 ti_pd_state(struct ti_pd *pd);
|
||||||
u8 lpsc_get_state(struct ti_lpsc *lpsc);
|
u8 lpsc_get_state(struct ti_lpsc *lpsc);
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue