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Merge patch series "Fix MMC tuning algorithm"
Judith Mendez <jm@ti.com> says: The following patch series includes a MMC tuning algorithm fix according to the following published paper [0]. This seris also includes fixes for OTAP/ITAP delay values in j721e_4bit_sdhci_set_ios_post and for HS400 mode. For DDR52 mode, also set ENDLL=1 and call am654_sdhci_setup_dll() instead of am654_sdhci_setup_delay_chain() according to device datasheet[1]. [0] https://www.ti.com/lit/an/spract9/spract9.pdf [1] https://www.ti.com/lit/ds/symlink/am62p.pdf
This commit is contained in:
Tom Rini
commit
1e4fe21860
1 changed files with 140 additions and 32 deletions
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@ -85,6 +85,8 @@
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#define AM654_SDHCI_MIN_FREQ 400000
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#define CLOCK_TOO_SLOW_HZ 50000000
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#define ENABLE 0x1
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struct am654_sdhci_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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@ -92,11 +94,13 @@ struct am654_sdhci_plat {
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bool non_removable;
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u32 otap_del_sel[MMC_MODES_END];
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u32 itap_del_sel[MMC_MODES_END];
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u32 itap_del_ena[MMC_MODES_END];
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u32 trm_icp;
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u32 drv_strength;
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u32 strb_sel;
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u32 clkbuf_sel;
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u32 flags;
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bool dll_enable;
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#define DLL_PRESENT BIT(0)
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#define IOMUX_PRESENT BIT(1)
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#define FREQSEL_2_BIT BIT(2)
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@ -110,6 +114,12 @@ struct timing_data {
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u32 capability;
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};
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struct window {
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u8 start;
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u8 end;
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u8 length;
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};
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static const struct timing_data td[] = {
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[MMC_LEGACY] = {"ti,otap-del-sel-legacy",
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"ti,itap-del-sel-legacy",
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@ -216,8 +226,10 @@ static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
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}
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static void am654_sdhci_write_itapdly(struct am654_sdhci_plat *plat,
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u32 itapdly)
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u32 itapdly, u32 enable)
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{
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
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enable << ITAPDLYENA_SHIFT);
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/* Set ITAPCHGWIN before writing to ITAPDLY */
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
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1 << ITAPCHGWIN_SHIFT);
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@ -235,7 +247,8 @@ static void am654_sdhci_setup_delay_chain(struct am654_sdhci_plat *plat,
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mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
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regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
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am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode]);
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am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
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plat->itap_del_ena[mode]);
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}
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static int am654_sdhci_set_ios_post(struct sdhci_host *host)
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@ -276,12 +289,22 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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if (mode > UHS_SDR25 && speed >= CLOCK_TOO_SLOW_HZ) {
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if ((mode > UHS_SDR25 || mode == MMC_DDR_52) && speed >= CLOCK_TOO_SLOW_HZ) {
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ret = am654_sdhci_setup_dll(plat, speed);
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if (ret)
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return ret;
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plat->dll_enable = true;
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if (mode == MMC_HS_400) {
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plat->itap_del_ena[mode] = ENABLE;
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plat->itap_del_sel[mode] = plat->itap_del_sel[mode - 1];
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}
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am654_sdhci_write_itapdly(plat, plat->itap_del_sel[mode],
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plat->itap_del_ena[mode]);
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} else {
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am654_sdhci_setup_delay_chain(plat, mode);
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plat->dll_enable = false;
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}
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regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
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@ -375,39 +398,103 @@ static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
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writeb(val, host->ioaddr + reg);
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}
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#ifdef MMC_SUPPORTS_TUNING
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#define ITAP_MAX 32
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#define ITAPDLY_LENGTH 32
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#define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
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static u32 am654_sdhci_calculate_itap(struct udevice *dev, struct window
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*fail_window, u8 num_fails, bool circular_buffer)
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{
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u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
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u8 first_fail_start = 0, last_fail_end = 0;
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struct window pass_window = {0, 0, 0};
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int prev_fail_end = -1;
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u8 i;
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if (!num_fails)
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return ITAPDLY_LAST_INDEX >> 1;
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if (fail_window->length == ITAPDLY_LENGTH) {
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dev_err(dev, "No passing ITAPDLY, return 0\n");
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return 0;
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}
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first_fail_start = fail_window->start;
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last_fail_end = fail_window[num_fails - 1].end;
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for (i = 0; i < num_fails; i++) {
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start_fail = fail_window[i].start;
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end_fail = fail_window[i].end;
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pass_length = start_fail - (prev_fail_end + 1);
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if (pass_length > pass_window.length) {
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pass_window.start = prev_fail_end + 1;
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pass_window.length = pass_length;
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}
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prev_fail_end = end_fail;
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}
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if (!circular_buffer)
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pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
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else
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pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
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if (pass_length > pass_window.length) {
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pass_window.start = last_fail_end + 1;
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pass_window.length = pass_length;
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}
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if (!circular_buffer)
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itap = pass_window.start + (pass_window.length >> 1);
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else
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itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
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return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
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}
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static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
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{
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struct udevice *dev = mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_plat(dev);
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int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
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u32 itap;
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struct window fail_window[ITAPDLY_LENGTH];
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int mode = mmc->selected_mode;
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u8 curr_pass, itap;
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u8 fail_index = 0;
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u8 prev_pass = 1;
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memset(fail_window, 0, sizeof(fail_window));
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/* Enable ITAPDLY */
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
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1 << ITAPDLYENA_SHIFT);
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plat->itap_del_ena[mode] = ENABLE;
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for (itap = 0; itap < ITAP_MAX; itap++) {
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am654_sdhci_write_itapdly(plat, itap);
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for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
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am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
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cur_val = !mmc_send_tuning(mmc, opcode);
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if (cur_val && !prev_val)
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pass_window = itap;
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curr_pass = !mmc_send_tuning(mmc, opcode);
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if (!cur_val)
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fail_len++;
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if (!curr_pass && prev_pass)
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fail_window[fail_index].start = itap;
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prev_val = cur_val;
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if (!curr_pass) {
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fail_window[fail_index].end = itap;
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fail_window[fail_index].length++;
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}
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/*
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* Having determined the length of the failing window and start of
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* the passing window calculate the length of the passing window and
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* set the final value halfway through it considering the range as a
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* circular buffer
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*/
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pass_len = ITAP_MAX - fail_len;
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itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
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am654_sdhci_write_itapdly(plat, itap);
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if (curr_pass && !prev_pass)
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fail_index++;
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prev_pass = curr_pass;
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}
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if (fail_window[fail_index].length != 0)
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fail_index++;
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itap = am654_sdhci_calculate_itap(dev, fail_window, fail_index,
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plat->dll_enable);
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/* Save ITAPDLY */
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plat->itap_del_sel[mode] = itap;
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am654_sdhci_write_itapdly(plat, itap, plat->itap_del_ena[mode]);
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return 0;
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}
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@ -442,12 +529,29 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
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{
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struct udevice *dev = host->mmc->dev;
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struct am654_sdhci_plat *plat = dev_get_plat(dev);
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u32 otap_del_sel, mask, val;
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int mode = host->mmc->selected_mode;
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u32 otap_del_sel;
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u32 itap_del_ena;
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u32 itap_del_sel;
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u32 mask, val;
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otap_del_sel = plat->otap_del_sel[mode];
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otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
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mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
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val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
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val = (1 << OTAPDLYENA_SHIFT) |
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(otap_del_sel << OTAPDLYSEL_SHIFT);
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itap_del_ena = plat->itap_del_ena[mode];
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itap_del_sel = plat->itap_del_sel[mode];
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mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
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val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
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(itap_del_sel << ITAPDLYSEL_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK,
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1 << ITAPCHGWIN_SHIFT);
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regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
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regmap_update_bits(plat->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
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regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
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plat->clkbuf_sel);
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@ -501,7 +605,7 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev,
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* Remove the corresponding capability if an otap-del-sel
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* value is not found
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*/
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for (i = MMC_HS; i <= MMC_HS_400; i++) {
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for (i = MMC_LEGACY; i <= MMC_HS_400; i++) {
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ret = dev_read_u32(dev, td[i].otap_binding,
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&plat->otap_del_sel[i]);
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if (ret) {
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@ -513,9 +617,13 @@ static int sdhci_am654_get_otap_delay(struct udevice *dev,
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cfg->host_caps &= ~td[i].capability;
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}
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if (td[i].itap_binding)
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dev_read_u32(dev, td[i].itap_binding,
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if (td[i].itap_binding) {
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ret = dev_read_u32(dev, td[i].itap_binding,
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&plat->itap_del_sel[i]);
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if (!ret)
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plat->itap_del_ena[i] = ENABLE;
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}
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}
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return 0;
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