Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-22 12:54:37 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

arm64: memset-arm64: Use simple memset when cache is disabled

Browse source 
The optimized memset uses the dc opcode, which causes problems when the
cache is disabled. This patch adds a check if the cache is disabled and
uses a very simple memset implementation in this case. Otherwise the
optimized version is used.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2021-09-02 17:00:18 +02:00 • committed by Tom Rini
parent dbf6b14e0a
commit 1e43bb6732
1 changed files with 32 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
arch/arm/lib/memset-arm64.S
View file

@ -11,6 +11,7 @@
* *
*/ */
#include <asm/macro.h>
#include "asmdefs.h" #include "asmdefs.h"
#define dstin x0 #define dstin x0
@ -25,6 +26,37 @@ ENTRY (memset)
PTR_ARG (0) PTR_ARG (0)
SIZE_ARG (2) SIZE_ARG (2)
/*
* The optimized memset uses the dc opcode, which causes problems
* when the cache is disabled. Let's check if the cache is disabled
* and use a very simple memset implementation in this case. Otherwise
* jump to the optimized version.
*/
switch_el x6, 3f, 2f, 1f
3: mrs x6, sctlr_el3
b 0f
2: mrs x6, sctlr_el2
b 0f
1: mrs x6, sctlr_el1
0:
tst x6, #CR_C
bne 9f
/*
* A very "simple" memset implementation without the use of the
* dc opcode. Can be run with caches disabled.
*/
mov x3, #0x0
cmp count, x3 /* check for zero length */
beq 8f
4: strb valw, [dstin, x3]
add x3, x3, #0x1
cmp count, x3
bne 4b
8: ret
9:
/* Here the optimized memset version starts */
dup v0.16B, valw dup v0.16B, valw
add dstend, dstin, count add dstend, dstin, count