mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-26 07:17:10 +00:00
ppc: Remove sbc8641d board
This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. This is also the last of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well. Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
parent
ed7fe2bee1
commit
1c58857ad7
41 changed files with 6 additions and 5091 deletions
|
|
@ -417,7 +417,7 @@ jobs:
|
||||||
t208xrdb_corenet_ds:
|
t208xrdb_corenet_ds:
|
||||||
BUILDMAN: "t208xrdb corenet_ds"
|
BUILDMAN: "t208xrdb corenet_ds"
|
||||||
fsl_ppc:
|
fsl_ppc:
|
||||||
BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
|
BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
|
||||||
t102x:
|
t102x:
|
||||||
BUILDMAN: "t102*"
|
BUILDMAN: "t102*"
|
||||||
p1_p2_rdb_pc:
|
p1_p2_rdb_pc:
|
||||||
|
|
|
||||||
|
|
@ -1002,12 +1002,6 @@ S: Maintained
|
||||||
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
|
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
|
||||||
F: arch/powerpc/cpu/mpc85xx/
|
F: arch/powerpc/cpu/mpc85xx/
|
||||||
|
|
||||||
POWERPC MPC86XX
|
|
||||||
M: Priyanka Jain <priyanka.jain@nxp.com>
|
|
||||||
S: Maintained
|
|
||||||
T: git https://source.denx.de/u-boot/custodians/u-boot-mpc86xx.git
|
|
||||||
F: arch/powerpc/cpu/mpc86xx/
|
|
||||||
|
|
||||||
RISC-V
|
RISC-V
|
||||||
M: Rick Chen <rick@andestech.com>
|
M: Rick Chen <rick@andestech.com>
|
||||||
M: Leo <ycliang@andestech.com>
|
M: Leo <ycliang@andestech.com>
|
||||||
|
|
|
||||||
3
README
3
README
|
|
@ -423,8 +423,7 @@ The following options need to be configured:
|
||||||
|
|
||||||
CONFIG_SYS_FSL_DDR
|
CONFIG_SYS_FSL_DDR
|
||||||
Freescale DDR driver in use. This type of DDR controller is
|
Freescale DDR driver in use. This type of DDR controller is
|
||||||
found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
|
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
|
||||||
SoCs.
|
|
||||||
|
|
||||||
CONFIG_SYS_FSL_DDR_ADDR
|
CONFIG_SYS_FSL_DDR_ADDR
|
||||||
Freescale DDR memory-mapped register base.
|
Freescale DDR memory-mapped register base.
|
||||||
|
|
|
||||||
|
|
@ -25,12 +25,6 @@ config MPC85xx
|
||||||
imply CMD_IRQ
|
imply CMD_IRQ
|
||||||
imply USB_EHCI_HCD if USB
|
imply USB_EHCI_HCD if USB
|
||||||
|
|
||||||
config MPC86xx
|
|
||||||
bool "MPC86xx"
|
|
||||||
select SYS_FSL_DDR
|
|
||||||
select SYS_FSL_DDR_BE
|
|
||||||
imply CMD_REGINFO
|
|
||||||
|
|
||||||
config MPC8xx
|
config MPC8xx
|
||||||
bool "MPC8xx"
|
bool "MPC8xx"
|
||||||
select BOARD_EARLY_INIT_F
|
select BOARD_EARLY_INIT_F
|
||||||
|
|
@ -47,7 +41,6 @@ config HIGH_BATS
|
||||||
|
|
||||||
source "arch/powerpc/cpu/mpc83xx/Kconfig"
|
source "arch/powerpc/cpu/mpc83xx/Kconfig"
|
||||||
source "arch/powerpc/cpu/mpc85xx/Kconfig"
|
source "arch/powerpc/cpu/mpc85xx/Kconfig"
|
||||||
source "arch/powerpc/cpu/mpc86xx/Kconfig"
|
|
||||||
source "arch/powerpc/cpu/mpc8xx/Kconfig"
|
source "arch/powerpc/cpu/mpc8xx/Kconfig"
|
||||||
source "arch/powerpc/lib/Kconfig"
|
source "arch/powerpc/lib/Kconfig"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,52 +0,0 @@
|
||||||
menu "mpc86xx CPU"
|
|
||||||
depends on MPC86xx
|
|
||||||
|
|
||||||
config SYS_CPU
|
|
||||||
default "mpc86xx"
|
|
||||||
|
|
||||||
choice
|
|
||||||
prompt "Target select"
|
|
||||||
optional
|
|
||||||
|
|
||||||
config TARGET_SBC8641D
|
|
||||||
bool "Support sbc8641d"
|
|
||||||
select ARCH_MPC8641
|
|
||||||
select BOARD_EARLY_INIT_F
|
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
config ARCH_MPC8610
|
|
||||||
bool
|
|
||||||
select FSL_LAW
|
|
||||||
select SYS_FSL_HAS_DDR1
|
|
||||||
select SYS_FSL_HAS_DDR2
|
|
||||||
|
|
||||||
config ARCH_MPC8641
|
|
||||||
bool
|
|
||||||
select FSL_LAW
|
|
||||||
select SYS_FSL_HAS_DDR1
|
|
||||||
select SYS_FSL_HAS_DDR2
|
|
||||||
|
|
||||||
config FSL_LAW
|
|
||||||
bool
|
|
||||||
help
|
|
||||||
Use Freescale common code for Local Access Window
|
|
||||||
|
|
||||||
config SYS_CCSRBAR_DEFAULT
|
|
||||||
hex "Default CCSRBAR address"
|
|
||||||
default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
|
|
||||||
help
|
|
||||||
Default value of CCSRBAR comes from power-on-reset. It
|
|
||||||
is fixed on each SoC. Some SoCs can have different value
|
|
||||||
if changed by pre-boot regime. The value here must match
|
|
||||||
the current value in SoC. If not sure, do not change.
|
|
||||||
config SYS_FSL_NUM_LAWS
|
|
||||||
int "Number of local access windows"
|
|
||||||
default 10 if ARCH_MPC8610 || ARCH_MPC8641
|
|
||||||
help
|
|
||||||
Number of local access windows. This is fixed per SoC.
|
|
||||||
If not sure, do not change.
|
|
||||||
|
|
||||||
source "board/sbc8641d/Kconfig"
|
|
||||||
|
|
||||||
endmenu
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# Copyright 2007 Freescale Semiconductor, Inc.
|
|
||||||
# (C) Copyright 2002,2003 Motorola Inc.
|
|
||||||
# Xianghua Xiao,X.Xiao@motorola.com
|
|
||||||
#
|
|
||||||
# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
|
|
||||||
# Jeff Brown
|
|
||||||
#
|
|
||||||
|
|
||||||
extra-y = start.o
|
|
||||||
extra-y += traps.o
|
|
||||||
|
|
||||||
obj-y += cache.o
|
|
||||||
obj-$(CONFIG_MP) += release.o
|
|
||||||
|
|
||||||
obj-y += cpu.o
|
|
||||||
obj-y += cpu_init.o
|
|
||||||
obj-$(CONFIG_OF_LIBFDT) += fdt.o
|
|
||||||
obj-y += interrupts.o
|
|
||||||
obj-$(CONFIG_MP) += mp.o
|
|
||||||
obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o
|
|
||||||
obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o
|
|
||||||
obj-y += speed.o
|
|
||||||
|
|
@ -1,332 +0,0 @@
|
||||||
#include <config.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <ppc_defs.h>
|
|
||||||
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
#ifndef CACHE_LINE_SIZE
|
|
||||||
# define CACHE_LINE_SIZE L1_CACHE_BYTES
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if CACHE_LINE_SIZE == 128
|
|
||||||
#define LG_CACHE_LINE_SIZE 7
|
|
||||||
#elif CACHE_LINE_SIZE == 32
|
|
||||||
#define LG_CACHE_LINE_SIZE 5
|
|
||||||
#elif CACHE_LINE_SIZE == 16
|
|
||||||
#define LG_CACHE_LINE_SIZE 4
|
|
||||||
#elif CACHE_LINE_SIZE == 8
|
|
||||||
#define LG_CACHE_LINE_SIZE 3
|
|
||||||
#else
|
|
||||||
# error "Invalid cache line size!"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Most of this code is taken from 74xx_7xx/cache.S
|
|
||||||
* and then cleaned up a bit
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Invalidate L1 instruction cache.
|
|
||||||
*/
|
|
||||||
_GLOBAL(invalidate_l1_instruction_cache)
|
|
||||||
/* use invalidate-all bit in HID0 */
|
|
||||||
mfspr r3,HID0
|
|
||||||
ori r3,r3,HID0_ICFI
|
|
||||||
mtspr HID0,r3
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Invalidate L1 data cache.
|
|
||||||
*/
|
|
||||||
_GLOBAL(invalidate_l1_data_cache)
|
|
||||||
mfspr r3,HID0
|
|
||||||
ori r3,r3,HID0_DCFI
|
|
||||||
mtspr HID0,r3
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flush data cache.
|
|
||||||
*/
|
|
||||||
_GLOBAL(flush_dcache)
|
|
||||||
lis r3,0
|
|
||||||
lis r5,CACHE_LINE_SIZE
|
|
||||||
flush:
|
|
||||||
cmp 0,1,r3,r5
|
|
||||||
bge done
|
|
||||||
lwz r5,0(r3)
|
|
||||||
lis r5,CACHE_LINE_SIZE
|
|
||||||
addi r3,r3,0x4
|
|
||||||
b flush
|
|
||||||
done:
|
|
||||||
blr
|
|
||||||
/*
|
|
||||||
* Write any modified data cache blocks out to memory
|
|
||||||
* and invalidate the corresponding instruction cache blocks.
|
|
||||||
* This is a no-op on the 601.
|
|
||||||
*
|
|
||||||
* flush_icache_range(unsigned long start, unsigned long stop)
|
|
||||||
*/
|
|
||||||
_GLOBAL(flush_icache_range)
|
|
||||||
li r5,CACHE_LINE_SIZE-1
|
|
||||||
andc r3,r3,r5
|
|
||||||
subf r4,r3,r4
|
|
||||||
add r4,r4,r5
|
|
||||||
srwi. r4,r4,LG_CACHE_LINE_SIZE
|
|
||||||
beqlr
|
|
||||||
mtctr r4
|
|
||||||
mr r6,r3
|
|
||||||
1: dcbst 0,r3
|
|
||||||
addi r3,r3,CACHE_LINE_SIZE
|
|
||||||
bdnz 1b
|
|
||||||
sync /* wait for dcbst's to get to ram */
|
|
||||||
mtctr r4
|
|
||||||
2: icbi 0,r6
|
|
||||||
addi r6,r6,CACHE_LINE_SIZE
|
|
||||||
bdnz 2b
|
|
||||||
sync /* additional sync needed on g4 */
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
/*
|
|
||||||
* Write any modified data cache blocks out to memory.
|
|
||||||
* Does not invalidate the corresponding cache lines (especially for
|
|
||||||
* any corresponding instruction cache).
|
|
||||||
*
|
|
||||||
* clean_dcache_range(unsigned long start, unsigned long stop)
|
|
||||||
*/
|
|
||||||
_GLOBAL(clean_dcache_range)
|
|
||||||
li r5,CACHE_LINE_SIZE-1
|
|
||||||
andc r3,r3,r5 /* align r3 down to cache line */
|
|
||||||
subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
|
|
||||||
add r4,r4,r5 /* r4 += cache_line_size-1 */
|
|
||||||
srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
|
|
||||||
beqlr /* if r4 == 0 return */
|
|
||||||
mtctr r4 /* ctr = r4 */
|
|
||||||
|
|
||||||
sync
|
|
||||||
1: dcbst 0,r3
|
|
||||||
addi r3,r3,CACHE_LINE_SIZE
|
|
||||||
bdnz 1b
|
|
||||||
sync /* wait for dcbst's to get to ram */
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flush a particular page from the data cache to RAM.
|
|
||||||
* Note: this is necessary because the instruction cache does *not*
|
|
||||||
* snoop from the data cache.
|
|
||||||
*
|
|
||||||
* void __flush_page_to_ram(void *page)
|
|
||||||
*/
|
|
||||||
_GLOBAL(__flush_page_to_ram)
|
|
||||||
rlwinm r3,r3,0,0,19 /* Get page base address */
|
|
||||||
li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
|
|
||||||
mtctr r4
|
|
||||||
mr r6,r3
|
|
||||||
0: dcbst 0,r3 /* Write line to ram */
|
|
||||||
addi r3,r3,CACHE_LINE_SIZE
|
|
||||||
bdnz 0b
|
|
||||||
sync
|
|
||||||
mtctr r4
|
|
||||||
1: icbi 0,r6
|
|
||||||
addi r6,r6,CACHE_LINE_SIZE
|
|
||||||
bdnz 1b
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flush a particular page from the instruction cache.
|
|
||||||
* Note: this is necessary because the instruction cache does *not*
|
|
||||||
* snoop from the data cache.
|
|
||||||
*
|
|
||||||
* void __flush_icache_page(void *page)
|
|
||||||
*/
|
|
||||||
_GLOBAL(__flush_icache_page)
|
|
||||||
li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
|
|
||||||
mtctr r4
|
|
||||||
1: icbi 0,r3
|
|
||||||
addi r3,r3,CACHE_LINE_SIZE
|
|
||||||
bdnz 1b
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clear a page using the dcbz instruction, which doesn't cause any
|
|
||||||
* memory traffic (except to write out any cache lines which get
|
|
||||||
* displaced). This only works on cacheable memory.
|
|
||||||
*/
|
|
||||||
_GLOBAL(clear_page)
|
|
||||||
li r0,4096/CACHE_LINE_SIZE
|
|
||||||
mtctr r0
|
|
||||||
1: dcbz 0,r3
|
|
||||||
addi r3,r3,CACHE_LINE_SIZE
|
|
||||||
bdnz 1b
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable L1 Instruction cache
|
|
||||||
*/
|
|
||||||
_GLOBAL(icache_enable)
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, HID0_ICFI|HID0_ILOCK
|
|
||||||
andc r3, r3, r5
|
|
||||||
ori r3, r3, HID0_ICE
|
|
||||||
ori r5, r3, HID0_ICFI
|
|
||||||
mtspr HID0, r5
|
|
||||||
mtspr HID0, r3
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable L1 Instruction cache
|
|
||||||
*/
|
|
||||||
_GLOBAL(icache_disable)
|
|
||||||
mflr r4
|
|
||||||
bl invalidate_l1_instruction_cache /* uses r3 */
|
|
||||||
sync
|
|
||||||
mtlr r4
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, 0
|
|
||||||
ori r5, r5, HID0_ICE
|
|
||||||
andc r3, r3, r5
|
|
||||||
mtspr HID0, r3
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Is instruction cache enabled?
|
|
||||||
*/
|
|
||||||
_GLOBAL(icache_status)
|
|
||||||
mfspr r3, HID0
|
|
||||||
andi. r3, r3, HID0_ICE
|
|
||||||
blr
|
|
||||||
|
|
||||||
|
|
||||||
_GLOBAL(l1dcache_enable)
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, HID0_DCFI|HID0_DLOCK
|
|
||||||
andc r3, r3, r5
|
|
||||||
mtspr HID0, r3 /* no invalidate, unlock */
|
|
||||||
ori r3, r3, HID0_DCE
|
|
||||||
ori r5, r3, HID0_DCFI
|
|
||||||
mtspr HID0, r5 /* enable + invalidate */
|
|
||||||
mtspr HID0, r3 /* enable */
|
|
||||||
sync
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable data cache(s) - L1 and optionally L2
|
|
||||||
* Calls l2cache_enable. LR saved in r5
|
|
||||||
*/
|
|
||||||
_GLOBAL(dcache_enable)
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, HID0_DCFI|HID0_DLOCK
|
|
||||||
andc r3, r3, r5
|
|
||||||
mtspr HID0, r3 /* no invalidate, unlock */
|
|
||||||
ori r3, r3, HID0_DCE
|
|
||||||
ori r5, r3, HID0_DCFI
|
|
||||||
mtspr HID0, r5 /* enable + invalidate */
|
|
||||||
mtspr HID0, r3 /* enable */
|
|
||||||
sync
|
|
||||||
#ifdef CONFIG_SYS_L2
|
|
||||||
mflr r5
|
|
||||||
bl l2cache_enable /* uses r3 and r4 */
|
|
||||||
sync
|
|
||||||
mtlr r5
|
|
||||||
#endif
|
|
||||||
blr
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable data cache(s) - L1 and optionally L2
|
|
||||||
* Calls flush_dcache and l2cache_disable_no_flush.
|
|
||||||
* LR saved in r4
|
|
||||||
*/
|
|
||||||
_GLOBAL(dcache_disable)
|
|
||||||
mflr r4 /* save link register */
|
|
||||||
bl flush_dcache /* uses r3 and r5 */
|
|
||||||
sync
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, HID0_DCFI|HID0_DLOCK
|
|
||||||
andc r3, r3, r5
|
|
||||||
mtspr HID0, r3 /* no invalidate, unlock */
|
|
||||||
li r5, HID0_DCE|HID0_DCFI
|
|
||||||
andc r3, r3, r5 /* no enable, no invalidate */
|
|
||||||
mtspr HID0, r3
|
|
||||||
sync
|
|
||||||
#ifdef CONFIG_SYS_L2
|
|
||||||
bl l2cache_disable_no_flush /* uses r3 */
|
|
||||||
#endif
|
|
||||||
mtlr r4 /* restore link register */
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Is data cache enabled?
|
|
||||||
*/
|
|
||||||
_GLOBAL(dcache_status)
|
|
||||||
mfspr r3, HID0
|
|
||||||
andi. r3, r3, HID0_DCE
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Invalidate L2 cache using L2I, assume L2 is enabled
|
|
||||||
*/
|
|
||||||
_GLOBAL(l2cache_invalidate)
|
|
||||||
mfspr r3, l2cr
|
|
||||||
rlwinm. r3, r3, 0, 0, 0
|
|
||||||
beq 1f
|
|
||||||
|
|
||||||
mfspr r3, l2cr
|
|
||||||
rlwinm r3, r3, 0, 1, 31
|
|
||||||
|
|
||||||
#ifdef CONFIG_ALTIVEC
|
|
||||||
dssall
|
|
||||||
#endif
|
|
||||||
sync
|
|
||||||
mtspr l2cr, r3
|
|
||||||
sync
|
|
||||||
1: mfspr r3, l2cr
|
|
||||||
oris r3, r3, L2CR_L2I@h
|
|
||||||
mtspr l2cr, r3
|
|
||||||
|
|
||||||
invl2:
|
|
||||||
mfspr r3, l2cr
|
|
||||||
andis. r3, r3, L2CR_L2I@h
|
|
||||||
bne invl2
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable L2 cache
|
|
||||||
* Calls l2cache_invalidate. LR is saved in r4
|
|
||||||
*/
|
|
||||||
_GLOBAL(l2cache_enable)
|
|
||||||
mflr r4 /* save link register */
|
|
||||||
bl l2cache_invalidate /* uses r3 */
|
|
||||||
sync
|
|
||||||
lis r3, L2_ENABLE@h
|
|
||||||
ori r3, r3, L2_ENABLE@l
|
|
||||||
mtspr l2cr, r3
|
|
||||||
isync
|
|
||||||
mtlr r4 /* restore link register */
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable L2 cache
|
|
||||||
* Calls flush_dcache. LR is saved in r4
|
|
||||||
*/
|
|
||||||
_GLOBAL(l2cache_disable)
|
|
||||||
mflr r4 /* save link register */
|
|
||||||
bl flush_dcache /* uses r3 and r5 */
|
|
||||||
sync
|
|
||||||
mtlr r4 /* restore link register */
|
|
||||||
l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
|
|
||||||
lis r3, L2_INIT@h
|
|
||||||
ori r3, r3, L2_INIT@l
|
|
||||||
mtspr l2cr, r3
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# (C) Copyright 2004 Freescale Semiconductor.
|
|
||||||
# Jeff Brown
|
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float
|
|
||||||
|
|
@ -1,207 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
|
|
||||||
* Jeff Brown
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <cpu_func.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <time.h>
|
|
||||||
#include <vsprintf.h>
|
|
||||||
#include <watchdog.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/ppc.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Default board reset function
|
|
||||||
*/
|
|
||||||
static void
|
|
||||||
__board_reset(void)
|
|
||||||
{
|
|
||||||
/* Do nothing */
|
|
||||||
}
|
|
||||||
void board_reset(void) __attribute__((weak, alias("__board_reset")));
|
|
||||||
|
|
||||||
|
|
||||||
int
|
|
||||||
checkcpu(void)
|
|
||||||
{
|
|
||||||
sys_info_t sysinfo;
|
|
||||||
uint pvr, svr;
|
|
||||||
uint major, minor;
|
|
||||||
char buf1[32], buf2[32];
|
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
struct cpu_type *cpu;
|
|
||||||
uint msscr0 = mfspr(MSSCR0);
|
|
||||||
|
|
||||||
svr = get_svr();
|
|
||||||
major = SVR_MAJ(svr);
|
|
||||||
minor = SVR_MIN(svr);
|
|
||||||
|
|
||||||
if (cpu_numcores() > 1) {
|
|
||||||
#ifndef CONFIG_MP
|
|
||||||
puts("Unicore software on multiprocessor system!!\n"
|
|
||||||
"To enable mutlticore build define CONFIG_MP\n");
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
puts("CPU: ");
|
|
||||||
|
|
||||||
cpu = gd->arch.cpu;
|
|
||||||
|
|
||||||
puts(cpu->name);
|
|
||||||
|
|
||||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
|
|
||||||
puts("Core: ");
|
|
||||||
|
|
||||||
pvr = get_pvr();
|
|
||||||
major = PVR_E600_MAJ(pvr);
|
|
||||||
minor = PVR_E600_MIN(pvr);
|
|
||||||
|
|
||||||
printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
|
|
||||||
if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
|
|
||||||
puts("\n Core1Translation Enabled");
|
|
||||||
debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
|
|
||||||
|
|
||||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
|
|
||||||
|
|
||||||
get_sys_info(&sysinfo);
|
|
||||||
|
|
||||||
puts("Clock Configuration:\n");
|
|
||||||
printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
|
|
||||||
printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
|
|
||||||
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
|
|
||||||
strmhz(buf1, sysinfo.freq_systembus / 2),
|
|
||||||
strmhz(buf2, sysinfo.freq_systembus));
|
|
||||||
|
|
||||||
if (sysinfo.freq_localbus > LCRR_CLKDIV) {
|
|
||||||
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
|
|
||||||
} else {
|
|
||||||
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
|
|
||||||
sysinfo.freq_localbus);
|
|
||||||
}
|
|
||||||
|
|
||||||
puts("L1: D-cache 32 KiB enabled\n");
|
|
||||||
puts(" I-cache 32 KiB enabled\n");
|
|
||||||
|
|
||||||
puts("L2: ");
|
|
||||||
if (get_l2cr() & 0x80000000) {
|
|
||||||
#if defined(CONFIG_ARCH_MPC8610)
|
|
||||||
puts("256");
|
|
||||||
#elif defined(CONFIG_ARCH_MPC8641)
|
|
||||||
puts("512");
|
|
||||||
#endif
|
|
||||||
puts(" KiB enabled\n");
|
|
||||||
} else {
|
|
||||||
puts("Disabled\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
|
|
||||||
/* Attempt board-specific reset */
|
|
||||||
board_reset();
|
|
||||||
|
|
||||||
/* Next try asserting HRESET_REQ */
|
|
||||||
out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
|
|
||||||
|
|
||||||
while (1)
|
|
||||||
;
|
|
||||||
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Get timebase clock frequency
|
|
||||||
*/
|
|
||||||
unsigned long
|
|
||||||
get_tbclk(void)
|
|
||||||
{
|
|
||||||
sys_info_t sys_info;
|
|
||||||
|
|
||||||
get_sys_info(&sys_info);
|
|
||||||
return (sys_info.freq_systembus + 3L) / 4L;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_WATCHDOG)
|
|
||||||
void
|
|
||||||
watchdog_reset(void)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_ARCH_MPC8610)
|
|
||||||
/*
|
|
||||||
* This actually feed the hard enabled watchdog.
|
|
||||||
*/
|
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile ccsr_wdt_t *wdt = &immap->im_wdt;
|
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
u32 tmp = gur->pordevsr;
|
|
||||||
|
|
||||||
if (tmp & 0x4000) {
|
|
||||||
wdt->swsrr = 0x556c;
|
|
||||||
wdt->swsrr = 0xaa39;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_WATCHDOG */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Print out the state of various machine registers.
|
|
||||||
* Currently prints out LAWs, BR0/OR0, and BATs
|
|
||||||
*/
|
|
||||||
void print_reginfo(void)
|
|
||||||
{
|
|
||||||
print_bats();
|
|
||||||
print_laws();
|
|
||||||
print_lbc_regs();
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set the DDR BATs to reflect the actual size of DDR.
|
|
||||||
*
|
|
||||||
* dram_size is the actual size of DDR, in bytes
|
|
||||||
*
|
|
||||||
* Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
|
|
||||||
* are using a single BAT to cover DDR.
|
|
||||||
*
|
|
||||||
* If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
|
|
||||||
* is not defined) then we might have a situation where U-Boot will attempt
|
|
||||||
* to relocated itself outside of the region mapped by DBAT0.
|
|
||||||
* This will cause a machine check.
|
|
||||||
*
|
|
||||||
* Currently we are limited to power of two sized DDR since we only use a
|
|
||||||
* single bat. If a non-power of two size is used that is less than
|
|
||||||
* CONFIG_MAX_MEM_MAPPED u-boot will crash.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
void setup_ddr_bat(phys_addr_t dram_size)
|
|
||||||
{
|
|
||||||
unsigned long batu, bl;
|
|
||||||
|
|
||||||
bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
|
|
||||||
|
|
||||||
if (BATU_SIZE(bl) != dram_size) {
|
|
||||||
u64 sz = (u64)dram_size - BATU_SIZE(bl);
|
|
||||||
print_size(sz, " left unmapped\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
batu = bl | BATU_VS | BATU_VP;
|
|
||||||
write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
|
|
||||||
write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
|
|
||||||
}
|
|
||||||
|
|
@ -1,104 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
|
|
||||||
* Jeff Brown
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* cpu_init.c - low level cpu init
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <asm-offsets.h>
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/fsl_serdes.h>
|
|
||||||
#include <asm/mp.h>
|
|
||||||
|
|
||||||
extern void srio_init(void);
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Breathe some life into the CPU...
|
|
||||||
*
|
|
||||||
* Set up the memory map
|
|
||||||
* initialize a bunch of registers
|
|
||||||
*/
|
|
||||||
|
|
||||||
void cpu_init_f(void)
|
|
||||||
{
|
|
||||||
/* Pointer is writable since we allocated a register for it */
|
|
||||||
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
|
||||||
|
|
||||||
/* Clear initial global data */
|
|
||||||
memset ((void *) gd, 0, sizeof (gd_t));
|
|
||||||
|
|
||||||
#ifdef CONFIG_FSL_LAW
|
|
||||||
init_laws();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
setup_bats();
|
|
||||||
|
|
||||||
init_early_memctl_regs();
|
|
||||||
|
|
||||||
#if defined(CONFIG_FSL_DMA)
|
|
||||||
dma_init();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* enable the timebase bit in HID0 */
|
|
||||||
set_hid0(get_hid0() | 0x4000000);
|
|
||||||
|
|
||||||
/* enable EMCP, SYNCBE | ABE bits in HID1 */
|
|
||||||
set_hid1(get_hid1() | 0x80000C00);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* initialize higher level parts of CPU like timers
|
|
||||||
*/
|
|
||||||
int cpu_init_r(void)
|
|
||||||
{
|
|
||||||
/* needs to be in ram since code uses global static vars */
|
|
||||||
fsl_serdes_init();
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_SRIO
|
|
||||||
srio_init();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_MP)
|
|
||||||
setup_mp();
|
|
||||||
#endif
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_ADDR_MAP
|
|
||||||
/* Initialize address mapping array */
|
|
||||||
void init_addr_map(void)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
ppc_bat_t bat = DBAT0;
|
|
||||||
phys_size_t size;
|
|
||||||
unsigned long upper, lower;
|
|
||||||
|
|
||||||
for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
|
|
||||||
if (read_bat(bat, &upper, &lower) != -1) {
|
|
||||||
if (!BATU_VALID(upper))
|
|
||||||
size = 0;
|
|
||||||
else
|
|
||||||
size = BATU_SIZE(upper);
|
|
||||||
addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
|
|
||||||
size, i);
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_HIGH_BATS
|
|
||||||
/* High bats are not contiguous with low BAT numbers */
|
|
||||||
if (bat == DBAT3)
|
|
||||||
bat = DBAT4 - 1;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,52 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright 2008, 2011 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#include <asm/mp.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
extern void ft_fixup_num_cores(void *blob);
|
|
||||||
extern void ft_srio_setup(void *blob);
|
|
||||||
|
|
||||||
void ft_cpu_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_MP
|
|
||||||
int off;
|
|
||||||
u32 bootpg = determine_mp_bootpg(NULL);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
|
|
||||||
"timebase-frequency", bd->bi_busfreq / 4, 1);
|
|
||||||
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
|
|
||||||
"bus-frequency", bd->bi_busfreq, 1);
|
|
||||||
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
|
|
||||||
"clock-frequency", bd->bi_intfreq, 1);
|
|
||||||
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
|
|
||||||
"bus-frequency", bd->bi_busfreq, 1);
|
|
||||||
|
|
||||||
fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_NS16550
|
|
||||||
do_fixup_by_compat_u32(blob, "ns16550",
|
|
||||||
"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_MP
|
|
||||||
/* Reserve the boot page so OSes dont use it */
|
|
||||||
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
|
|
||||||
if (off < 0)
|
|
||||||
printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
|
|
||||||
|
|
||||||
ft_fixup_num_cores(blob);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_SRIO
|
|
||||||
ft_srio_setup(blob);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
@ -1,116 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* (C) Copyright 2000-2002
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2002 (440 port)
|
|
||||||
* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
|
|
||||||
*
|
|
||||||
* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
|
|
||||||
* Xianghua Xiao (X.Xiao@motorola.com)
|
|
||||||
*
|
|
||||||
* (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
|
|
||||||
* Jeff Brown
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <irq_func.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <time.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#ifdef CONFIG_POST
|
|
||||||
#include <post.h>
|
|
||||||
#endif
|
|
||||||
#include <asm/ptrace.h>
|
|
||||||
|
|
||||||
void interrupt_init_cpu(unsigned *decrementer_count)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile ccsr_pic_t *pic = &immr->im_pic;
|
|
||||||
|
|
||||||
#ifdef CONFIG_POST
|
|
||||||
/*
|
|
||||||
* The POST word is stored in the PIC's TFRR register which gets
|
|
||||||
* cleared when the PIC is reset. Save it off so we can restore it
|
|
||||||
* later.
|
|
||||||
*/
|
|
||||||
ulong post_word = post_word_load();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
pic->gcr = MPC86xx_PICGCR_RST;
|
|
||||||
while (pic->gcr & MPC86xx_PICGCR_RST)
|
|
||||||
;
|
|
||||||
pic->gcr = MPC86xx_PICGCR_MODE;
|
|
||||||
|
|
||||||
*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
|
|
||||||
debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
|
|
||||||
(get_tbclk() / 1000000),
|
|
||||||
*decrementer_count);
|
|
||||||
|
|
||||||
#ifdef CONFIG_INTERRUPTS
|
|
||||||
|
|
||||||
pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
|
|
||||||
debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
|
|
||||||
|
|
||||||
pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
|
|
||||||
debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
|
|
||||||
|
|
||||||
pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
|
|
||||||
debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
|
|
||||||
pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
|
|
||||||
debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
|
|
||||||
pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
|
|
||||||
debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
pic->ctpr = 0; /* 40080 clear current task priority register */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_POST
|
|
||||||
post_word_store(post_word);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* timer_interrupt - gets called when the decrementer overflows,
|
|
||||||
* with interrupts disabled.
|
|
||||||
* Trivial implementation - no need to be really accurate.
|
|
||||||
*/
|
|
||||||
void timer_interrupt_cpu(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
/* nothing to do here */
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Install and free a interrupt handler. Not implemented yet.
|
|
||||||
*/
|
|
||||||
void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
void irq_free_handler(int vec)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* irqinfo - print information about PCI devices,not implemented.
|
|
||||||
*/
|
|
||||||
int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Handle external interrupts
|
|
||||||
*/
|
|
||||||
void external_interrupt(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
puts("external_interrupt(oops!)\n");
|
|
||||||
}
|
|
||||||
|
|
@ -1,130 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <cpu_func.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <ioports.h>
|
|
||||||
#include <lmb.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/mp.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
int cpu_reset(u32 nr)
|
|
||||||
{
|
|
||||||
/* dummy function so common/cmd_mp.c will build
|
|
||||||
* should be implemented in the future, when cpu_release()
|
|
||||||
* is supported. Be aware there may be a similiar bug
|
|
||||||
* as exists on MPC85xx w/its PIC having a timing window
|
|
||||||
* associated to resetting the core */
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cpu_status(u32 nr)
|
|
||||||
{
|
|
||||||
/* dummy function so common/cmd_mp.c will build */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cpu_disable(u32 nr)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
|
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
|
|
||||||
switch (nr) {
|
|
||||||
case 0:
|
|
||||||
setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printf("Invalid cpu number for disable %d\n", nr);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int is_core_disabled(int nr) {
|
|
||||||
immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
|
|
||||||
ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
u32 devdisr = in_be32(&gur->devdisr);
|
|
||||||
|
|
||||||
switch (nr) {
|
|
||||||
case 0:
|
|
||||||
return (devdisr & MPC86xx_DEVDISR_CPU0);
|
|
||||||
case 1:
|
|
||||||
return (devdisr & MPC86xx_DEVDISR_CPU1);
|
|
||||||
default:
|
|
||||||
printf("Invalid cpu number for disable %d\n", nr);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int cpu_release(u32 nr, int argc, char *const argv[])
|
|
||||||
{
|
|
||||||
/* dummy function so common/cmd_mp.c will build
|
|
||||||
* should be implemented in the future */
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 determine_mp_bootpg(unsigned int *pagesize)
|
|
||||||
{
|
|
||||||
if (pagesize)
|
|
||||||
*pagesize = 4096;
|
|
||||||
|
|
||||||
/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
|
|
||||||
if ((u64)gd->ram_size > 0xfffff000)
|
|
||||||
return (0xfff00000);
|
|
||||||
|
|
||||||
return (gd->ram_size - (1024 * 1024));
|
|
||||||
}
|
|
||||||
|
|
||||||
void cpu_mp_lmb_reserve(struct lmb *lmb)
|
|
||||||
{
|
|
||||||
u32 bootpg = determine_mp_bootpg(NULL);
|
|
||||||
|
|
||||||
/* tell u-boot we stole a page */
|
|
||||||
lmb_reserve(lmb, bootpg, 4096);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copy the code for other cpus to execute into an
|
|
||||||
* aligned location accessible via BPTR
|
|
||||||
*/
|
|
||||||
void setup_mp(void)
|
|
||||||
{
|
|
||||||
extern ulong __secondary_start_page;
|
|
||||||
ulong fixup = (ulong)&__secondary_start_page;
|
|
||||||
u32 bootpg = determine_mp_bootpg(NULL);
|
|
||||||
u32 bootpg_va;
|
|
||||||
|
|
||||||
if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
|
|
||||||
/* We're not covered by the DDR mapping, set up BAT */
|
|
||||||
write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
|
|
||||||
BATU_VS | BATU_VP,
|
|
||||||
bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
|
|
||||||
bootpg_va = CONFIG_SYS_SCRATCH_VA;
|
|
||||||
} else {
|
|
||||||
bootpg_va = bootpg;
|
|
||||||
}
|
|
||||||
|
|
||||||
memcpy((void *)bootpg_va, (void *)fixup, 4096);
|
|
||||||
flush_cache(bootpg_va, 4096);
|
|
||||||
|
|
||||||
/* remove the temporary BAT mapping */
|
|
||||||
if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
|
|
||||||
write_bat(DBAT7, 0, 0);
|
|
||||||
|
|
||||||
/* If the physical location of bootpg is not at fff00000, set BPTR */
|
|
||||||
if (bootpg != 0xfff00000)
|
|
||||||
out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
|
|
||||||
(bootpg >> 12));
|
|
||||||
}
|
|
||||||
|
|
@ -1,87 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/immap_86xx.h>
|
|
||||||
#include <asm/fsl_serdes.h>
|
|
||||||
|
|
||||||
#define SRDS1_MAX_LANES 4
|
|
||||||
#define SRDS2_MAX_LANES 4
|
|
||||||
|
|
||||||
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
|
|
||||||
|
|
||||||
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
|
|
||||||
[0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0x7] = {NONE, NONE, NONE, NONE},
|
|
||||||
};
|
|
||||||
|
|
||||||
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
|
|
||||||
[0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
|
||||||
[0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
|
||||||
[0x7] = {NONE, NONE, NONE, NONE},
|
|
||||||
};
|
|
||||||
|
|
||||||
int is_serdes_configured(enum srds_prtcl device)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
if (!(serdes1_prtcl_map & (1 << NONE)))
|
|
||||||
fsl_serdes_init();
|
|
||||||
|
|
||||||
ret = (1 << device) & serdes1_prtcl_map;
|
|
||||||
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
if (!(serdes2_prtcl_map & (1 << NONE)))
|
|
||||||
fsl_serdes_init();
|
|
||||||
|
|
||||||
return (1 << device) & serdes2_prtcl_map;
|
|
||||||
}
|
|
||||||
|
|
||||||
void fsl_serdes_init(void)
|
|
||||||
{
|
|
||||||
immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
|
|
||||||
ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
|
||||||
u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
|
|
||||||
MPC8610_PORDEVSR_IO_SEL_SHIFT;
|
|
||||||
int lane;
|
|
||||||
|
|
||||||
if (serdes1_prtcl_map & (1 << NONE) &&
|
|
||||||
serdes2_prtcl_map & (1 << NONE))
|
|
||||||
return;
|
|
||||||
|
|
||||||
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
|
|
||||||
|
|
||||||
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
|
|
||||||
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
|
|
||||||
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
|
|
||||||
serdes1_prtcl_map |= (1 << lane_prtcl);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set the first bit to indicate serdes has been initialized */
|
|
||||||
serdes1_prtcl_map |= (1 << NONE);
|
|
||||||
|
|
||||||
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
|
|
||||||
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
|
|
||||||
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
|
|
||||||
serdes2_prtcl_map |= (1 << lane_prtcl);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set the first bit to indicate serdes has been initialized */
|
|
||||||
serdes2_prtcl_map |= (1 << NONE);
|
|
||||||
}
|
|
||||||
|
|
@ -1,96 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/immap_86xx.h>
|
|
||||||
#include <asm/fsl_serdes.h>
|
|
||||||
|
|
||||||
#define SRDS1_MAX_LANES 4
|
|
||||||
#define SRDS2_MAX_LANES 4
|
|
||||||
|
|
||||||
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
|
|
||||||
|
|
||||||
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
|
|
||||||
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
|
||||||
};
|
|
||||||
|
|
||||||
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
|
|
||||||
[0x3] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
|
||||||
[0x5] = {SRIO1, SRIO1, SRIO1, SRIO1},
|
|
||||||
[0x6] = {SRIO1, SRIO1, SRIO1, SRIO1},
|
|
||||||
[0x7] = {SRIO1, SRIO1, SRIO1, SRIO1},
|
|
||||||
[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
|
|
||||||
[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
|
|
||||||
[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
|
|
||||||
[0xe] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
|
||||||
[0xf] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
|
||||||
};
|
|
||||||
|
|
||||||
int is_serdes_configured(enum srds_prtcl device)
|
|
||||||
{
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
if (!(serdes1_prtcl_map & (1 << NONE)))
|
|
||||||
fsl_serdes_init();
|
|
||||||
|
|
||||||
ret = (1 << device) & serdes1_prtcl_map;
|
|
||||||
|
|
||||||
if (ret)
|
|
||||||
return ret;
|
|
||||||
|
|
||||||
if (!(serdes2_prtcl_map & (1 << NONE)))
|
|
||||||
fsl_serdes_init();
|
|
||||||
|
|
||||||
return (1 << device) & serdes2_prtcl_map;
|
|
||||||
}
|
|
||||||
|
|
||||||
void fsl_serdes_init(void)
|
|
||||||
{
|
|
||||||
immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
|
|
||||||
ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
|
||||||
u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >>
|
|
||||||
MPC8641_PORDEVSR_IO_SEL_SHIFT;
|
|
||||||
int lane;
|
|
||||||
|
|
||||||
if (serdes1_prtcl_map & (1 << NONE) &&
|
|
||||||
serdes2_prtcl_map & (1 << NONE))
|
|
||||||
return;
|
|
||||||
|
|
||||||
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
|
|
||||||
|
|
||||||
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
|
|
||||||
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
|
|
||||||
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
|
|
||||||
serdes1_prtcl_map |= (1 << lane_prtcl);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set the first bit to indicate serdes has been initialized */
|
|
||||||
serdes1_prtcl_map |= (1 << NONE);
|
|
||||||
|
|
||||||
if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
|
|
||||||
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
|
|
||||||
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
|
|
||||||
serdes2_prtcl_map |= (1 << lane_prtcl);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Set the first bit to indicate serdes has been initialized */
|
|
||||||
serdes2_prtcl_map |= (1 << NONE);
|
|
||||||
}
|
|
||||||
|
|
@ -1,149 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2004, 2007, 2008 Freescale Semiconductor.
|
|
||||||
* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
|
|
||||||
*/
|
|
||||||
#include <config.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <ppc_defs.h>
|
|
||||||
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
/* If this is a multi-cpu system then we need to handle the
|
|
||||||
* 2nd cpu. The assumption is that the 2nd cpu is being
|
|
||||||
* held in boot holdoff mode until the 1st cpu unlocks it
|
|
||||||
* from Linux. We'll do some basic cpu init and then pass
|
|
||||||
* it to the Linux Reset Vector.
|
|
||||||
* Sri: Much of this initialization is not required. Linux
|
|
||||||
* rewrites the bats, and the sprs and also enables the L1 cache.
|
|
||||||
*
|
|
||||||
* Core 0 must copy this to a 1M aligned region and set BPTR
|
|
||||||
* to point to it.
|
|
||||||
*/
|
|
||||||
.align 12
|
|
||||||
.globl __secondary_start_page
|
|
||||||
__secondary_start_page:
|
|
||||||
.space 0x100 /* space over to reset vector loc */
|
|
||||||
mfspr r0, MSSCR0
|
|
||||||
andi. r0, r0, 0x0020
|
|
||||||
rlwinm r0,r0,27,31,31
|
|
||||||
mtspr PIR, r0
|
|
||||||
|
|
||||||
/* Invalidate BATs */
|
|
||||||
li r0, 0
|
|
||||||
mtspr IBAT0U, r0
|
|
||||||
mtspr IBAT1U, r0
|
|
||||||
mtspr IBAT2U, r0
|
|
||||||
mtspr IBAT3U, r0
|
|
||||||
mtspr IBAT4U, r0
|
|
||||||
mtspr IBAT5U, r0
|
|
||||||
mtspr IBAT6U, r0
|
|
||||||
mtspr IBAT7U, r0
|
|
||||||
isync
|
|
||||||
mtspr DBAT0U, r0
|
|
||||||
mtspr DBAT1U, r0
|
|
||||||
mtspr DBAT2U, r0
|
|
||||||
mtspr DBAT3U, r0
|
|
||||||
mtspr DBAT4U, r0
|
|
||||||
mtspr DBAT5U, r0
|
|
||||||
mtspr DBAT6U, r0
|
|
||||||
mtspr DBAT7U, r0
|
|
||||||
isync
|
|
||||||
sync
|
|
||||||
|
|
||||||
/* enable extended addressing */
|
|
||||||
mfspr r0, HID0
|
|
||||||
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
|
|
||||||
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
|
|
||||||
mtspr HID0, r0
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_L2
|
|
||||||
/* init the L2 cache */
|
|
||||||
addis r3, r0, L2_INIT@h
|
|
||||||
ori r3, r3, L2_INIT@l
|
|
||||||
sync
|
|
||||||
mtspr l2cr, r3
|
|
||||||
#ifdef CONFIG_ALTIVEC
|
|
||||||
dssall
|
|
||||||
#endif
|
|
||||||
/* invalidate the L2 cache */
|
|
||||||
mfspr r3, l2cr
|
|
||||||
rlwinm. r3, r3, 0, 0, 0
|
|
||||||
beq 1f
|
|
||||||
|
|
||||||
mfspr r3, l2cr
|
|
||||||
rlwinm r3, r3, 0, 1, 31
|
|
||||||
|
|
||||||
#ifdef CONFIG_ALTIVEC
|
|
||||||
dssall
|
|
||||||
#endif
|
|
||||||
sync
|
|
||||||
mtspr l2cr, r3
|
|
||||||
sync
|
|
||||||
1: mfspr r3, l2cr
|
|
||||||
oris r3, r3, L2CR_L2I@h
|
|
||||||
mtspr l2cr, r3
|
|
||||||
|
|
||||||
invl2:
|
|
||||||
mfspr r3, l2cr
|
|
||||||
andis. r3, r3, L2CR_L2I@h
|
|
||||||
bne invl2
|
|
||||||
sync
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* enable and invalidate the data cache */
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, HID0_DCFI|HID0_DLOCK
|
|
||||||
andc r3, r3, r5
|
|
||||||
mtspr HID0, r3 /* no invalidate, unlock */
|
|
||||||
ori r3, r3, HID0_DCE
|
|
||||||
ori r5, r3, HID0_DCFI
|
|
||||||
mtspr HID0, r5 /* enable + invalidate */
|
|
||||||
mtspr HID0, r3 /* enable */
|
|
||||||
sync
|
|
||||||
#ifdef CONFIG_SYS_L2
|
|
||||||
sync
|
|
||||||
lis r3, L2_ENABLE@h
|
|
||||||
ori r3, r3, L2_ENABLE@l
|
|
||||||
mtspr l2cr, r3
|
|
||||||
isync
|
|
||||||
sync
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* enable and invalidate the instruction cache*/
|
|
||||||
mfspr r3, HID0
|
|
||||||
li r5, HID0_ICFI|HID0_ILOCK
|
|
||||||
andc r3, r3, r5
|
|
||||||
ori r3, r3, HID0_ICE
|
|
||||||
ori r5, r3, HID0_ICFI
|
|
||||||
mtspr HID0, r5
|
|
||||||
mtspr HID0, r3
|
|
||||||
isync
|
|
||||||
sync
|
|
||||||
|
|
||||||
/* TBEN in HID0 */
|
|
||||||
mfspr r4, HID0
|
|
||||||
oris r4, r4, 0x0400
|
|
||||||
mtspr HID0, r4
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* MCP|SYNCBE|ABE in HID1 */
|
|
||||||
mfspr r4, HID1
|
|
||||||
oris r4, r4, 0x8000
|
|
||||||
ori r4, r4, 0x0C00
|
|
||||||
mtspr HID1, r4
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
|
|
||||||
lis r3, CONFIG_LINUX_RESET_VEC@h
|
|
||||||
ori r3, r3, CONFIG_LINUX_RESET_VEC@l
|
|
||||||
mtlr r3
|
|
||||||
blr
|
|
||||||
|
|
||||||
/* Never Returns, Running in Linux Now */
|
|
||||||
|
|
@ -1,134 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2004 Freescale Semiconductor.
|
|
||||||
* Jeff Brown
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000-2002
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <clock_legacy.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
|
|
||||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|
||||||
|
|
||||||
void get_sys_info(sys_info_t *sys_info)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
uint plat_ratio, e600_ratio;
|
|
||||||
|
|
||||||
plat_ratio = (gur->porpllsr) & 0x0000003e;
|
|
||||||
plat_ratio >>= 1;
|
|
||||||
|
|
||||||
switch (plat_ratio) {
|
|
||||||
case 0x0:
|
|
||||||
sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ;
|
|
||||||
break;
|
|
||||||
case 0x02:
|
|
||||||
case 0x03:
|
|
||||||
case 0x04:
|
|
||||||
case 0x05:
|
|
||||||
case 0x06:
|
|
||||||
case 0x08:
|
|
||||||
case 0x09:
|
|
||||||
case 0x0a:
|
|
||||||
case 0x0c:
|
|
||||||
case 0x10:
|
|
||||||
sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
sys_info->freq_systembus = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
e600_ratio = (gur->porpllsr) & 0x003f0000;
|
|
||||||
e600_ratio >>= 16;
|
|
||||||
|
|
||||||
switch (e600_ratio) {
|
|
||||||
case 0x10:
|
|
||||||
sys_info->freq_processor = 2 * sys_info->freq_systembus;
|
|
||||||
break;
|
|
||||||
case 0x19:
|
|
||||||
sys_info->freq_processor = 5 * sys_info->freq_systembus / 2;
|
|
||||||
break;
|
|
||||||
case 0x20:
|
|
||||||
sys_info->freq_processor = 3 * sys_info->freq_systembus;
|
|
||||||
break;
|
|
||||||
case 0x39:
|
|
||||||
sys_info->freq_processor = 7 * sys_info->freq_systembus / 2;
|
|
||||||
break;
|
|
||||||
case 0x28:
|
|
||||||
sys_info->freq_processor = 4 * sys_info->freq_systembus;
|
|
||||||
break;
|
|
||||||
case 0x1d:
|
|
||||||
sys_info->freq_processor = 9 * sys_info->freq_systembus / 2;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
sys_info->freq_processor = e600_ratio +
|
|
||||||
sys_info->freq_systembus;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
sys_info->freq_localbus = sys_info->freq_systembus;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Measure CPU clock speed (core clock GCLK1, GCLK2)
|
|
||||||
* (Approx. GCLK frequency in Hz)
|
|
||||||
*/
|
|
||||||
|
|
||||||
int get_clocks(void)
|
|
||||||
{
|
|
||||||
sys_info_t sys_info;
|
|
||||||
|
|
||||||
get_sys_info(&sys_info);
|
|
||||||
gd->cpu_clk = sys_info.freq_processor;
|
|
||||||
gd->bus_clk = sys_info.freq_systembus;
|
|
||||||
gd->arch.lbc_clk = sys_info.freq_localbus;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The base clock for I2C depends on the actual SOC. Unfortunately,
|
|
||||||
* there is no pattern that can be used to determine the frequency, so
|
|
||||||
* the only choice is to look up the actual SOC number and use the value
|
|
||||||
* for that SOC. This information is taken from application note
|
|
||||||
* AN2919.
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_ARCH_MPC8610
|
|
||||||
gd->arch.i2c1_clk = sys_info.freq_systembus;
|
|
||||||
#else
|
|
||||||
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
|
|
||||||
#endif
|
|
||||||
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
|
|
||||||
|
|
||||||
if (gd->cpu_clk != 0)
|
|
||||||
return 0;
|
|
||||||
else
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* get_bus_freq
|
|
||||||
* Return system bus freq in Hz
|
|
||||||
*/
|
|
||||||
|
|
||||||
ulong get_bus_freq(ulong dummy)
|
|
||||||
{
|
|
||||||
ulong val;
|
|
||||||
sys_info_t sys_info;
|
|
||||||
|
|
||||||
get_sys_info(&sys_info);
|
|
||||||
val = sys_info.freq_systembus;
|
|
||||||
|
|
||||||
return val;
|
|
||||||
}
|
|
||||||
|
|
@ -1,982 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2004, 2007, 2011 Freescale Semiconductor.
|
|
||||||
* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* The processor starts at 0xfff00100 and the code is executed
|
|
||||||
* from flash. The code is organized to be at an other address
|
|
||||||
* in memory, but as long we don't jump around before relocating.
|
|
||||||
* board_init lies at a quite high address and when the cpu has
|
|
||||||
* jumped there, everything is ok.
|
|
||||||
*/
|
|
||||||
#include <asm-offsets.h>
|
|
||||||
#include <config.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
#include <version.h>
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <ppc_defs.h>
|
|
||||||
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/u-boot.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set up GOT: Global Offset Table
|
|
||||||
*
|
|
||||||
* Use r12 to access the GOT
|
|
||||||
*/
|
|
||||||
START_GOT
|
|
||||||
GOT_ENTRY(_GOT2_TABLE_)
|
|
||||||
GOT_ENTRY(_FIXUP_TABLE_)
|
|
||||||
|
|
||||||
GOT_ENTRY(_start)
|
|
||||||
GOT_ENTRY(_start_of_vectors)
|
|
||||||
GOT_ENTRY(_end_of_vectors)
|
|
||||||
GOT_ENTRY(transfer_to_handler)
|
|
||||||
|
|
||||||
GOT_ENTRY(__init_end)
|
|
||||||
GOT_ENTRY(__bss_end)
|
|
||||||
GOT_ENTRY(__bss_start)
|
|
||||||
END_GOT
|
|
||||||
|
|
||||||
/*
|
|
||||||
* r3 - 1st arg to board_init(): IMMP pointer
|
|
||||||
* r4 - 2nd arg to board_init(): boot flag
|
|
||||||
*/
|
|
||||||
.text
|
|
||||||
.long 0x27051956 /* U-Boot Magic Number */
|
|
||||||
.globl version_string
|
|
||||||
version_string:
|
|
||||||
.ascii U_BOOT_VERSION_STRING, "\0"
|
|
||||||
|
|
||||||
. = EXC_OFF_SYS_RESET
|
|
||||||
.globl _start
|
|
||||||
_start:
|
|
||||||
b boot_cold
|
|
||||||
|
|
||||||
/* the boot code is located below the exception table */
|
|
||||||
|
|
||||||
.globl _start_of_vectors
|
|
||||||
_start_of_vectors:
|
|
||||||
|
|
||||||
/* Machine check */
|
|
||||||
STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
|
|
||||||
|
|
||||||
/* Data Storage exception. */
|
|
||||||
STD_EXCEPTION(0x300, DataStorage, UnknownException)
|
|
||||||
|
|
||||||
/* Instruction Storage exception. */
|
|
||||||
STD_EXCEPTION(0x400, InstStorage, UnknownException)
|
|
||||||
|
|
||||||
/* External Interrupt exception. */
|
|
||||||
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
|
|
||||||
|
|
||||||
/* Alignment exception. */
|
|
||||||
. = 0x600
|
|
||||||
Alignment:
|
|
||||||
EXCEPTION_PROLOG(SRR0, SRR1)
|
|
||||||
mfspr r4,DAR
|
|
||||||
stw r4,_DAR(r21)
|
|
||||||
mfspr r5,DSISR
|
|
||||||
stw r5,_DSISR(r21)
|
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
||||||
EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
|
|
||||||
|
|
||||||
/* Program check exception */
|
|
||||||
. = 0x700
|
|
||||||
ProgramCheck:
|
|
||||||
EXCEPTION_PROLOG(SRR0, SRR1)
|
|
||||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
||||||
EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
|
|
||||||
MSR_KERNEL, COPY_EE)
|
|
||||||
|
|
||||||
STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
|
|
||||||
|
|
||||||
/* I guess we could implement decrementer, and may have
|
|
||||||
* to someday for timekeeping.
|
|
||||||
*/
|
|
||||||
STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
|
|
||||||
STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
|
|
||||||
STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
|
|
||||||
STD_EXCEPTION(0xc00, SystemCall, UnknownException)
|
|
||||||
STD_EXCEPTION(0xd00, SingleStep, UnknownException)
|
|
||||||
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
|
|
||||||
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
|
|
||||||
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1500, Reserved5, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1600, Reserved6, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1700, Reserved7, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1800, Reserved8, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1900, Reserved9, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
|
|
||||||
STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
|
|
||||||
|
|
||||||
.globl _end_of_vectors
|
|
||||||
_end_of_vectors:
|
|
||||||
|
|
||||||
. = 0x2000
|
|
||||||
|
|
||||||
boot_cold:
|
|
||||||
/*
|
|
||||||
* NOTE: Only Cpu 0 will ever come here. Other cores go to an
|
|
||||||
* address specified by the BPTR
|
|
||||||
*/
|
|
||||||
1:
|
|
||||||
#ifdef CONFIG_SYS_RAMBOOT
|
|
||||||
/* disable everything */
|
|
||||||
li r0, 0
|
|
||||||
mtspr HID0, r0
|
|
||||||
sync
|
|
||||||
mtmsr 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Invalidate BATs */
|
|
||||||
bl invalidate_bats
|
|
||||||
sync
|
|
||||||
/* Invalidate all of TLB before MMU turn on */
|
|
||||||
bl clear_tlbs
|
|
||||||
sync
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_L2
|
|
||||||
/* init the L2 cache */
|
|
||||||
lis r3, L2_INIT@h
|
|
||||||
ori r3, r3, L2_INIT@l
|
|
||||||
mtspr l2cr, r3
|
|
||||||
/* invalidate the L2 cache */
|
|
||||||
bl l2cache_invalidate
|
|
||||||
sync
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Calculate absolute address in FLASH and jump there
|
|
||||||
*------------------------------------------------------*/
|
|
||||||
lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
|
|
||||||
ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
|
|
||||||
addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
|
|
||||||
mtlr r3
|
|
||||||
blr
|
|
||||||
|
|
||||||
in_flash:
|
|
||||||
/* let the C-code set up the rest */
|
|
||||||
/* */
|
|
||||||
/* Be careful to keep code relocatable ! */
|
|
||||||
/*------------------------------------------------------*/
|
|
||||||
/* perform low-level init */
|
|
||||||
|
|
||||||
/* enable extended addressing */
|
|
||||||
bl enable_ext_addr
|
|
||||||
|
|
||||||
/* setup the bats */
|
|
||||||
bl early_bats
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Cache must be enabled here for stack-in-cache trick.
|
|
||||||
* This means we need to enable the BATS.
|
|
||||||
* Cache should be turned on after BATs, since by default
|
|
||||||
* everything is write-through.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* enable address translation */
|
|
||||||
mfmsr r5
|
|
||||||
ori r5, r5, (MSR_IR | MSR_DR)
|
|
||||||
lis r3,addr_trans_enabled@h
|
|
||||||
ori r3, r3, addr_trans_enabled@l
|
|
||||||
mtspr SPRN_SRR0,r3
|
|
||||||
mtspr SPRN_SRR1,r5
|
|
||||||
rfi
|
|
||||||
|
|
||||||
addr_trans_enabled:
|
|
||||||
/* enable and invalidate the data cache */
|
|
||||||
/* bl l1dcache_enable */
|
|
||||||
bl dcache_enable
|
|
||||||
sync
|
|
||||||
|
|
||||||
#if 1
|
|
||||||
bl icache_enable
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_INIT_RAM_LOCK
|
|
||||||
bl lock_ram_in_cache
|
|
||||||
sync
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
|
||||||
bl setup_ccsrbar
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* set up the stack pointer in our newly created
|
|
||||||
* cache-ram (r1) */
|
|
||||||
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
|
|
||||||
ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
|
|
||||||
|
|
||||||
li r0, 0 /* Make room for stack frame header and */
|
|
||||||
stwu r0, -4(r1) /* clear final stack frame so that */
|
|
||||||
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
|
|
||||||
|
|
||||||
GET_GOT /* initialize GOT access */
|
|
||||||
|
|
||||||
/* run low-level CPU init code (from Flash) */
|
|
||||||
bl cpu_init_f
|
|
||||||
sync
|
|
||||||
|
|
||||||
#ifdef RUN_DIAG
|
|
||||||
|
|
||||||
/* Load PX_AUX register address in r4 */
|
|
||||||
lis r4, PIXIS_BASE@h
|
|
||||||
ori r4, r4, 0x6
|
|
||||||
/* Load contents of PX_AUX in r3 bits 24 to 31*/
|
|
||||||
lbz r3, 0(r4)
|
|
||||||
|
|
||||||
/* Mask and obtain the bit in r3 */
|
|
||||||
rlwinm. r3, r3, 0, 24, 24
|
|
||||||
/* If not zero, jump and continue with u-boot */
|
|
||||||
bne diag_done
|
|
||||||
|
|
||||||
/* Load back contents of PX_AUX in r3 bits 24 to 31 */
|
|
||||||
lbz r3, 0(r4)
|
|
||||||
/* Set the MSB of the register value */
|
|
||||||
ori r3, r3, 0x80
|
|
||||||
/* Write value in r3 back to PX_AUX */
|
|
||||||
stb r3, 0(r4)
|
|
||||||
|
|
||||||
/* Get the address to jump to in r3*/
|
|
||||||
lis r3, CONFIG_SYS_DIAG_ADDR@h
|
|
||||||
ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
|
|
||||||
|
|
||||||
/* Load the LR with the branch address */
|
|
||||||
mtlr r3
|
|
||||||
|
|
||||||
/* Branch to diagnostic */
|
|
||||||
blr
|
|
||||||
|
|
||||||
diag_done:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* bl l2cache_enable */
|
|
||||||
|
|
||||||
/* run 1st part of board init code (from Flash) */
|
|
||||||
li r3, 0 /* clear boot_flag for calling board_init_f */
|
|
||||||
bl board_init_f
|
|
||||||
sync
|
|
||||||
|
|
||||||
/* NOTREACHED - board_init_f() does not return */
|
|
||||||
|
|
||||||
.globl invalidate_bats
|
|
||||||
invalidate_bats:
|
|
||||||
|
|
||||||
li r0, 0
|
|
||||||
/* invalidate BATs */
|
|
||||||
mtspr IBAT0U, r0
|
|
||||||
mtspr IBAT1U, r0
|
|
||||||
mtspr IBAT2U, r0
|
|
||||||
mtspr IBAT3U, r0
|
|
||||||
mtspr IBAT4U, r0
|
|
||||||
mtspr IBAT5U, r0
|
|
||||||
mtspr IBAT6U, r0
|
|
||||||
mtspr IBAT7U, r0
|
|
||||||
|
|
||||||
isync
|
|
||||||
mtspr DBAT0U, r0
|
|
||||||
mtspr DBAT1U, r0
|
|
||||||
mtspr DBAT2U, r0
|
|
||||||
mtspr DBAT3U, r0
|
|
||||||
mtspr DBAT4U, r0
|
|
||||||
mtspr DBAT5U, r0
|
|
||||||
mtspr DBAT6U, r0
|
|
||||||
mtspr DBAT7U, r0
|
|
||||||
|
|
||||||
isync
|
|
||||||
sync
|
|
||||||
blr
|
|
||||||
|
|
||||||
#define CONFIG_BAT_PAIR(n) \
|
|
||||||
lis r4, CONFIG_SYS_IBAT##n##L@h; \
|
|
||||||
ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
|
|
||||||
lis r3, CONFIG_SYS_IBAT##n##U@h; \
|
|
||||||
ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
|
|
||||||
mtspr IBAT##n##L, r4; \
|
|
||||||
mtspr IBAT##n##U, r3; \
|
|
||||||
lis r4, CONFIG_SYS_DBAT##n##L@h; \
|
|
||||||
ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
|
|
||||||
lis r3, CONFIG_SYS_DBAT##n##U@h; \
|
|
||||||
ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
|
|
||||||
mtspr DBAT##n##L, r4; \
|
|
||||||
mtspr DBAT##n##U, r3;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* setup_bats:
|
|
||||||
*
|
|
||||||
* Set up the final BAT registers now that setup is done.
|
|
||||||
*
|
|
||||||
* Assumes that:
|
|
||||||
* 1) Address translation is enabled upon entry
|
|
||||||
* 2) The boot rom is still accessible via 1:1 translation
|
|
||||||
*/
|
|
||||||
.globl setup_bats
|
|
||||||
setup_bats:
|
|
||||||
mflr r5
|
|
||||||
sync
|
|
||||||
|
|
||||||
/*
|
|
||||||
* When we disable address translation, we will get 1:1 (VA==PA)
|
|
||||||
* translation. The only place we know for sure is safe for that is
|
|
||||||
* the bootrom where we originally started out. Pop back into there.
|
|
||||||
*/
|
|
||||||
lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
|
|
||||||
ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
|
|
||||||
addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
|
|
||||||
|
|
||||||
/* disable address translation */
|
|
||||||
mfmsr r3
|
|
||||||
rlwinm r3, r3, 0, 28, 25
|
|
||||||
mtspr SRR0, r4
|
|
||||||
mtspr SRR1, r3
|
|
||||||
rfi
|
|
||||||
|
|
||||||
trans_disabled:
|
|
||||||
#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
|
|
||||||
&& defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
|
|
||||||
CONFIG_BAT_PAIR(0)
|
|
||||||
#endif
|
|
||||||
CONFIG_BAT_PAIR(1)
|
|
||||||
CONFIG_BAT_PAIR(2)
|
|
||||||
CONFIG_BAT_PAIR(3)
|
|
||||||
CONFIG_BAT_PAIR(4)
|
|
||||||
CONFIG_BAT_PAIR(5)
|
|
||||||
CONFIG_BAT_PAIR(6)
|
|
||||||
CONFIG_BAT_PAIR(7)
|
|
||||||
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* Turn translation back on and return */
|
|
||||||
mfmsr r3
|
|
||||||
ori r3, r3, (MSR_IR | MSR_DR)
|
|
||||||
mtspr SPRN_SRR0,r5
|
|
||||||
mtspr SPRN_SRR1,r3
|
|
||||||
rfi
|
|
||||||
|
|
||||||
/*
|
|
||||||
* early_bats:
|
|
||||||
*
|
|
||||||
* Set up bats needed early on - this is usually the BAT for the
|
|
||||||
* stack-in-cache, the Flash, and CCSR space
|
|
||||||
*/
|
|
||||||
.globl early_bats
|
|
||||||
early_bats:
|
|
||||||
/* IBAT 3 */
|
|
||||||
lis r4, CONFIG_SYS_IBAT3L@h
|
|
||||||
ori r4, r4, CONFIG_SYS_IBAT3L@l
|
|
||||||
lis r3, CONFIG_SYS_IBAT3U@h
|
|
||||||
ori r3, r3, CONFIG_SYS_IBAT3U@l
|
|
||||||
mtspr IBAT3L, r4
|
|
||||||
mtspr IBAT3U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* DBAT 3 */
|
|
||||||
lis r4, CONFIG_SYS_DBAT3L@h
|
|
||||||
ori r4, r4, CONFIG_SYS_DBAT3L@l
|
|
||||||
lis r3, CONFIG_SYS_DBAT3U@h
|
|
||||||
ori r3, r3, CONFIG_SYS_DBAT3U@l
|
|
||||||
mtspr DBAT3L, r4
|
|
||||||
mtspr DBAT3U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* IBAT 5 */
|
|
||||||
lis r4, CONFIG_SYS_IBAT5L@h
|
|
||||||
ori r4, r4, CONFIG_SYS_IBAT5L@l
|
|
||||||
lis r3, CONFIG_SYS_IBAT5U@h
|
|
||||||
ori r3, r3, CONFIG_SYS_IBAT5U@l
|
|
||||||
mtspr IBAT5L, r4
|
|
||||||
mtspr IBAT5U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* DBAT 5 */
|
|
||||||
lis r4, CONFIG_SYS_DBAT5L@h
|
|
||||||
ori r4, r4, CONFIG_SYS_DBAT5L@l
|
|
||||||
lis r3, CONFIG_SYS_DBAT5U@h
|
|
||||||
ori r3, r3, CONFIG_SYS_DBAT5U@l
|
|
||||||
mtspr DBAT5L, r4
|
|
||||||
mtspr DBAT5U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* IBAT 6 */
|
|
||||||
lis r4, CONFIG_SYS_IBAT6L_EARLY@h
|
|
||||||
ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
|
|
||||||
lis r3, CONFIG_SYS_IBAT6U_EARLY@h
|
|
||||||
ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
|
|
||||||
mtspr IBAT6L, r4
|
|
||||||
mtspr IBAT6U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* DBAT 6 */
|
|
||||||
lis r4, CONFIG_SYS_DBAT6L_EARLY@h
|
|
||||||
ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
|
|
||||||
lis r3, CONFIG_SYS_DBAT6U_EARLY@h
|
|
||||||
ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
|
|
||||||
mtspr DBAT6L, r4
|
|
||||||
mtspr DBAT6U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
|
||||||
/* IBAT 7 */
|
|
||||||
lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
|
|
||||||
ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
|
|
||||||
lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
|
|
||||||
ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
|
|
||||||
mtspr IBAT7L, r4
|
|
||||||
mtspr IBAT7U, r3
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* DBAT 7 */
|
|
||||||
lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
|
|
||||||
ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
|
|
||||||
lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
|
|
||||||
ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
|
|
||||||
mtspr DBAT7L, r4
|
|
||||||
mtspr DBAT7U, r3
|
|
||||||
isync
|
|
||||||
#endif
|
|
||||||
blr
|
|
||||||
|
|
||||||
.globl clear_tlbs
|
|
||||||
clear_tlbs:
|
|
||||||
addis r3, 0, 0x0000
|
|
||||||
addis r5, 0, 0x4
|
|
||||||
isync
|
|
||||||
tlblp:
|
|
||||||
tlbie r3
|
|
||||||
sync
|
|
||||||
addi r3, r3, 0x1000
|
|
||||||
cmp 0, 0, r3, r5
|
|
||||||
blt tlblp
|
|
||||||
blr
|
|
||||||
|
|
||||||
.globl disable_addr_trans
|
|
||||||
disable_addr_trans:
|
|
||||||
/* disable address translation */
|
|
||||||
mflr r4
|
|
||||||
mfmsr r3
|
|
||||||
andi. r0, r3, (MSR_IR | MSR_DR)
|
|
||||||
beqlr
|
|
||||||
andc r3, r3, r0
|
|
||||||
mtspr SRR0, r4
|
|
||||||
mtspr SRR1, r3
|
|
||||||
rfi
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This code finishes saving the registers to the exception frame
|
|
||||||
* and jumps to the appropriate handler for the exception.
|
|
||||||
* Register r21 is pointer into trap frame, r1 has new stack pointer.
|
|
||||||
*/
|
|
||||||
.globl transfer_to_handler
|
|
||||||
transfer_to_handler:
|
|
||||||
stw r22,_NIP(r21)
|
|
||||||
lis r22,MSR_POW@h
|
|
||||||
andc r23,r23,r22
|
|
||||||
stw r23,_MSR(r21)
|
|
||||||
SAVE_GPR(7, r21)
|
|
||||||
SAVE_4GPRS(8, r21)
|
|
||||||
SAVE_8GPRS(12, r21)
|
|
||||||
SAVE_8GPRS(24, r21)
|
|
||||||
mflr r23
|
|
||||||
andi. r24,r23,0x3f00 /* get vector offset */
|
|
||||||
stw r24,TRAP(r21)
|
|
||||||
li r22,0
|
|
||||||
stw r22,RESULT(r21)
|
|
||||||
mtspr SPRG2,r22 /* r1 is now kernel sp */
|
|
||||||
lwz r24,0(r23) /* virtual address of handler */
|
|
||||||
lwz r23,4(r23) /* where to go when done */
|
|
||||||
mtspr SRR0,r24
|
|
||||||
mtspr SRR1,r20
|
|
||||||
mtlr r23
|
|
||||||
SYNC
|
|
||||||
rfi /* jump to handler, enable MMU */
|
|
||||||
|
|
||||||
int_return:
|
|
||||||
mfmsr r28 /* Disable interrupts */
|
|
||||||
li r4,0
|
|
||||||
ori r4,r4,MSR_EE
|
|
||||||
andc r28,r28,r4
|
|
||||||
SYNC /* Some chip revs need this... */
|
|
||||||
mtmsr r28
|
|
||||||
SYNC
|
|
||||||
lwz r2,_CTR(r1)
|
|
||||||
lwz r0,_LINK(r1)
|
|
||||||
mtctr r2
|
|
||||||
mtlr r0
|
|
||||||
lwz r2,_XER(r1)
|
|
||||||
lwz r0,_CCR(r1)
|
|
||||||
mtspr XER,r2
|
|
||||||
mtcrf 0xFF,r0
|
|
||||||
REST_10GPRS(3, r1)
|
|
||||||
REST_10GPRS(13, r1)
|
|
||||||
REST_8GPRS(23, r1)
|
|
||||||
REST_GPR(31, r1)
|
|
||||||
lwz r2,_NIP(r1) /* Restore environment */
|
|
||||||
lwz r0,_MSR(r1)
|
|
||||||
mtspr SRR0,r2
|
|
||||||
mtspr SRR1,r0
|
|
||||||
lwz r0,GPR0(r1)
|
|
||||||
lwz r2,GPR2(r1)
|
|
||||||
lwz r1,GPR1(r1)
|
|
||||||
SYNC
|
|
||||||
rfi
|
|
||||||
|
|
||||||
.globl dc_read
|
|
||||||
dc_read:
|
|
||||||
blr
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: in8
|
|
||||||
* Description: Input 8 bits
|
|
||||||
*/
|
|
||||||
.globl in8
|
|
||||||
in8:
|
|
||||||
lbz r3,0x0000(r3)
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: out8
|
|
||||||
* Description: Output 8 bits
|
|
||||||
*/
|
|
||||||
.globl out8
|
|
||||||
out8:
|
|
||||||
stb r4,0x0000(r3)
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: out16
|
|
||||||
* Description: Output 16 bits
|
|
||||||
*/
|
|
||||||
.globl out16
|
|
||||||
out16:
|
|
||||||
sth r4,0x0000(r3)
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: out16r
|
|
||||||
* Description: Byte reverse and output 16 bits
|
|
||||||
*/
|
|
||||||
.globl out16r
|
|
||||||
out16r:
|
|
||||||
sthbrx r4,r0,r3
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: out32
|
|
||||||
* Description: Output 32 bits
|
|
||||||
*/
|
|
||||||
.globl out32
|
|
||||||
out32:
|
|
||||||
stw r4,0x0000(r3)
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: out32r
|
|
||||||
* Description: Byte reverse and output 32 bits
|
|
||||||
*/
|
|
||||||
.globl out32r
|
|
||||||
out32r:
|
|
||||||
stwbrx r4,r0,r3
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: in16
|
|
||||||
* Description: Input 16 bits
|
|
||||||
*/
|
|
||||||
.globl in16
|
|
||||||
in16:
|
|
||||||
lhz r3,0x0000(r3)
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: in16r
|
|
||||||
* Description: Input 16 bits and byte reverse
|
|
||||||
*/
|
|
||||||
.globl in16r
|
|
||||||
in16r:
|
|
||||||
lhbrx r3,r0,r3
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: in32
|
|
||||||
* Description: Input 32 bits
|
|
||||||
*/
|
|
||||||
.globl in32
|
|
||||||
in32:
|
|
||||||
lwz 3,0x0000(3)
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Function: in32r
|
|
||||||
* Description: Input 32 bits and byte reverse
|
|
||||||
*/
|
|
||||||
.globl in32r
|
|
||||||
in32r:
|
|
||||||
lwbrx r3,r0,r3
|
|
||||||
blr
|
|
||||||
|
|
||||||
/*
|
|
||||||
* void relocate_code(addr_sp, gd, addr_moni)
|
|
||||||
*
|
|
||||||
* This "function" does not return, instead it continues in RAM
|
|
||||||
* after relocating the monitor code.
|
|
||||||
*
|
|
||||||
* r3 = dest
|
|
||||||
* r4 = src
|
|
||||||
* r5 = length in bytes
|
|
||||||
* r6 = cachelinesize
|
|
||||||
*/
|
|
||||||
.globl relocate_code
|
|
||||||
relocate_code:
|
|
||||||
|
|
||||||
mr r1, r3 /* Set new stack pointer */
|
|
||||||
mr r9, r4 /* Save copy of Global Data pointer */
|
|
||||||
mr r10, r5 /* Save copy of Destination Address */
|
|
||||||
|
|
||||||
GET_GOT
|
|
||||||
mr r3, r5 /* Destination Address */
|
|
||||||
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
|
|
||||||
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
|
|
||||||
lwz r5, GOT(__init_end)
|
|
||||||
sub r5, r5, r4
|
|
||||||
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Fix GOT pointer:
|
|
||||||
*
|
|
||||||
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
|
|
||||||
*
|
|
||||||
* Offset:
|
|
||||||
*/
|
|
||||||
sub r15, r10, r4
|
|
||||||
|
|
||||||
/* First our own GOT */
|
|
||||||
add r12, r12, r15
|
|
||||||
/* then the one used by the C code */
|
|
||||||
add r30, r30, r15
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Now relocate code
|
|
||||||
*/
|
|
||||||
cmplw cr1,r3,r4
|
|
||||||
addi r0,r5,3
|
|
||||||
srwi. r0,r0,2
|
|
||||||
beq cr1,4f /* In place copy is not necessary */
|
|
||||||
beq 7f /* Protect against 0 count */
|
|
||||||
mtctr r0
|
|
||||||
bge cr1,2f
|
|
||||||
|
|
||||||
la r8,-4(r4)
|
|
||||||
la r7,-4(r3)
|
|
||||||
1: lwzu r0,4(r8)
|
|
||||||
stwu r0,4(r7)
|
|
||||||
bdnz 1b
|
|
||||||
b 4f
|
|
||||||
|
|
||||||
2: slwi r0,r0,2
|
|
||||||
add r8,r4,r0
|
|
||||||
add r7,r3,r0
|
|
||||||
3: lwzu r0,-4(r8)
|
|
||||||
stwu r0,-4(r7)
|
|
||||||
bdnz 3b
|
|
||||||
/*
|
|
||||||
* Now flush the cache: note that we must start from a cache aligned
|
|
||||||
* address. Otherwise we might miss one cache line.
|
|
||||||
*/
|
|
||||||
4: cmpwi r6,0
|
|
||||||
add r5,r3,r5
|
|
||||||
beq 7f /* Always flush prefetch queue in any case */
|
|
||||||
subi r0,r6,1
|
|
||||||
andc r3,r3,r0
|
|
||||||
mr r4,r3
|
|
||||||
5: dcbst 0,r4
|
|
||||||
add r4,r4,r6
|
|
||||||
cmplw r4,r5
|
|
||||||
blt 5b
|
|
||||||
sync /* Wait for all dcbst to complete on bus */
|
|
||||||
mr r4,r3
|
|
||||||
6: icbi 0,r4
|
|
||||||
add r4,r4,r6
|
|
||||||
cmplw r4,r5
|
|
||||||
blt 6b
|
|
||||||
7: sync /* Wait for all icbi to complete on bus */
|
|
||||||
isync
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We are done. Do not return, instead branch to second part of board
|
|
||||||
* initialization, now running from RAM.
|
|
||||||
*/
|
|
||||||
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
||||||
mtlr r0
|
|
||||||
blr
|
|
||||||
|
|
||||||
in_ram:
|
|
||||||
/*
|
|
||||||
* Relocation Function, r12 point to got2+0x8000
|
|
||||||
*
|
|
||||||
* Adjust got2 pointers, no need to check for 0, this code
|
|
||||||
* already puts a few entries in the table.
|
|
||||||
*/
|
|
||||||
li r0,__got2_entries@sectoff@l
|
|
||||||
la r3,GOT(_GOT2_TABLE_)
|
|
||||||
lwz r11,GOT(_GOT2_TABLE_)
|
|
||||||
mtctr r0
|
|
||||||
sub r11,r3,r11
|
|
||||||
addi r3,r3,-4
|
|
||||||
1: lwzu r0,4(r3)
|
|
||||||
cmpwi r0,0
|
|
||||||
beq- 2f
|
|
||||||
add r0,r0,r11
|
|
||||||
stw r0,0(r3)
|
|
||||||
2: bdnz 1b
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Now adjust the fixups and the pointers to the fixups
|
|
||||||
* in case we need to move ourselves again.
|
|
||||||
*/
|
|
||||||
li r0,__fixup_entries@sectoff@l
|
|
||||||
lwz r3,GOT(_FIXUP_TABLE_)
|
|
||||||
cmpwi r0,0
|
|
||||||
mtctr r0
|
|
||||||
addi r3,r3,-4
|
|
||||||
beq 4f
|
|
||||||
3: lwzu r4,4(r3)
|
|
||||||
lwzux r0,r4,r11
|
|
||||||
cmpwi r0,0
|
|
||||||
add r0,r0,r11
|
|
||||||
stw r4,0(r3)
|
|
||||||
beq- 5f
|
|
||||||
stw r0,0(r4)
|
|
||||||
5: bdnz 3b
|
|
||||||
4:
|
|
||||||
/* clear_bss: */
|
|
||||||
/*
|
|
||||||
* Now clear BSS segment
|
|
||||||
*/
|
|
||||||
lwz r3,GOT(__bss_start)
|
|
||||||
lwz r4,GOT(__bss_end)
|
|
||||||
|
|
||||||
cmplw 0, r3, r4
|
|
||||||
beq 6f
|
|
||||||
|
|
||||||
li r0, 0
|
|
||||||
5:
|
|
||||||
stw r0, 0(r3)
|
|
||||||
addi r3, r3, 4
|
|
||||||
cmplw 0, r3, r4
|
|
||||||
bne 5b
|
|
||||||
6:
|
|
||||||
mr r3, r9 /* Init Date pointer */
|
|
||||||
mr r4, r10 /* Destination Address */
|
|
||||||
bl board_init_r
|
|
||||||
|
|
||||||
/* not reached - end relocate_code */
|
|
||||||
/*-----------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copy exception vector code to low memory
|
|
||||||
*
|
|
||||||
* r3: dest_addr
|
|
||||||
* r7: source address, r8: end address, r9: target address
|
|
||||||
*/
|
|
||||||
.globl trap_init
|
|
||||||
trap_init:
|
|
||||||
mflr r4 /* save link register */
|
|
||||||
GET_GOT
|
|
||||||
lwz r7, GOT(_start)
|
|
||||||
lwz r8, GOT(_end_of_vectors)
|
|
||||||
|
|
||||||
li r9, 0x100 /* reset vector always at 0x100 */
|
|
||||||
|
|
||||||
cmplw 0, r7, r8
|
|
||||||
bgelr /* return if r7>=r8 - just in case */
|
|
||||||
1:
|
|
||||||
lwz r0, 0(r7)
|
|
||||||
stw r0, 0(r9)
|
|
||||||
addi r7, r7, 4
|
|
||||||
addi r9, r9, 4
|
|
||||||
cmplw 0, r7, r8
|
|
||||||
bne 1b
|
|
||||||
|
|
||||||
/*
|
|
||||||
* relocate `hdlr' and `int_return' entries
|
|
||||||
*/
|
|
||||||
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
|
||||||
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
|
||||||
2:
|
|
||||||
bl trap_reloc
|
|
||||||
addi r7, r7, 0x100 /* next exception vector */
|
|
||||||
cmplw 0, r7, r8
|
|
||||||
blt 2b
|
|
||||||
|
|
||||||
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
|
||||||
bl trap_reloc
|
|
||||||
|
|
||||||
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
|
||||||
bl trap_reloc
|
|
||||||
|
|
||||||
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
|
||||||
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
|
||||||
3:
|
|
||||||
bl trap_reloc
|
|
||||||
addi r7, r7, 0x100 /* next exception vector */
|
|
||||||
cmplw 0, r7, r8
|
|
||||||
blt 3b
|
|
||||||
|
|
||||||
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
|
|
||||||
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
||||||
4:
|
|
||||||
bl trap_reloc
|
|
||||||
addi r7, r7, 0x100 /* next exception vector */
|
|
||||||
cmplw 0, r7, r8
|
|
||||||
blt 4b
|
|
||||||
|
|
||||||
/* enable execptions from RAM vectors */
|
|
||||||
mfmsr r7
|
|
||||||
li r8,MSR_IP
|
|
||||||
andc r7,r7,r8
|
|
||||||
ori r7,r7,MSR_ME /* Enable Machine Check */
|
|
||||||
mtmsr r7
|
|
||||||
|
|
||||||
mtlr r4 /* restore link register */
|
|
||||||
blr
|
|
||||||
|
|
||||||
.globl enable_ext_addr
|
|
||||||
enable_ext_addr:
|
|
||||||
mfspr r0, HID0
|
|
||||||
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
|
|
||||||
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
|
|
||||||
mtspr HID0, r0
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
|
||||||
.globl setup_ccsrbar
|
|
||||||
setup_ccsrbar:
|
|
||||||
/* Special sequence needed to update CCSRBAR itself */
|
|
||||||
lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
|
|
||||||
ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
|
|
||||||
|
|
||||||
lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
|
|
||||||
ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
|
|
||||||
srwi r5,r5,12
|
|
||||||
li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
|
|
||||||
rlwimi r5,r6,20,8,11
|
|
||||||
stw r5, 0(r4) /* Store physical value of CCSR */
|
|
||||||
isync
|
|
||||||
|
|
||||||
lis r5, CONFIG_SYS_TEXT_BASE@h
|
|
||||||
ori r5,r5,CONFIG_SYS_TEXT_BASE@l
|
|
||||||
lwz r5, 0(r5)
|
|
||||||
isync
|
|
||||||
|
|
||||||
/* Use VA of CCSR to do read */
|
|
||||||
lis r3, CONFIG_SYS_CCSRBAR@h
|
|
||||||
lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
|
|
||||||
isync
|
|
||||||
|
|
||||||
blr
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_INIT_RAM_LOCK
|
|
||||||
lock_ram_in_cache:
|
|
||||||
/* Allocate Initial RAM in data cache.
|
|
||||||
*/
|
|
||||||
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
|
|
||||||
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
|
|
||||||
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
|
|
||||||
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
|
|
||||||
mtctr r4
|
|
||||||
1:
|
|
||||||
dcbz r0, r3
|
|
||||||
addi r3, r3, 32
|
|
||||||
bdnz 1b
|
|
||||||
#if 1
|
|
||||||
/* Lock the data cache */
|
|
||||||
mfspr r0, HID0
|
|
||||||
ori r0, r0, 0x1000
|
|
||||||
sync
|
|
||||||
mtspr HID0, r0
|
|
||||||
sync
|
|
||||||
blr
|
|
||||||
#endif
|
|
||||||
#if 0
|
|
||||||
/* Lock the first way of the data cache */
|
|
||||||
mfspr r0, LDSTCR
|
|
||||||
ori r0, r0, 0x0080
|
|
||||||
#if defined(CONFIG_ALTIVEC)
|
|
||||||
dssall
|
|
||||||
#endif
|
|
||||||
sync
|
|
||||||
mtspr LDSTCR, r0
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
blr
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.globl unlock_ram_in_cache
|
|
||||||
unlock_ram_in_cache:
|
|
||||||
/* invalidate the INIT_RAM section */
|
|
||||||
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
|
|
||||||
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
|
|
||||||
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
|
|
||||||
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
|
|
||||||
mtctr r4
|
|
||||||
1: icbi r0, r3
|
|
||||||
addi r3, r3, 32
|
|
||||||
bdnz 1b
|
|
||||||
sync /* Wait for all icbi to complete on bus */
|
|
||||||
isync
|
|
||||||
#if 1
|
|
||||||
/* Unlock the data cache and invalidate it */
|
|
||||||
mfspr r0, HID0
|
|
||||||
li r3,0x1000
|
|
||||||
andc r0,r0,r3
|
|
||||||
li r3,0x0400
|
|
||||||
or r0,r0,r3
|
|
||||||
sync
|
|
||||||
mtspr HID0, r0
|
|
||||||
sync
|
|
||||||
blr
|
|
||||||
#endif
|
|
||||||
#if 0
|
|
||||||
/* Unlock the first way of the data cache */
|
|
||||||
mfspr r0, LDSTCR
|
|
||||||
li r3,0x0080
|
|
||||||
andc r0,r0,r3
|
|
||||||
#ifdef CONFIG_ALTIVEC
|
|
||||||
dssall
|
|
||||||
#endif
|
|
||||||
sync
|
|
||||||
mtspr LDSTCR, r0
|
|
||||||
sync
|
|
||||||
isync
|
|
||||||
li r3,0x0400
|
|
||||||
or r0,r0,r3
|
|
||||||
sync
|
|
||||||
mtspr HID0, r0
|
|
||||||
sync
|
|
||||||
blr
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,199 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
|
||||||
*
|
|
||||||
* Modified by Cort Dougan (cort@cs.nmt.edu)
|
|
||||||
* and Paul Mackerras (paulus@cs.anu.edu.au)
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This file handles the architecture-dependent parts of hardware exceptions
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/ptrace.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <kgdb.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
/* Returns 0 if exception not found and fixup otherwise. */
|
|
||||||
extern unsigned long search_exception_table(unsigned long);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* End of addressable memory. This may be less than the actual
|
|
||||||
* amount of memory on the system if we're unable to keep all
|
|
||||||
* the memory mapped in.
|
|
||||||
*/
|
|
||||||
#define END_OF_MEM (gd->ram_base + get_effective_memsize())
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Trap & Exception support
|
|
||||||
*/
|
|
||||||
|
|
||||||
static void print_backtrace(unsigned long *sp)
|
|
||||||
{
|
|
||||||
int cnt = 0;
|
|
||||||
unsigned long i;
|
|
||||||
|
|
||||||
printf("Call backtrace: ");
|
|
||||||
while (sp) {
|
|
||||||
if ((uint) sp > END_OF_MEM)
|
|
||||||
break;
|
|
||||||
|
|
||||||
i = sp[1];
|
|
||||||
if (cnt++ % 7 == 0)
|
|
||||||
printf("\n");
|
|
||||||
printf("%08lX ", i);
|
|
||||||
if (cnt > 32)
|
|
||||||
break;
|
|
||||||
sp = (unsigned long *)*sp;
|
|
||||||
}
|
|
||||||
printf("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
void show_regs(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
printf("NIP: %08lX XER: %08lX LR: %08lX REGS:"
|
|
||||||
" %p TRAP: %04lx DAR: %08lX\n",
|
|
||||||
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
|
|
||||||
printf("MSR: %08lx EE: %01x PR: %01x FP:"
|
|
||||||
" %01x ME: %01x IR/DR: %01x%01x\n",
|
|
||||||
regs->msr, regs->msr & MSR_EE ? 1 : 0,
|
|
||||||
regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
|
|
||||||
regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
|
|
||||||
regs->msr & MSR_DR ? 1 : 0);
|
|
||||||
|
|
||||||
printf("\n");
|
|
||||||
for (i = 0; i < 32; i++) {
|
|
||||||
if ((i % 8) == 0) {
|
|
||||||
printf("GPR%02d: ", i);
|
|
||||||
}
|
|
||||||
|
|
||||||
printf("%08lX ", regs->gpr[i]);
|
|
||||||
if ((i % 8) == 7) {
|
|
||||||
printf("\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static void _exception(int signr, struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
show_regs(regs);
|
|
||||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
|
||||||
panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
|
|
||||||
}
|
|
||||||
|
|
||||||
void MachineCheckException(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
unsigned long fixup;
|
|
||||||
|
|
||||||
/* Probing PCI using config cycles cause this exception
|
|
||||||
* when a device is not present. Catch it and return to
|
|
||||||
* the PCI exception handler.
|
|
||||||
*/
|
|
||||||
if ((fixup = search_exception_table(regs->nip)) != 0) {
|
|
||||||
regs->nip = fixup;
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
|
|
||||||
return;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
printf("Machine check in kernel mode.\n");
|
|
||||||
printf("Caused by (from msr): ");
|
|
||||||
printf("regs %p ", regs);
|
|
||||||
switch ( regs->msr & 0x001F0000) {
|
|
||||||
case (0x80000000>>11):
|
|
||||||
printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0));
|
|
||||||
break;
|
|
||||||
case (0x80000000>>12):
|
|
||||||
printf("Machine check signal - probably due to mm fault\n"
|
|
||||||
"with mmu off\n");
|
|
||||||
break;
|
|
||||||
case (0x80000000 >> 13):
|
|
||||||
printf("Transfer error ack signal\n");
|
|
||||||
break;
|
|
||||||
case (0x80000000 >> 14):
|
|
||||||
printf("Data parity signal\n");
|
|
||||||
break;
|
|
||||||
case (0x80000000 >> 15):
|
|
||||||
printf("Address parity signal\n");
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printf("Unknown values in msr\n");
|
|
||||||
}
|
|
||||||
show_regs(regs);
|
|
||||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
|
||||||
panic("machine check");
|
|
||||||
}
|
|
||||||
|
|
||||||
void AlignmentException(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
|
|
||||||
return;
|
|
||||||
#endif
|
|
||||||
show_regs(regs);
|
|
||||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
|
||||||
panic("Alignment Exception");
|
|
||||||
}
|
|
||||||
|
|
||||||
void ProgramCheckException(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
|
|
||||||
int i, j;
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
|
|
||||||
return;
|
|
||||||
#endif
|
|
||||||
show_regs(regs);
|
|
||||||
|
|
||||||
p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0);
|
|
||||||
p -= 32;
|
|
||||||
for (i = 0; i < 256; i += 16) {
|
|
||||||
printf("%08x: ", (unsigned int)p + i);
|
|
||||||
for (j = 0; j < 16; j++) {
|
|
||||||
printf("%02x ", p[i + j]);
|
|
||||||
}
|
|
||||||
printf("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
|
||||||
panic("Program Check Exception");
|
|
||||||
}
|
|
||||||
|
|
||||||
void SoftEmuException(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
|
|
||||||
return;
|
|
||||||
#endif
|
|
||||||
show_regs(regs);
|
|
||||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
|
||||||
panic("Software Emulation Exception");
|
|
||||||
}
|
|
||||||
|
|
||||||
void UnknownException(struct pt_regs *regs)
|
|
||||||
{
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
if (debugger_exception_handler && (*debugger_exception_handler) (regs))
|
|
||||||
return;
|
|
||||||
#endif
|
|
||||||
printf("UnknownException regs@%lx\n", (ulong)regs);
|
|
||||||
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
|
|
||||||
regs->nip, regs->msr, regs->trap);
|
|
||||||
_exception(0, regs);
|
|
||||||
}
|
|
||||||
|
|
@ -1,77 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2006, 2007 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc)
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
arch/powerpc/cpu/mpc86xx/start.o (.text*)
|
|
||||||
arch/powerpc/cpu/mpc86xx/traps.o (.text*)
|
|
||||||
*(.text*)
|
|
||||||
}
|
|
||||||
_etext = .;
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
|
||||||
_erotext = .;
|
|
||||||
PROVIDE (erotext = .);
|
|
||||||
.reloc :
|
|
||||||
{
|
|
||||||
_GOT2_TABLE_ = .;
|
|
||||||
KEEP(*(.got2))
|
|
||||||
KEEP(*(.got))
|
|
||||||
_FIXUP_TABLE_ = .;
|
|
||||||
KEEP(*(.fixup))
|
|
||||||
}
|
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data*)
|
|
||||||
*(.sdata*)
|
|
||||||
}
|
|
||||||
_edata = .;
|
|
||||||
PROVIDE (edata = .);
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
.u_boot_list : {
|
|
||||||
KEEP(*(SORT(.u_boot_list*)));
|
|
||||||
}
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
__start___ex_table = .;
|
|
||||||
__ex_table : { *(__ex_table) }
|
|
||||||
__stop___ex_table = .;
|
|
||||||
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_begin = .;
|
|
||||||
.text.init : { *(.text.init) }
|
|
||||||
.data.init : { *(.data.init) }
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_end = .;
|
|
||||||
|
|
||||||
__bss_start = .;
|
|
||||||
.bss (NOLOAD) :
|
|
||||||
{
|
|
||||||
*(.bss*)
|
|
||||||
*(.sbss*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
}
|
|
||||||
__bss_end = . ;
|
|
||||||
PROVIDE (end = .);
|
|
||||||
}
|
|
||||||
|
|
@ -10,10 +10,6 @@
|
||||||
#include <asm/config_mpc85xx.h>
|
#include <asm/config_mpc85xx.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_MPC86xx
|
|
||||||
#include <asm/config_mpc86xx.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef HWCONFIG_BUFFER_SIZE
|
#ifndef HWCONFIG_BUFFER_SIZE
|
||||||
#define HWCONFIG_BUFFER_SIZE 256
|
#define HWCONFIG_BUFFER_SIZE 256
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _ASM_MPC86xx_CONFIG_H_
|
|
||||||
#define _ASM_MPC86xx_CONFIG_H_
|
|
||||||
|
|
||||||
#endif /* _ASM_MPC85xx_CONFIG_H_ */
|
|
||||||
|
|
@ -78,9 +78,6 @@ enum law_trgt_if {
|
||||||
enum law_trgt_if {
|
enum law_trgt_if {
|
||||||
LAW_TRGT_IF_PCI = 0x00,
|
LAW_TRGT_IF_PCI = 0x00,
|
||||||
LAW_TRGT_IF_PCI_2 = 0x01,
|
LAW_TRGT_IF_PCI_2 = 0x01,
|
||||||
#ifndef CONFIG_ARCH_MPC8641
|
|
||||||
LAW_TRGT_IF_PCIE_1 = 0x02,
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
|
#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
|
||||||
LAW_TRGT_IF_OCN_DSP = 0x03,
|
LAW_TRGT_IF_OCN_DSP = 0x03,
|
||||||
#else
|
#else
|
||||||
|
|
@ -116,10 +113,6 @@ enum law_trgt_if {
|
||||||
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
|
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
|
||||||
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
|
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
|
||||||
|
|
||||||
#ifdef CONFIG_ARCH_MPC8641
|
|
||||||
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_P2020)
|
#if defined(CONFIG_ARCH_P2020)
|
||||||
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
|
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -30,7 +30,7 @@ void fsl_pci_config_unlock(struct pci_controller *hose);
|
||||||
void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
|
void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
|
* Common PCI/PCIE Register structure for mpc85xx
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -15,10 +15,6 @@
|
||||||
#if defined(CONFIG_MPC8xx)
|
#if defined(CONFIG_MPC8xx)
|
||||||
#include <asm/immap_8xx.h>
|
#include <asm/immap_8xx.h>
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_MPC86xx
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
#include <asm/immap_86xx.h>
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_MPC85xx
|
#ifdef CONFIG_MPC85xx
|
||||||
#include <mpc85xx.h>
|
#include <mpc85xx.h>
|
||||||
#include <asm/immap_85xx.h>
|
#include <asm/immap_85xx.h>
|
||||||
|
|
|
||||||
|
|
@ -1,9 +0,0 @@
|
||||||
if TARGET_SBC8641D
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "sbc8641d"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "sbc8641d"
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
@ -1,6 +0,0 @@
|
||||||
SBC8641D BOARD
|
|
||||||
M: Paul Gortmaker <paul.gortmaker@windriver.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/sbc8641d/
|
|
||||||
F: include/configs/sbc8641d.h
|
|
||||||
F: configs/sbc8641d_defconfig
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# (C) Copyright 2001
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
|
|
||||||
obj-y += sbc8641d.o
|
|
||||||
obj-y += law.o
|
|
||||||
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
|
|
||||||
|
|
@ -1,49 +0,0 @@
|
||||||
Wind River SBC8641D reference board
|
|
||||||
===========================
|
|
||||||
|
|
||||||
Created 06/14/2007 Joe Hamman
|
|
||||||
Copyright 2007, Embedded Specialties, Inc.
|
|
||||||
Copyright 2007 Wind River Systems, Inc.
|
|
||||||
-----------------------------
|
|
||||||
|
|
||||||
1. Building U-Boot
|
|
||||||
------------------
|
|
||||||
The SBC8641D code is known to build using ELDK 4.1.
|
|
||||||
|
|
||||||
$ make sbc8641d_config
|
|
||||||
Configuring for sbc8641d board...
|
|
||||||
|
|
||||||
$ make
|
|
||||||
|
|
||||||
|
|
||||||
2. Switch and Jumper Settings
|
|
||||||
-----------------------------
|
|
||||||
All Jumpers & Switches are in their default positions. Please refer to
|
|
||||||
the board documentation for details. Some settings control CPU voltages
|
|
||||||
and settings may change with board revisions.
|
|
||||||
|
|
||||||
3. Known limitations
|
|
||||||
--------------------
|
|
||||||
PCI:
|
|
||||||
The PCI command may hang if no boards are present in either slot.
|
|
||||||
|
|
||||||
4. Reflashing U-Boot
|
|
||||||
--------------------
|
|
||||||
The board has two independent flash devices which can be used for dual
|
|
||||||
booting, or for U-Boot backup and recovery. A two pin jumper on the
|
|
||||||
three pin JP10 determines which device is attached to /CS0 line.
|
|
||||||
|
|
||||||
Assuming one device has a functional U-Boot, and the other device has
|
|
||||||
a recently installed non-functional image, to perform a recovery from
|
|
||||||
that non-functional image goes essentially as follows:
|
|
||||||
|
|
||||||
a) power down the board and jumper JP10 to select the functional image.
|
|
||||||
b) power on the board and let it get to U-Boot prompt.
|
|
||||||
c) while on, using static precautions, move JP10 back to the failed image.
|
|
||||||
d) use "md fff00000" to confirm you are looking at the failed image
|
|
||||||
e) turn off write protect with "prot off all"
|
|
||||||
f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin"
|
|
||||||
g) erase failed image: "erase FFF00000 FFF5FFFF"
|
|
||||||
h) copy in new image: "cp.b 200000 FFF00000 60000"
|
|
||||||
i) ensure new image is written: "md fff00000"
|
|
||||||
k) power cycle the board and confirm new image works.
|
|
||||||
|
|
@ -1,53 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <fsl_ddr_dimm_params.h>
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
||||||
dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Factors to consider for clock adjust:
|
|
||||||
* - number of chips on bus
|
|
||||||
* - position of slot
|
|
||||||
* - DDR1 vs. DDR2?
|
|
||||||
* - ???
|
|
||||||
*
|
|
||||||
* This needs to be determined on a board-by-board basis.
|
|
||||||
* 0110 3/4 cycle late
|
|
||||||
* 0111 7/8 cycle late
|
|
||||||
*/
|
|
||||||
popts->clk_adjust = 7;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for CPO:
|
|
||||||
* - frequency
|
|
||||||
* - ddr1 vs. ddr2
|
|
||||||
*/
|
|
||||||
popts->cpo_override = 10;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for write data delay:
|
|
||||||
* - number of DIMMs
|
|
||||||
*
|
|
||||||
* 1 = 1/4 clock delay
|
|
||||||
* 2 = 1/2 clock delay
|
|
||||||
* 3 = 3/4 clock delay
|
|
||||||
* 4 = 1 clock delay
|
|
||||||
* 5 = 5/4 clock delay
|
|
||||||
* 6 = 3/2 clock delay
|
|
||||||
*/
|
|
||||||
popts->write_data_delay = 3;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable:
|
|
||||||
* - number of DIMMs installed
|
|
||||||
*/
|
|
||||||
popts->half_strength_driver_enable = 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LAW (Local Access Window) configuration:
|
|
||||||
*
|
|
||||||
* 0x0000_0000 DDR 256M
|
|
||||||
* 0x1000_0000 DDR2 256M
|
|
||||||
* 0x8000_0000 PCIE1 MEM 512M
|
|
||||||
* 0xa000_0000 PCIE2 MEM 512M
|
|
||||||
* 0xc000_0000 RapidIO 512M
|
|
||||||
* 0xe200_0000 PCIE1 IO 16M
|
|
||||||
* 0xe300_0000 PCIE2 IO 16M
|
|
||||||
* 0xf800_0000 CCSRBAR 2M
|
|
||||||
* 0xfe00_0000 FLASH (boot bank) 32M
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
struct law_entry law_table[] = {
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM)
|
|
||||||
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
|
|
||||||
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
|
||||||
LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
|
|
||||||
#endif
|
|
||||||
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
|
|
||||||
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table);
|
|
||||||
|
|
@ -1,268 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
|
|
||||||
* Copyright 2007 Embedded Specialties, Inc.
|
|
||||||
* Joe Hamman joe.hamman@embeddedspecialties.com
|
|
||||||
*
|
|
||||||
* Copyright 2004 Freescale Semiconductor.
|
|
||||||
* Jeff Brown
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*
|
|
||||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <pci.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/immap_86xx.h>
|
|
||||||
#include <asm/fsl_pci.h>
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <asm/fsl_serdes.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
long int fixed_sdram (void);
|
|
||||||
|
|
||||||
int board_early_init_f (void)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int checkboard (void)
|
|
||||||
{
|
|
||||||
puts ("Board: Wind River SBC8641D\n");
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int dram_init(void)
|
|
||||||
{
|
|
||||||
long dram_size = 0;
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
dram_size = fsl_ddr_sdram();
|
|
||||||
#else
|
|
||||||
dram_size = fixed_sdram ();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
debug(" DDR: ");
|
|
||||||
gd->ram_size = dram_size;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_DRAM_TEST)
|
|
||||||
int testdram(void)
|
|
||||||
{
|
|
||||||
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
|
|
||||||
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
|
|
||||||
uint *p;
|
|
||||||
|
|
||||||
puts ("SDRAM test phase 1:\n");
|
|
||||||
for (p = pstart; p < pend; p++)
|
|
||||||
*p = 0xaaaaaaaa;
|
|
||||||
|
|
||||||
for (p = pstart; p < pend; p++) {
|
|
||||||
if (*p != 0xaaaaaaaa) {
|
|
||||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
puts ("SDRAM test phase 2:\n");
|
|
||||||
for (p = pstart; p < pend; p++)
|
|
||||||
*p = 0x55555555;
|
|
||||||
|
|
||||||
for (p = pstart; p < pend; p++) {
|
|
||||||
if (*p != 0x55555555) {
|
|
||||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
puts ("SDRAM test passed.\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*
|
|
||||||
* Fixed sdram init -- doesn't use serial presence detect.
|
|
||||||
*/
|
|
||||||
long int fixed_sdram (void)
|
|
||||||
{
|
|
||||||
#if !defined(CONFIG_SYS_RAMBOOT)
|
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
|
|
||||||
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
|
|
||||||
ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
|
|
||||||
ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
|
|
||||||
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
|
|
||||||
ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
|
|
||||||
ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
|
|
||||||
ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
|
|
||||||
ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
|
|
||||||
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
|
|
||||||
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
|
|
||||||
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
|
|
||||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
|
|
||||||
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
|
|
||||||
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
|
|
||||||
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
|
|
||||||
ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
|
|
||||||
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
|
|
||||||
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
|
|
||||||
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
|
|
||||||
|
|
||||||
asm ("sync;isync");
|
|
||||||
|
|
||||||
udelay(500);
|
|
||||||
|
|
||||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
|
|
||||||
asm ("sync; isync");
|
|
||||||
|
|
||||||
udelay(500);
|
|
||||||
ddr = &immap->im_ddr2;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
|
|
||||||
ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
|
|
||||||
ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
|
|
||||||
ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
|
|
||||||
ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
|
|
||||||
ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
|
|
||||||
ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
|
|
||||||
ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
|
|
||||||
ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
|
|
||||||
ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
|
|
||||||
ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
|
|
||||||
ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
|
|
||||||
ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
|
|
||||||
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
|
|
||||||
ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
|
|
||||||
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
|
|
||||||
ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
|
|
||||||
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
|
|
||||||
ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
|
|
||||||
ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
|
|
||||||
|
|
||||||
asm ("sync;isync");
|
|
||||||
|
|
||||||
udelay(500);
|
|
||||||
|
|
||||||
ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
|
|
||||||
asm ("sync; isync");
|
|
||||||
|
|
||||||
udelay(500);
|
|
||||||
#endif
|
|
||||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
|
||||||
}
|
|
||||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
|
||||||
/*
|
|
||||||
* Initialize PCI Devices, report devices found.
|
|
||||||
*/
|
|
||||||
|
|
||||||
void pci_init_board(void)
|
|
||||||
{
|
|
||||||
fsl_pcie_init_board(0);
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
FT_FSL_PCI_SETUP;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void sbc8641d_reset_board (void)
|
|
||||||
{
|
|
||||||
puts ("Resetting board....\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* get_board_sys_clk
|
|
||||||
* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
|
|
||||||
*/
|
|
||||||
|
|
||||||
unsigned long get_board_sys_clk (ulong dummy)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
ulong val = 0;
|
|
||||||
|
|
||||||
i = 5;
|
|
||||||
i &= 0x07;
|
|
||||||
|
|
||||||
switch (i) {
|
|
||||||
case 0:
|
|
||||||
val = 33000000;
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
val = 40000000;
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
val = 50000000;
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
val = 66000000;
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
val = 83000000;
|
|
||||||
break;
|
|
||||||
case 5:
|
|
||||||
val = 100000000;
|
|
||||||
break;
|
|
||||||
case 6:
|
|
||||||
val = 134000000;
|
|
||||||
break;
|
|
||||||
case 7:
|
|
||||||
val = 166000000;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return val;
|
|
||||||
}
|
|
||||||
|
|
||||||
void board_reset(void)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_SYS_RESET_ADDRESS
|
|
||||||
ulong addr = CONFIG_SYS_RESET_ADDRESS;
|
|
||||||
|
|
||||||
/* flush and disable I/D cache */
|
|
||||||
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
|
|
||||||
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
|
|
||||||
__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
|
|
||||||
__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
|
|
||||||
__asm__ __volatile__ ("sync");
|
|
||||||
__asm__ __volatile__ ("mtspr 1008, 4");
|
|
||||||
__asm__ __volatile__ ("isync");
|
|
||||||
__asm__ __volatile__ ("sync");
|
|
||||||
__asm__ __volatile__ ("mtspr 1008, 5");
|
|
||||||
__asm__ __volatile__ ("isync");
|
|
||||||
__asm__ __volatile__ ("sync");
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SRR0 has system reset vector, SRR1 has default MSR value
|
|
||||||
* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
|
|
||||||
*/
|
|
||||||
__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
|
|
||||||
__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
|
|
||||||
__asm__ __volatile__ ("mtspr 27, 4");
|
|
||||||
__asm__ __volatile__ ("rfi");
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
@ -1,39 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xfff00000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_MPC86xx=y
|
|
||||||
CONFIG_HIGH_BATS=y
|
|
||||||
CONFIG_TARGET_SBC8641D=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=10
|
|
||||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
# CONFIG_AUTO_COMPLETE is not set
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_MP=y
|
|
||||||
CONFIG_DOS_PARTITION=y
|
|
||||||
CONFIG_ENV_OVERWRITE=y
|
|
||||||
CONFIG_ENV_ADDR=0xFFF60000
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_PROTECTION=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -99,7 +99,6 @@ alias ppc powerpc
|
||||||
alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@c-s.fr>
|
alias mpc8xx uboot, wd, Christophe Leroy <christophe.leroy@c-s.fr>
|
||||||
alias mpc83xx uboot, mariosix
|
alias mpc83xx uboot, mariosix
|
||||||
alias mpc85xx uboot, afleming, priyankajain
|
alias mpc85xx uboot, afleming, priyankajain
|
||||||
alias mpc86xx uboot, afleming, priyankajain
|
|
||||||
|
|
||||||
alias sandbox sjg
|
alias sandbox sjg
|
||||||
alias sb sandbox
|
alias sb sandbox
|
||||||
|
|
|
||||||
|
|
@ -2,8 +2,8 @@ config SYS_FSL_DDR
|
||||||
bool
|
bool
|
||||||
help
|
help
|
||||||
Select Freescale General DDR driver, shared between most Freescale
|
Select Freescale General DDR driver, shared between most Freescale
|
||||||
PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
|
PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
|
||||||
based Layerscape SoCs (such as ls2080a).
|
Layerscape SoCs (such as ls2080a).
|
||||||
|
|
||||||
config SYS_FSL_MMDC
|
config SYS_FSL_MMDC
|
||||||
bool
|
bool
|
||||||
|
|
@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS
|
||||||
ARCH_T4240
|
ARCH_T4240
|
||||||
default 2 if ARCH_B4860 || \
|
default 2 if ARCH_B4860 || \
|
||||||
ARCH_BSC9132 || \
|
ARCH_BSC9132 || \
|
||||||
ARCH_MPC8641 || \
|
|
||||||
ARCH_P4080 || \
|
ARCH_P4080 || \
|
||||||
ARCH_P5040 || \
|
ARCH_P5040 || \
|
||||||
ARCH_LX2160A || \
|
ARCH_LX2160A || \
|
||||||
|
|
@ -79,12 +78,6 @@ config SYS_FSL_DDRC_GEN2
|
||||||
help
|
help
|
||||||
Enable Freescale DDR2 controller.
|
Enable Freescale DDR2 controller.
|
||||||
|
|
||||||
config SYS_FSL_DDRC_86XX_GEN2
|
|
||||||
bool
|
|
||||||
depends on MPC86xx
|
|
||||||
help
|
|
||||||
Enable Freescale DDR2 controller for MPC86xx SoCs.
|
|
||||||
|
|
||||||
config SYS_FSL_DDRC_GEN3
|
config SYS_FSL_DDRC_GEN3
|
||||||
bool
|
bool
|
||||||
depends on PPC
|
depends on PPC
|
||||||
|
|
@ -136,7 +129,6 @@ config SYS_FSL_DDR2
|
||||||
bool "Freescale DDR2 controller"
|
bool "Freescale DDR2 controller"
|
||||||
depends on SYS_FSL_HAS_DDR2
|
depends on SYS_FSL_HAS_DDR2
|
||||||
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
|
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
|
||||||
select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
|
|
||||||
|
|
||||||
config SYS_FSL_DDR1
|
config SYS_FSL_DDR1
|
||||||
bool "Freescale DDR1 controller"
|
bool "Freescale DDR1 controller"
|
||||||
|
|
|
||||||
|
|
@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
|
||||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
|
obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
|
||||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
|
obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
|
||||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
|
obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
|
||||||
obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o
|
|
||||||
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
|
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
|
||||||
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
|
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
|
||||||
obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
|
obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
|
||||||
|
|
|
||||||
|
|
@ -1,84 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <linux/delay.h>
|
|
||||||
|
|
||||||
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
|
|
||||||
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|
||||||
unsigned int ctrl_num, int step)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
struct ccsr_ddr __iomem *ddr;
|
|
||||||
|
|
||||||
switch (ctrl_num) {
|
|
||||||
case 0:
|
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
||||||
if (i == 0) {
|
|
||||||
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
|
|
||||||
out_be32(&ddr->cs0_config, regs->cs[i].config);
|
|
||||||
|
|
||||||
} else if (i == 1) {
|
|
||||||
out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
|
|
||||||
out_be32(&ddr->cs1_config, regs->cs[i].config);
|
|
||||||
|
|
||||||
} else if (i == 2) {
|
|
||||||
out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
|
|
||||||
out_be32(&ddr->cs2_config, regs->cs[i].config);
|
|
||||||
|
|
||||||
} else if (i == 3) {
|
|
||||||
out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
|
|
||||||
out_be32(&ddr->cs3_config, regs->cs[i].config);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
|
|
||||||
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
|
|
||||||
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
|
|
||||||
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
|
|
||||||
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
|
|
||||||
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
|
|
||||||
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
|
|
||||||
out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
|
|
||||||
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
|
|
||||||
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
|
|
||||||
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
|
|
||||||
out_be32(&ddr->init_addr, regs->ddr_init_addr);
|
|
||||||
out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
|
|
||||||
|
|
||||||
debug("before go\n");
|
|
||||||
|
|
||||||
/*
|
|
||||||
* 200 painful micro-seconds must elapse between
|
|
||||||
* the DDR clock setup and the DDR config enable.
|
|
||||||
*/
|
|
||||||
udelay(200);
|
|
||||||
asm volatile("sync;isync");
|
|
||||||
|
|
||||||
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
|
|
||||||
*/
|
|
||||||
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
|
|
||||||
udelay(10000); /* throttle polling rate */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
2
env/Kconfig
vendored
2
env/Kconfig
vendored
|
|
@ -85,7 +85,7 @@ config ENV_IS_IN_FLASH
|
||||||
default y if M548x || M547x || M5282
|
default y if M548x || M547x || M5282
|
||||||
default y if MCF532x || MCF52x2
|
default y if MCF532x || MCF52x2
|
||||||
default y if MPC86xx || MPC83xx
|
default y if MPC86xx || MPC83xx
|
||||||
default y if ARCH_MPC8548 || ARCH_MPC8641
|
default y if ARCH_MPC8548
|
||||||
default y if SH && !CPU_SH4
|
default y if SH && !CPU_SH4
|
||||||
help
|
help
|
||||||
Define this if you have a flash device which you want to use for the
|
Define this if you have a flash device which you want to use for the
|
||||||
|
|
|
||||||
|
|
@ -1,509 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2007 Wind River Systems <www.windriver.com>
|
|
||||||
* Copyright 2007 Embedded Specialties, Inc.
|
|
||||||
* Joe Hamman <joe.hamman@embeddedspecialties.com>
|
|
||||||
*
|
|
||||||
* Copyright 2006 Freescale Semiconductor.
|
|
||||||
*
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SBC8641D board configuration file
|
|
||||||
*
|
|
||||||
* Make sure you change the MAC address and other network params first,
|
|
||||||
* search for CONFIG_SERVERIP, etc in this file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/* High Level Configuration Options */
|
|
||||||
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
|
|
||||||
|
|
||||||
#ifdef RUN_DIAG
|
|
||||||
#define CONFIG_SYS_DIAG_ADDR 0xff800000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
|
|
||||||
|
|
||||||
/*
|
|
||||||
* virtual address to be used for temporary mappings. There
|
|
||||||
* should be 128k free at this VA.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SCRATCH_VA 0xe8000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SRIO
|
|
||||||
#define CONFIG_SRIO1 /* SRIO port 1 */
|
|
||||||
|
|
||||||
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
|
|
||||||
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
|
|
||||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
|
||||||
|
|
||||||
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
|
|
||||||
|
|
||||||
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/
|
|
||||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
|
||||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
|
||||||
#define CACHE_LINE_INTERLEAVING 0x20000000
|
|
||||||
#define PAGE_INTERLEAVING 0x21000000
|
|
||||||
#define BANK_INTERLEAVING 0x22000000
|
|
||||||
#define SUPER_BANK_INTERLEAVING 0x23000000
|
|
||||||
|
|
||||||
#define CONFIG_ALTIVEC 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* L2CR setup -- make sure this is right for your board!
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_L2
|
|
||||||
#define L2_INIT 0
|
|
||||||
#define L2_ENABLE (L2CR_L2E)
|
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_CLK_FREQ
|
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Base addresses -- Note these are effective addresses where the
|
|
||||||
* actual resources get mapped (not physical addresses)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
|
|
||||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR Setup
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
|
|
||||||
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
|
|
||||||
#define CONFIG_VERY_BIG_RAM
|
|
||||||
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*
|
|
||||||
* Determine DDR configuration from I2C interface.
|
|
||||||
*/
|
|
||||||
#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
|
|
||||||
#define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */
|
|
||||||
#define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */
|
|
||||||
#define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */
|
|
||||||
|
|
||||||
#else
|
|
||||||
/*
|
|
||||||
* Manually set up DDR1 & DDR2 parameters
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
|
|
||||||
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
|
|
||||||
#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_0 0x00220802
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_1 0x38377322
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_2 0x002040c7
|
|
||||||
#define CONFIG_SYS_DDR_CFG_1A 0x43008008
|
|
||||||
#define CONFIG_SYS_DDR_CFG_2 0x24401000
|
|
||||||
#define CONFIG_SYS_DDR_MODE_1 0x23c00542
|
|
||||||
#define CONFIG_SYS_DDR_MODE_2 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_MODE_CTL 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_INTERVAL 0x05080100
|
|
||||||
#define CONFIG_SYS_DDR_DATA_INIT 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
|
|
||||||
#define CONFIG_SYS_DDR_CFG_1B 0xC3008008
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
|
|
||||||
#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
|
|
||||||
#define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_TIMING_0 0x00220802
|
|
||||||
#define CONFIG_SYS_DDR2_TIMING_1 0x38377322
|
|
||||||
#define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
|
|
||||||
#define CONFIG_SYS_DDR2_CFG_1A 0x43008008
|
|
||||||
#define CONFIG_SYS_DDR2_CFG_2 0x24401000
|
|
||||||
#define CONFIG_SYS_DDR2_MODE_1 0x23c00542
|
|
||||||
#define CONFIG_SYS_DDR2_MODE_2 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_INTERVAL 0x05080100
|
|
||||||
#define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
|
|
||||||
#define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
|
|
||||||
#define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* #define CONFIG_ID_EEPROM 1
|
|
||||||
#define ID_EEPROM_ADDR 0x57 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The SBC8641D contains 16MB flash space at ff000000.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
|
|
||||||
|
|
||||||
/* Flash */
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */
|
|
||||||
|
|
||||||
/* 64KB EEPROM */
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */
|
|
||||||
|
|
||||||
/* EPLD - User switches, board id, LEDs */
|
|
||||||
#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */
|
|
||||||
#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */
|
|
||||||
|
|
||||||
/* Local bus SDRAM 128MB */
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */
|
|
||||||
#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */
|
|
||||||
#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */
|
|
||||||
|
|
||||||
/* Disk on Chip (DOC) 128MB */
|
|
||||||
#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */
|
|
||||||
#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */
|
|
||||||
|
|
||||||
/* LCD */
|
|
||||||
#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */
|
|
||||||
#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
|
|
||||||
|
|
||||||
/* Control logic & misc peripherals */
|
|
||||||
#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */
|
|
||||||
#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */
|
|
||||||
|
|
||||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_WRITE_SWAPPED_DATA
|
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#ifndef CONFIG_SYS_INIT_RAM_LOCK
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
|
||||||
|
|
||||||
/* Serial Port */
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_FSL
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
|
|
||||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RapidIO MMU
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */
|
|
||||||
#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
|
|
||||||
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Addresses are mapped 1-1.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
|
||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
||||||
|
|
||||||
|
|
||||||
#if !defined(CONFIG_PCI_PNP)
|
|
||||||
#define PCI_ENET0_IOADDR 0xe0000000
|
|
||||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
|
||||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SCSI_AHCI
|
|
||||||
#define CONFIG_SATA_ULI5288
|
|
||||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
|
|
||||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
|
||||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
||||||
#define CONFIG_TSEC3 1
|
|
||||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
|
||||||
#define CONFIG_TSEC4 1
|
|
||||||
#define CONFIG_TSEC4_NAME "eTSEC4"
|
|
||||||
|
|
||||||
#define TSEC1_PHY_ADDR 0x1F
|
|
||||||
#define TSEC2_PHY_ADDR 0x00
|
|
||||||
#define TSEC3_PHY_ADDR 0x01
|
|
||||||
#define TSEC4_PHY_ADDR 0x02
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define TSEC3_PHYIDX 0
|
|
||||||
#define TSEC4_PHYIDX 0
|
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC3_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC4_FLAGS TSEC_GIGABIT
|
|
||||||
|
|
||||||
#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
|
|
||||||
|
|
||||||
#define CONFIG_ETHPRIME "eTSEC1"
|
|
||||||
|
|
||||||
#endif /* CONFIG_TSEC_ENET */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT0 2G Cacheable, non-guarded
|
|
||||||
* 0x0000_0000 2G DDR
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
|
|
||||||
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT1 1G Cache-inhibited, guarded
|
|
||||||
* 0x8000_0000 512M PCI-Express 1 Memory
|
|
||||||
* 0xa000_0000 512M PCI-Express 2 Memory
|
|
||||||
* Changed it for operating from 0xd0000000
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
|
|
||||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT2 512M Cache-inhibited, guarded
|
|
||||||
* 0xc000_0000 512M RapidIO Memory
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
|
|
||||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT3 4M Cache-inhibited, guarded
|
|
||||||
* 0xf800_0000 4M CCSR
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
|
|
||||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
|
|
||||||
| BATL_PP_RW | BATL_CACHEINHIBIT \
|
|
||||||
| BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
|
|
||||||
| BATU_BL_1M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
|
|
||||||
| BATL_PP_RW | BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT4 32M Cache-inhibited, guarded
|
|
||||||
* 0xe200_0000 16M PCI-Express 1 I/O
|
|
||||||
* 0xe300_0000 16M PCI-Express 2 I/0
|
|
||||||
* Note that this is at 0xe0000000
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
|
|
||||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT5 128K Cacheable, non-guarded
|
|
||||||
* 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
|
|
||||||
#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT6 32M Cache-inhibited, guarded
|
|
||||||
* 0xfe00_0000 32M FLASH
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
|
|
||||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
|
|
||||||
|
|
||||||
/* Map the last 1M of flash where we're running from reset */
|
|
||||||
#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
|
|
||||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
|
|
||||||
| BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DBAT7L 0x00000000
|
|
||||||
#define CONFIG_SYS_DBAT7U 0x00000000
|
|
||||||
#define CONFIG_SYS_IBAT7L 0x00000000
|
|
||||||
#define CONFIG_SYS_IBAT7U 0x00000000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 8 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
|
||||||
|
|
||||||
/* Cache Configuration */
|
|
||||||
#define CONFIG_SYS_DCACHE_SIZE 32768
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_HAS_ETH0 1
|
|
||||||
#define CONFIG_HAS_ETH1 1
|
|
||||||
#define CONFIG_HAS_ETH2 1
|
|
||||||
#define CONFIG_HAS_ETH3 1
|
|
||||||
|
|
||||||
#define CONFIG_IPADDR 192.168.0.50
|
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME "sbc8641d"
|
|
||||||
#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
|
|
||||||
#define CONFIG_BOOTFILE "uImage"
|
|
||||||
|
|
||||||
#define CONFIG_SERVERIP 192.168.0.2
|
|
||||||
#define CONFIG_GATEWAYIP 192.168.0.1
|
|
||||||
#define CONFIG_NETMASK 255.255.255.0
|
|
||||||
|
|
||||||
/* default location for tftp and bootm */
|
|
||||||
#define CONFIG_LOADADDR 1000000
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"consoledev=ttyS0\0" \
|
|
||||||
"ramdiskaddr=2000000\0" \
|
|
||||||
"ramdiskfile=uRamdisk\0" \
|
|
||||||
"dtbaddr=400000\0" \
|
|
||||||
"dtbfile=sbc8641d.dtb\0" \
|
|
||||||
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
|
|
||||||
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
|
|
||||||
"maxcpus=1"
|
|
||||||
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$serverip:$rootpath " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $dtbaddr $dtbfile;" \
|
|
||||||
"bootm $loadaddr - $dtbaddr"
|
|
||||||
|
|
||||||
#define CONFIG_RAMBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $dtbaddr $dtbfile;" \
|
|
||||||
"bootm $loadaddr $ramdiskaddr $dtbaddr"
|
|
||||||
|
|
||||||
#define CONFIG_FLASHBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs;" \
|
|
||||||
"bootm ffd00000 ffb00000 ffa00000"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
|
|
@ -29,11 +29,6 @@
|
||||||
#include <asm/immap_85xx.h>
|
#include <asm/immap_85xx.h>
|
||||||
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
|
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
|
||||||
offsetof(ccsr_pic_t, tfrr))
|
offsetof(ccsr_pic_t, tfrr))
|
||||||
|
|
||||||
#elif defined (CONFIG_MPC86xx)
|
|
||||||
#include <asm/immap_86xx.h>
|
|
||||||
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
|
|
||||||
offsetof(ccsr_pic_t, tfrr))
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef _POST_WORD_ADDR
|
#ifndef _POST_WORD_ADDR
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue