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board: mediatek: add MT8365 EVK board support
This adds support for the MT8365 EVK board with the following features enabled/tested: Boot, UART, Watchdog and MMC. Signed-off-by: Julien Masson <jmasson@baylibre.com>
This commit is contained in:
Julien Masson
Tom Rini
parent
5679eccb83
commit
1c2c0c6359
6 changed files with 761 additions and 0 deletions
282
arch/arm/dts/mt6357.dtsi
Normal file
282
arch/arm/dts/mt6357.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Copyright (c) 2023 BayLibre Inc.
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*/
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#include <dt-bindings/input/input.h>
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&pwrap {
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mt6357_pmic: pmic {
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compatible = "mediatek,mt6357";
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regulators {
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mt6357_vproc_reg: buck-vproc {
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regulator-name = "vproc";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vcore_reg: buck-vcore {
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regulator-name = "vcore";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vmodem_reg: buck-vmodem {
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regulator-name = "vmodem";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1193750>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <220>;
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};
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mt6357_vs1_reg: buck-vs1 {
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regulator-name = "vs1";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <2200000>;
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regulator-ramp-delay = <12500>;
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regulator-enable-ramp-delay = <220>;
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regulator-always-on;
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};
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mt6357_vpa_reg: buck-vpa {
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regulator-name = "vpa";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <3650000>;
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regulator-ramp-delay = <50000>;
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regulator-enable-ramp-delay = <220>;
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};
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mt6357_vfe28_reg: ldo-vfe28 {
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compatible = "regulator-fixed";
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regulator-name = "vfe28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vxo22_reg: ldo-vxo22 {
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regulator-name = "vxo22";
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regulator-min-microvolt = <2200000>;
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regulator-max-microvolt = <2400000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vrf18_reg: ldo-vrf18 {
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compatible = "regulator-fixed";
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regulator-name = "vrf18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vrf12_reg: ldo-vrf12 {
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compatible = "regulator-fixed";
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regulator-name = "vrf12";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <110>;
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};
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mt6357_vefuse_reg: ldo-vefuse {
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regulator-name = "vefuse";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn33_bt_reg: ldo-vcn33-bt {
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regulator-name = "vcn33-bt";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3500000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn33_wifi_reg: ldo-vcn33-wifi {
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regulator-name = "vcn33-wifi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3500000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn28_reg: ldo-vcn28 {
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compatible = "regulator-fixed";
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regulator-name = "vcn28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcn18_reg: ldo-vcn18 {
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compatible = "regulator-fixed";
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regulator-name = "vcn18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcama_reg: ldo-vcama {
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regulator-name = "vcama";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcamd_reg: ldo-vcamd {
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regulator-name = "vcamd";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vcamio_reg: ldo-vcamio18 {
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compatible = "regulator-fixed";
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regulator-name = "vcamio";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vldo28_reg: ldo-vldo28 {
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regulator-name = "vldo28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <3000000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vsram_others_reg: ldo-vsram-others {
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regulator-name = "vsram-others";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <110>;
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regulator-always-on;
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};
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mt6357_vsram_proc_reg: ldo-vsram-proc {
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regulator-name = "vsram-proc";
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regulator-min-microvolt = <518750>;
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regulator-max-microvolt = <1312500>;
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regulator-ramp-delay = <6250>;
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regulator-enable-ramp-delay = <110>;
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regulator-always-on;
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};
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mt6357_vaux18_reg: ldo-vaux18 {
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compatible = "regulator-fixed";
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regulator-name = "vaux18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vaud28_reg: ldo-vaud28 {
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compatible = "regulator-fixed";
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regulator-name = "vaud28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vio28_reg: ldo-vio28 {
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compatible = "regulator-fixed";
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regulator-name = "vio28";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vio18_reg: ldo-vio18 {
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compatible = "regulator-fixed";
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regulator-name = "vio18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <264>;
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regulator-always-on;
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};
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mt6357_vdram_reg: ldo-vdram {
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regulator-name = "vdram";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1200000>;
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regulator-enable-ramp-delay = <3300>;
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};
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mt6357_vmc_reg: ldo-vmc {
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regulator-name = "vmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vmch_reg: ldo-vmch {
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regulator-name = "vmch";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vemc_reg: ldo-vemc {
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regulator-name = "vemc";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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regulator-always-on;
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};
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mt6357_vsim1_reg: ldo-vsim1 {
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regulator-name = "vsim1";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vsim2_reg: ldo-vsim2 {
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regulator-name = "vsim2";
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regulator-min-microvolt = <1700000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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mt6357_vibr_reg: ldo-vibr {
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regulator-name = "vibr";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <3300000>;
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regulator-enable-ramp-delay = <44>;
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};
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mt6357_vusb33_reg: ldo-vusb33 {
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regulator-name = "vusb33";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3100000>;
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regulator-enable-ramp-delay = <264>;
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};
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};
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rtc {
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compatible = "mediatek,mt6357-rtc";
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};
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keys {
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compatible = "mediatek,mt6357-keys";
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key-power {
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linux,keycodes = <KEY_POWER>;
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wakeup-source;
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};
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key-home {
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linux,keycodes = <KEY_HOME>;
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wakeup-source;
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};
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};
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};
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};
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418
arch/arm/dts/mt8365-evk.dts
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418
arch/arm/dts/mt8365-evk.dts
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@ -0,0 +1,418 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021-2022 BayLibre, SAS.
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* Authors:
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* Fabien Parent <fparent@baylibre.com>
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* Bernhard Rosenkränzer <bero@baylibre.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
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#include "mt8365.dtsi"
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#include "mt6357.dtsi"
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/ {
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model = "MediaTek MT8365 Open Platform EVK";
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compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&gpio_keys>;
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key-volume-up {
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gpios = <&pio 24 GPIO_ACTIVE_LOW>;
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label = "volume_up";
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linux,code = <KEY_VOLUMEUP>;
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wakeup-source;
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debounce-interval = <15>;
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0xc0000000>;
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};
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usb_otg_vbus: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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bl31_secmon_reserved: secmon@43000000 {
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no-map;
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reg = <0 0x43000000 0 0x30000>;
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};
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/* 12 MiB reserved for OP-TEE (BL32)
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* +-----------------------+ 0x43e0_0000
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* | SHMEM 2MiB |
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* +-----------------------+ 0x43c0_0000
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* | | TA_RAM 8MiB |
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* + TZDRAM +--------------+ 0x4340_0000
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* | | TEE_RAM 2MiB |
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* +-----------------------+ 0x4320_0000
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*/
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optee_reserved: optee@43200000 {
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no-map;
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reg = <0 0x43200000 0 0x00c00000>;
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};
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};
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};
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&cpu0 {
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proc-supply = <&mt6357_vproc_reg>;
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sram-supply = <&mt6357_vsram_proc_reg>;
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};
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&cpu1 {
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proc-supply = <&mt6357_vproc_reg>;
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sram-supply = <&mt6357_vsram_proc_reg>;
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};
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&cpu2 {
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proc-supply = <&mt6357_vproc_reg>;
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sram-supply = <&mt6357_vsram_proc_reg>;
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};
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&cpu3 {
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proc-supply = <&mt6357_vproc_reg>;
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sram-supply = <&mt6357_vsram_proc_reg>;
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};
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ðernet {
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pinctrl-0 = <ðernet_pins>;
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pinctrl-names = "default";
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phy-handle = <ð_phy>;
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phy-mode = "rmii";
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/*
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* Ethernet and HDMI (DSI0) are sharing pins.
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* Only one can be enabled at a time and require the physical switch
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* SW2101 to be set on LAN position
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* mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
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*/
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status = "disabled";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&mmc0 {
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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hs400-ds-delay = <0x12012>;
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max-frequency = <200000000>;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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pinctrl-0 = <&mmc0_default_pins>;
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pinctrl-1 = <&mmc0_uhs_pins>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&mt6357_vemc_reg>;
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vqmmc-supply = <&mt6357_vio18_reg>;
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status = "okay";
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};
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&mmc1 {
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bus-width = <4>;
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cap-sd-highspeed;
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cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
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max-frequency = <200000000>;
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pinctrl-0 = <&mmc1_default_pins>;
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pinctrl-1 = <&mmc1_uhs_pins>;
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pinctrl-names = "default", "state_uhs";
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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vmmc-supply = <&mt6357_vmch_reg>;
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vqmmc-supply = <&mt6357_vmc_reg>;
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status = "okay";
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};
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&mt6357_pmic {
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interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
|
||||
|
||||
&pio {
|
||||
ethernet_pins: ethernet-pins {
|
||||
phy_reset_pins {
|
||||
pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
|
||||
};
|
||||
|
||||
rmii_pins {
|
||||
pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
|
||||
<MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
|
||||
<MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
|
||||
<MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
|
||||
<MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
|
||||
<MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
|
||||
<MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
|
||||
<MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
|
||||
<MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
|
||||
<MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
|
||||
<MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
|
||||
<MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
|
||||
<MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
|
||||
<MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
|
||||
<MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
|
||||
<MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
|
||||
<MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_default_pins: mmc0-default-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_uhs_pins: mmc0-uhs-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
|
||||
<MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
|
||||
<MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
|
||||
<MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
|
||||
<MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
|
||||
<MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
|
||||
<MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
|
||||
<MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
|
||||
<MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
ds-pins {
|
||||
pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
rst-pins {
|
||||
pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
|
||||
drive-strength = <MTK_DRIVE_10mA>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_default_pins: mmc1-default-pins {
|
||||
cd-pins {
|
||||
pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_uhs_pins: mmc1-uhs-pins {
|
||||
clk-pins {
|
||||
pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
cmd-dat-pins {
|
||||
pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
|
||||
<MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
|
||||
<MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
|
||||
<MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
|
||||
<MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
|
||||
<MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
|
||||
<MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
|
||||
<MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_pins: usb-pins {
|
||||
id-pins {
|
||||
pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
usb0-vbus-pins {
|
||||
pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
usb1-vbus-pins {
|
||||
pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins: pwm-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
|
||||
<MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
pinctrl-0 = <&usb_pins>;
|
||||
pinctrl-names = "default";
|
||||
usb-role-switch;
|
||||
vusb33-supply = <&mt6357_vusb33_reg>;
|
||||
status = "okay";
|
||||
|
||||
connector {
|
||||
compatible = "gpio-usb-b-connector", "usb-b-connector";
|
||||
id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
|
||||
type = "micro";
|
||||
vbus-supply = <&usb_otg_vbus>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
vusb33-supply = <&mt6357_vusb33_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
6
board/mediatek/mt8365_evk/MAINTAINERS
Normal file
6
board/mediatek/mt8365_evk/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
MT8365 EVK
|
||||
M: Julien Masson <jmasson@baylibre.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/mt8365-evk.dts
|
||||
F: board/mediatek/mt8365_evk/
|
||||
F: configs/mt8365_evk_defconfig
|
||||
3
board/mediatek/mt8365_evk/Makefile
Normal file
3
board/mediatek/mt8365_evk/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y += mt8365_evk.o
|
||||
33
board/mediatek/mt8365_evk/mt8365_evk.c
Normal file
33
board/mediatek/mt8365_evk/mt8365_evk.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2023 BayLibre SAS
|
||||
* Author: Julien Masson <jmasson@baylibre.com>
|
||||
*/
|
||||
|
||||
#include <asm/armv8/mmu.h>
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mm_region mt8365_evk_mem_map[] = {
|
||||
{
|
||||
/* DDR */
|
||||
.virt = 0x40000000UL,
|
||||
.phys = 0x40000000UL,
|
||||
.size = 0xc0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
|
||||
}, {
|
||||
.virt = 0x00000000UL,
|
||||
.phys = 0x00000000UL,
|
||||
.size = 0x20000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = mt8365_evk_mem_map;
|
||||
19
configs/mt8365_evk_defconfig
Normal file
19
configs/mt8365_evk_defconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_BOARD="mt8365_evk"
|
||||
CONFIG_COUNTER_FREQUENCY=13000000
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_TEXT_BASE=0x4c000000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt8365-evk"
|
||||
CONFIG_TARGET_MT8365=y
|
||||
CONFIG_IDENT_STRING=" mt8365-evk"
|
||||
CONFIG_SYS_LOAD_ADDR=0x4c000000
|
||||
CONFIG_DEFAULT_FDT_FILE="mt8365-evk"
|
||||
CONFIG_CLK=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_BAUDRATE=921600
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_WDT_MTK=y
|
||||
Loading…
Add table
Reference in a new issue