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https://github.com/u-boot/u-boot.git
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acpi: x86: Move SPCR and DBG2 into common code
This moves the SPCR and DBG2 table generation into common code, so that they can be used by architectures other than x86. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Maximilian Brune
Tom Rini
parent
0d28900dd1
commit
1c03efc014
4 changed files with 195 additions and 185 deletions
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@ -45,17 +45,6 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
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*/
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int acpi_write_hpet(struct acpi_ctx *ctx);
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/**
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* acpi_write_dbg2_pci_uart() - Write out a DBG2 table
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*
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* @ctx: Current ACPI context
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* @dev: Debug UART device to describe
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* @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
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* Return: 0 if OK, -ve on error
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*/
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int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
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uint access_size);
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/**
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* acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table
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*
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@ -279,140 +279,6 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx,
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}
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ACPI_WRITER(5tpm2, "TPM2", acpi_write_tpm2, 0);
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int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
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{
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struct serial_device_info serial_info = {0};
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ulong serial_address, serial_offset;
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struct acpi_table_header *header;
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struct acpi_spcr *spcr;
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struct udevice *dev;
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uint serial_config;
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uint serial_width;
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int access_size;
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int space_id;
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int ret = -ENODEV;
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spcr = ctx->current;
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header = &spcr->header;
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memset(spcr, '\0', sizeof(struct acpi_spcr));
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/* Fill out header fields */
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acpi_fill_header(header, "SPCR");
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header->length = sizeof(struct acpi_spcr);
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header->revision = 2;
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/* Read the device once, here. It is reused below */
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dev = gd->cur_serial_dev;
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if (dev)
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ret = serial_getinfo(dev, &serial_info);
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if (ret)
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serial_info.type = SERIAL_CHIP_UNKNOWN;
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/* Encode chip type */
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switch (serial_info.type) {
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case SERIAL_CHIP_16550_COMPATIBLE:
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spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
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break;
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case SERIAL_CHIP_UNKNOWN:
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default:
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spcr->interface_type = ACPI_DBG2_UNKNOWN;
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break;
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}
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/* Encode address space */
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switch (serial_info.addr_space) {
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case SERIAL_ADDRESS_SPACE_MEMORY:
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space_id = ACPI_ADDRESS_SPACE_MEMORY;
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break;
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case SERIAL_ADDRESS_SPACE_IO:
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default:
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space_id = ACPI_ADDRESS_SPACE_IO;
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break;
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}
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serial_width = serial_info.reg_width * 8;
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serial_offset = serial_info.reg_offset << serial_info.reg_shift;
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serial_address = serial_info.addr + serial_offset;
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/* Encode register access size */
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switch (serial_info.reg_shift) {
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case 0:
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access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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break;
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case 1:
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access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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break;
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case 2:
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access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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break;
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case 3:
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access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
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break;
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default:
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access_size = ACPI_ACCESS_SIZE_UNDEFINED;
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break;
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}
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debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
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/* Fill GAS */
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spcr->serial_port.space_id = space_id;
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spcr->serial_port.bit_width = serial_width;
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spcr->serial_port.bit_offset = 0;
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spcr->serial_port.access_size = access_size;
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spcr->serial_port.addrl = lower_32_bits(serial_address);
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spcr->serial_port.addrh = upper_32_bits(serial_address);
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/* Encode baud rate */
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switch (serial_info.baudrate) {
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case 9600:
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spcr->baud_rate = 3;
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break;
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case 19200:
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spcr->baud_rate = 4;
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break;
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case 57600:
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spcr->baud_rate = 6;
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break;
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case 115200:
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spcr->baud_rate = 7;
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break;
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default:
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spcr->baud_rate = 0;
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break;
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}
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serial_config = SERIAL_DEFAULT_CONFIG;
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if (dev)
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ret = serial_getconfig(dev, &serial_config);
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spcr->parity = SERIAL_GET_PARITY(serial_config);
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spcr->stop_bits = SERIAL_GET_STOP(serial_config);
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/* No PCI devices for now */
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spcr->pci_device_id = 0xffff;
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spcr->pci_vendor_id = 0xffff;
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/*
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* SPCR has no clue if the UART base clock speed is different
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* to the default one. However, the SPCR 1.04 defines baud rate
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* 0 as a preconfigured state of UART and OS is supposed not
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* to touch the configuration of the serial device.
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*/
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if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
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spcr->baud_rate = 0;
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/* Fix checksum */
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header->checksum = table_compute_checksum((void *)spcr, header->length);
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acpi_add_table(ctx, spcr);
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acpi_inc(ctx, spcr->header.length);
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return 0;
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}
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ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
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int acpi_write_gnvs(struct acpi_ctx *ctx, const struct acpi_writer *entry)
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{
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ulong addr;
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@ -515,46 +381,6 @@ int acpi_write_hpet(struct acpi_ctx *ctx)
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return 0;
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}
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int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
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uint access_size)
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{
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struct acpi_dbg2_header *dbg2 = ctx->current;
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char path[ACPI_PATH_MAX];
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struct acpi_gen_regaddr address;
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phys_addr_t addr;
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int ret;
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if (!device_active(dev)) {
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log_info("Device not enabled\n");
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return -EACCES;
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}
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/*
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* PCI devices don't remember their resource allocation information in
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* U-Boot at present. We assume that MMIO is used for the UART and that
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* the address space is 32 bytes: ns16550 uses 8 registers of up to
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* 32-bits each. This is only for debugging so it is not a big deal.
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*/
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addr = dm_pci_read_bar32(dev, 0);
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log_debug("UART addr %lx\n", (ulong)addr);
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memset(&address, '\0', sizeof(address));
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address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
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address.addrl = (uint32_t)addr;
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address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
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address.access_size = access_size;
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ret = acpi_device_path(dev, path, sizeof(path));
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if (ret)
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return log_msg_ret("path", ret);
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acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
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ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
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acpi_inc_align(ctx, dbg2->header.length);
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acpi_add_table(ctx, dbg2);
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return 0;
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}
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void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
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void *dsdt)
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{
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@ -913,6 +913,17 @@ static inline int acpi_add_fadt(struct acpi_ctx *ctx, struct acpi_fadt *fadt)
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return 0;
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}
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/**
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* acpi_write_dbg2_pci_uart() - Write out a DBG2 table
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*
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* @ctx: Current ACPI context
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* @dev: Debug UART device to describe
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* @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS)
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* Return: 0 if OK, -ve on error
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*/
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int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
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uint access_size);
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/**
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* acpi_write_rsdp() - Write out an RSDP indicating where the ACPI tables are
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*
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@ -10,8 +10,10 @@
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#include <log.h>
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#include <mapmem.h>
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#include <tables_csum.h>
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#include <serial.h>
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#include <version_string.h>
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#include <acpi/acpi_table.h>
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#include <acpi/acpi_device.h>
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#include <asm/global_data.h>
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#include <dm/acpi.h>
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@ -262,3 +264,185 @@ void acpi_create_dbg2(struct acpi_dbg2_header *dbg2,
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header->length = current - (uintptr_t)dbg2;
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header->checksum = table_compute_checksum(dbg2, header->length);
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}
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int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
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uint access_size)
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{
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struct acpi_dbg2_header *dbg2 = ctx->current;
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char path[ACPI_PATH_MAX];
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struct acpi_gen_regaddr address;
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u64 addr;
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int ret;
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if (!device_active(dev)) {
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log_info("Device not enabled\n");
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return -EACCES;
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}
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/*
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* PCI devices don't remember their resource allocation information in
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* U-Boot at present. We assume that MMIO is used for the UART and that
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* the address space is 32 bytes: ns16550 uses 8 registers of up to
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* 32-bits each. This is only for debugging so it is not a big deal.
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*/
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addr = dm_pci_read_bar32(dev, 0);
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log_debug("UART addr %lx\n", (ulong)addr);
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ret = acpi_device_path(dev, path, sizeof(path));
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if (ret)
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return log_msg_ret("path", ret);
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memset(&address, '\0', sizeof(address));
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address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
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address.addrl = (uint32_t)addr;
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address.addrh = (uint32_t)((addr >> 32) & 0xffffffff);
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address.access_size = access_size;
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ret = acpi_device_path(dev, path, sizeof(path));
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if (ret)
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return log_msg_ret("path", ret);
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acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT,
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ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path);
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acpi_inc_align(ctx, dbg2->header.length);
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acpi_add_table(ctx, dbg2);
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return 0;
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}
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static int acpi_write_spcr(struct acpi_ctx *ctx, const struct acpi_writer *entry)
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{
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struct serial_device_info serial_info = {0};
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ulong serial_address, serial_offset;
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struct acpi_table_header *header;
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struct acpi_spcr *spcr;
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struct udevice *dev;
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uint serial_config;
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uint serial_width;
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int access_size;
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int space_id;
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int ret = -ENODEV;
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spcr = ctx->current;
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header = &spcr->header;
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memset(spcr, '\0', sizeof(struct acpi_spcr));
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/* Fill out header fields */
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acpi_fill_header(header, "SPCR");
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header->length = sizeof(struct acpi_spcr);
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header->revision = 2;
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/* Read the device once, here. It is reused below */
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dev = gd->cur_serial_dev;
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if (dev)
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ret = serial_getinfo(dev, &serial_info);
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if (ret)
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serial_info.type = SERIAL_CHIP_UNKNOWN;
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/* Encode chip type */
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switch (serial_info.type) {
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case SERIAL_CHIP_16550_COMPATIBLE:
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spcr->interface_type = ACPI_DBG2_16550_COMPATIBLE;
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break;
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case SERIAL_CHIP_PL01X:
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spcr->interface_type = ACPI_DBG2_ARM_PL011;
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break;
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case SERIAL_CHIP_UNKNOWN:
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default:
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spcr->interface_type = ACPI_DBG2_UNKNOWN;
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break;
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}
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/* Encode address space */
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switch (serial_info.addr_space) {
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case SERIAL_ADDRESS_SPACE_MEMORY:
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space_id = ACPI_ADDRESS_SPACE_MEMORY;
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break;
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case SERIAL_ADDRESS_SPACE_IO:
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default:
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space_id = ACPI_ADDRESS_SPACE_IO;
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break;
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}
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serial_width = serial_info.reg_width * 8;
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serial_offset = serial_info.reg_offset << serial_info.reg_shift;
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serial_address = serial_info.addr + serial_offset;
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/* Encode register access size */
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switch (serial_info.reg_shift) {
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case 0:
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access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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break;
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case 1:
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access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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break;
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case 2:
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access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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break;
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case 3:
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access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS;
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break;
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default:
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access_size = ACPI_ACCESS_SIZE_UNDEFINED;
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break;
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}
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debug("UART type %u @ %lx\n", spcr->interface_type, serial_address);
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/* Fill GAS */
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spcr->serial_port.space_id = space_id;
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spcr->serial_port.bit_width = serial_width;
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spcr->serial_port.bit_offset = 0;
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spcr->serial_port.access_size = access_size;
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spcr->serial_port.addrl = lower_32_bits(serial_address);
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spcr->serial_port.addrh = upper_32_bits(serial_address);
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/* Encode baud rate */
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switch (serial_info.baudrate) {
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case 9600:
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spcr->baud_rate = 3;
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break;
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case 19200:
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spcr->baud_rate = 4;
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break;
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case 57600:
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spcr->baud_rate = 6;
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break;
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case 115200:
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spcr->baud_rate = 7;
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break;
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default:
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spcr->baud_rate = 0;
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break;
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}
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serial_config = SERIAL_DEFAULT_CONFIG;
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if (dev)
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ret = serial_getconfig(dev, &serial_config);
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spcr->parity = SERIAL_GET_PARITY(serial_config);
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spcr->stop_bits = SERIAL_GET_STOP(serial_config);
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/* No PCI devices for now */
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spcr->pci_device_id = 0xffff;
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spcr->pci_vendor_id = 0xffff;
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/*
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* SPCR has no clue if the UART base clock speed is different
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* to the default one. However, the SPCR 1.04 defines baud rate
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* 0 as a preconfigured state of UART and OS is supposed not
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* to touch the configuration of the serial device.
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*/
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if (serial_info.clock != SERIAL_DEFAULT_CLOCK)
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spcr->baud_rate = 0;
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/* Fix checksum */
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header->checksum = table_compute_checksum((void *)spcr, header->length);
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acpi_add_table(ctx, spcr);
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acpi_inc(ctx, spcr->header.length);
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return 0;
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}
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ACPI_WRITER(5spcr, "SPCR", acpi_write_spcr, 0);
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