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imx9: Add 233Mhz DDR PLL frequency

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To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li 2024-09-19 12:01:29 +08:00 • committed by Fabio Estevam
parent ab7566d78b
commit 1b631589d4
2 changed files with 5 additions and 0 deletions
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1
arch/arm/mach-imx/imx9/clock.c
View file

@ -41,6 +41,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
}; };
/* return in khz */ /* return in khz */

4
drivers/ddr/imx/phy/ddrphy_utils.c
View file

@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(266)); dram_pll_init(MHZ(266));
dram_disable_bypass(); dram_disable_bypass();
break; break;
case 933:
dram_pll_init(MHZ(233));
dram_disable_bypass();
break;
case 667: case 667:
dram_pll_init(MHZ(167)); dram_pll_init(MHZ(167));
dram_disable_bypass(); dram_disable_bypass();