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Coding Style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
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8c8428a576
commit
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22 changed files with 2130 additions and 291 deletions
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@ -29,4 +29,3 @@
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#
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TEXT_BASE = 0x8FFC0000
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@ -42,7 +42,6 @@
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.align 2
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lowlevel_init:
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mov.l CCR_A, r1 ! Address of Cache Control Register
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mov.l CCR_D, r0 ! Instruction Cache Invalidate
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mov.l r0, @r1
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@ -100,7 +99,6 @@ lowlevel_init:
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mov.l r0, @r1
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bsc_init:
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mov.l CMNCR_A, r1 ! CMNCR address -> R1
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mov.l CMNCR_D, r0 ! CMNCR data -> R0
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mov.l r0, @r1 ! CMNCR set
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@ -188,8 +186,6 @@ bsc_init:
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rts
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mov #0, r0
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.align 4
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CCR_A: .long CCR
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@ -266,4 +262,3 @@ PSCR_D: .word 0x0000
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RWTCSR_D_1: .word 0xA507
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RWTCSR_D_2: .word 0xA504 ! 20080115
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RWTCNT_D: .word 0x5A00
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@ -51,4 +51,3 @@ int dram_init (void)
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void led_set_state (unsigned short value)
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{
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}
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@ -103,4 +103,3 @@ SECTIONS
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PROVIDE (_end = .);
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}
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@ -159,4 +159,3 @@ int dram_init(void)
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printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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@ -69,9 +69,11 @@ int get_clocks (void)
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/* Setup PLL */
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pll->syncr = 0x01080000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK));
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while (!(pll->synsr & FMPLL_SYNSR_LOCK)
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;
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pll->syncr = 0x01000000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK));
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while (!(pll->synsr & FMPLL_SYNSR_LOCK))
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;
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#endif
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gd->cpu_clk = CFG_CLK;
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@ -2494,8 +2494,7 @@ e1000_phy_reset(struct e1000_hw *hw)
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return 0;
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}
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static int
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e1000_set_phy_type(struct e1000_hw *hw)
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static int e1000_set_phy_type (struct e1000_hw *hw)
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{
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DEBUGFUNC ();
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@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm {
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uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
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char res19[4];
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uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
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char res20[780]; // XXX: LAW 8, LAW9 for 8572
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char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
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uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
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char res21[12];
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uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
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@ -478,7 +478,6 @@
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#define SPRN_MSSSR0 0x3f7
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#endif
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/* Short-hand versions for a number of the above SPRNs */
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#define CTR SPRN_CTR /* Counter Register */
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@ -737,7 +736,6 @@
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#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
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#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
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/* Processor Version Register */
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/* Processor Version Register (PVR) field extraction */
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@ -861,7 +859,6 @@
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#define PVR_5200 0x80822011
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#define PVR_5200B 0x80822014
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/*
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* System Version Register
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*/
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@ -882,7 +879,6 @@
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/* Some parts define SVR[0:23] as the SOC version */
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
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/*
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* SVR_SOC_VER() Version Values
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*/
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@ -915,8 +911,6 @@
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#define SVR_8641 0x809000
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#define SVR_8641D 0x809001
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/* I am just adding a single entry for 8260 boards. I think we may be
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* able to combine mbx, fads, rpxlite, bseip, and classic into a single
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* generic 8xx as well. The boards containing these processors are either
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@ -944,7 +938,6 @@
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#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
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#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */
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/* see residual.h for these */
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#define _PREP_Motorola 0x01 /* motorola prep */
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#define _PREP_Firm 0x02 /* firmworks prep */
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@ -13,8 +13,7 @@ void dcache_wback_range(u32 start, u32 end)
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start &= ~(L1_CACHE_BYTES - 1);
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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asm volatile("ocbwb %0"
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: /* no output */
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asm volatile ("ocbwb %0": /* no output */
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:"m" (__m (v)));
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}
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}
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@ -25,8 +24,7 @@ void dcache_invalid_range(u32 start, u32 end)
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start &= ~(L1_CACHE_BYTES - 1);
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for (v = start; v < end; v += L1_CACHE_BYTES) {
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asm volatile("ocbi %0"
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: /* no output */
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asm volatile ("ocbi %0": /* no output */
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:"m" (__m (v)));
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}
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}
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@ -33,5 +33,4 @@
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* ctrl, memory controllers etc.
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*/
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#endif
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@ -2073,4 +2073,3 @@
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#define PCI_DEVICE_ID_MPC8641 0x7010
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#define PCI_DEVICE_ID_MPC8641D 0x7011
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#define PCI_DEVICE_ID_MPC8610 0x7018
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