mirror of
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Prepare v2024.10-rc5
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This commit is contained in:
Tom Rini
commit
19dbc09405
34 changed files with 240 additions and 132 deletions
2
Makefile
2
Makefile
|
|
@ -3,7 +3,7 @@
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|||
VERSION = 2024
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||||
PATCHLEVEL = 10
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SUBLEVEL =
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EXTRAVERSION = -rc4
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EXTRAVERSION = -rc5
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NAME =
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# *DOCUMENTATION*
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|
|
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@ -111,6 +111,8 @@
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#endif
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#address-cells = <1>;
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offset = <0x57c00>;
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images {
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uboot {
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arch = "arm64";
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|
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@ -8,7 +8,6 @@
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#include "r8a779x-u-boot.dtsi"
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&rpc {
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reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
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bank-width = <2>;
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num-cs = <1>;
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};
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|
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@ -13,29 +13,9 @@
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};
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};
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&pfc {
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qspi0_pins: qspi0 {
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groups = "qspi0_ctrl", "qspi0_data4";
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function = "qspi0";
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};
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};
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&rpc {
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pinctrl-0 = <&qspi0_pins>;
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pinctrl-names = "default";
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <40000000>;
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status = "disabled";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "jedec,spi-nor";
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reg = <0>;
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flash@0 {
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <40000000>;
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};
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};
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@ -149,6 +149,7 @@ config TARGET_TURRIS_OMNIA
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select SPL_SYS_MALLOC_SIMPLE
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select SYS_I2C_MVTWSI
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select ATSHA204A
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select I2C_EEPROM
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select ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
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config TARGET_TURRIS_MOX
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@ -138,6 +138,7 @@ config FRAMEPOINTER
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config SPL_FRAMEPOINTER
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bool "Build SPL with frame pointer for stack unwinding"
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depends on SPL
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help
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Choose this option to use the frame pointer so the stack can be
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unwound if needed. This is useful for tracing where faults came
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@ -445,7 +446,20 @@ config AVAILABLE_HARTS
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If disable this, it will send IPI by CPUs node numbers of device tree.
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config SHOW_REGS
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default y
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bool "Show registers on unhandled exception"
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help
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By default only the program counter and the return address register
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are shown in crash dumps. Enable this symbol to show all registers in
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main U-Boot.
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config SPL_SHOW_REGS
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bool "In SPL show registers on unhandled exception"
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depends on SPL
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help
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By default only the program counter and the return address register
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are shown in crash dumps. Enable this symbol to show all registers in
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SPL.
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config RISCV_PRIV_1_9
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bool "Use version 1.9 of the RISC-V priviledged specification"
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|
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@ -138,6 +138,43 @@ static inline unsigned long ffz(unsigned long word)
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return k;
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}
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static inline int find_next_zero_bit(void *addr, int size, int offset)
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{
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unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG);
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unsigned long result = offset & ~(BITS_PER_LONG - 1);
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unsigned long tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= (BITS_PER_LONG - 1);
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if (offset) {
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tmp = *(p++);
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tmp |= ~0UL >> (BITS_PER_LONG - offset);
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if (size < BITS_PER_LONG)
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goto found_first;
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if (~tmp)
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goto found_middle;
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size -= BITS_PER_LONG;
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result += BITS_PER_LONG;
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}
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while (size & ~(BITS_PER_LONG - 1)) {
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tmp = *(p++);
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if (~tmp)
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goto found_middle;
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result += BITS_PER_LONG;
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size -= BITS_PER_LONG;
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}
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if (!size)
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return result;
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tmp = *p;
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found_first:
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tmp |= ~0UL << size;
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found_middle:
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return result + ffz(tmp);
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}
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/*
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* ffs: find first bit set. This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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@ -158,6 +195,9 @@ static inline unsigned long ffz(unsigned long word)
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#define hweight16(x) generic_hweight16(x)
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#define hweight8(x) generic_hweight8(x)
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#define find_first_zero_bit(addr, size) \
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find_next_zero_bit((addr), (size), 0)
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#define test_and_set_bit __test_and_set_bit
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#define test_and_clear_bit __test_and_clear_bit
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|
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@ -34,9 +34,8 @@ static void show_efi_loaded_images(uintptr_t epc)
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efi_print_image_infos((void *)epc);
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}
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static void show_regs(struct pt_regs *regs)
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static void __maybe_unused show_regs(struct pt_regs *regs)
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{
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#ifdef CONFIG_SHOW_REGS
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printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
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regs->sp, regs->gp, regs->tp);
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printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
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@ -57,7 +56,6 @@ static void show_regs(struct pt_regs *regs)
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regs->s10, regs->s11, regs->t3);
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printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n",
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regs->t4, regs->t5, regs->t6);
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#endif
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}
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static void __maybe_unused show_backtrace(struct pt_regs *regs)
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@ -157,7 +155,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
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printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
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epc - gd->reloc_off, regs->ra - gd->reloc_off);
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show_regs(regs);
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if (CONFIG_IS_ENABLED(SHOW_REGS))
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show_regs(regs);
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if (CONFIG_IS_ENABLED(FRAMEPOINTER))
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show_backtrace(regs);
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show_code(epc);
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@ -23,6 +23,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <fdt_support.h>
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#include <hexdump.h>
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#include <i2c_eeprom.h>
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#include <time.h>
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#include <turris-omnia-mcu-interface.h>
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#include <linux/bitops.h>
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@ -46,6 +47,9 @@ DECLARE_GLOBAL_DATA_PTR;
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#define OMNIA_I2C_EEPROM_CHIP_LEN 2
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#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
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#define OMNIA_RESET_TO_LOWER_DDR_SPEED 9
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#define OMNIA_LOWER_DDR_SPEED "1333H"
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#define A385_SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260)
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#define A385_SYS_RSTOUT_MASK_WD BIT(10)
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@ -205,6 +209,20 @@ static u32 omnia_mcu_crc32(const void *p, size_t len)
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return ~bitrev32(crc);
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}
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static int omnia_mcu_get_reset(void)
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{
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u8 reset_status;
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int ret;
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ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
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if (ret) {
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printf("omnia_mcu_read failed: %i, reset status unknown!\n", ret);
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return ret;
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}
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return reset_status;
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}
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/* Can only be called after relocation, since it needs cleared BSS */
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static int omnia_mcu_board_info(char *serial, u8 *mac, char *version)
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{
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@ -462,20 +480,27 @@ static bool check_eeprom_crc(const void *buf, size_t size, u32 expected,
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return true;
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}
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static struct udevice *omnia_get_eeprom(void)
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{
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return omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
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OMNIA_I2C_EEPROM_CHIP_LEN);
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}
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static bool omnia_read_eeprom(struct omnia_eeprom *oep)
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{
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struct udevice *chip;
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struct udevice *eeprom = omnia_get_eeprom();
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int ret;
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chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
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OMNIA_I2C_EEPROM_CHIP_LEN);
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if (!chip)
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if (!eeprom)
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return false;
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ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
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if (IS_ENABLED(CONFIG_SPL_BUILD))
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ret = dm_i2c_read(eeprom, 0, (void *)oep, sizeof(*oep));
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else
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ret = i2c_eeprom_read(eeprom, 0, (void *)oep, sizeof(*oep));
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if (ret) {
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printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
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printf("cannot read EEPROM: %d\n", ret);
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return false;
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}
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@ -497,6 +522,35 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep)
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return true;
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}
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static void omnia_eeprom_set_lower_ddr_speed(void)
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{
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struct udevice *eeprom = omnia_get_eeprom();
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struct omnia_eeprom oep;
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int ret;
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if (!eeprom || !omnia_read_eeprom(&oep))
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return;
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puts("Setting DDR speed to " OMNIA_LOWER_DDR_SPEED " in EEPROM as requested by reset button... ");
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/* check if already set */
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if (!strncmp(oep.ddr_speed, OMNIA_LOWER_DDR_SPEED, sizeof(oep.ddr_speed)) &&
|
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(oep.old_ddr_training == 0 || oep.old_ddr_training == 0xff)) {
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puts("was already set\n");
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return;
|
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}
|
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|
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strncpy(oep.ddr_speed, OMNIA_LOWER_DDR_SPEED, sizeof(oep.ddr_speed));
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oep.old_ddr_training = 0xff;
|
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oep.crc2 = crc32(0, (const void *)&oep, offsetof(struct omnia_eeprom, crc2));
|
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|
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ret = i2c_eeprom_write(eeprom, 0, (const void *)&oep, sizeof(oep));
|
||||
if (ret)
|
||||
printf("cannot write EEPROM: %d\n", ret);
|
||||
else
|
||||
puts("done\n");
|
||||
}
|
||||
|
||||
int omnia_get_ram_size_gb(void)
|
||||
{
|
||||
static int ram_size;
|
||||
|
|
@ -526,6 +580,13 @@ bool board_use_old_ddr3_training(void)
|
|||
{
|
||||
struct omnia_eeprom oep;
|
||||
|
||||
/*
|
||||
* If lower DDR speed is requested by reset button, we can't use old DDR
|
||||
* training algorithm.
|
||||
*/
|
||||
if (omnia_mcu_get_reset() == OMNIA_RESET_TO_LOWER_DDR_SPEED)
|
||||
return false;
|
||||
|
||||
if (!omnia_read_eeprom(&oep))
|
||||
return false;
|
||||
|
||||
|
|
@ -706,13 +767,19 @@ static void fixup_speed_in_ddr_topology(struct mv_ddr_topology_map *topology)
|
|||
const struct omnia_ddr_speed *setting;
|
||||
const char *speed;
|
||||
static bool done;
|
||||
int reset_status;
|
||||
|
||||
if (done)
|
||||
return;
|
||||
|
||||
done = true;
|
||||
|
||||
speed = omnia_get_ddr_speed();
|
||||
reset_status = omnia_mcu_get_reset();
|
||||
if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
|
||||
speed = OMNIA_LOWER_DDR_SPEED;
|
||||
else
|
||||
speed = omnia_get_ddr_speed();
|
||||
|
||||
if (!speed)
|
||||
return;
|
||||
|
||||
|
|
@ -729,7 +796,10 @@ static void fixup_speed_in_ddr_topology(struct mv_ddr_topology_map *topology)
|
|||
if (params->speed_bin_index == setting->speed_bin)
|
||||
return;
|
||||
|
||||
printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
|
||||
if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
|
||||
printf("Fixing up DDR3 speed to %s as requested by reset button\n", speed);
|
||||
else
|
||||
printf("Fixing up DDR3 speed (EEPROM defines %s)\n", speed);
|
||||
|
||||
params->speed_bin_index = setting->speed_bin;
|
||||
params->memory_freq = setting->freq;
|
||||
|
|
@ -766,8 +836,7 @@ static int set_regdomain(void)
|
|||
static void handle_reset_button(void)
|
||||
{
|
||||
const char * const vars[1] = { "bootcmd_rescue", };
|
||||
int ret;
|
||||
u8 reset_status;
|
||||
int reset_status;
|
||||
|
||||
/*
|
||||
* Ensure that bootcmd_rescue has always stock value, so that running
|
||||
|
|
@ -776,12 +845,12 @@ static void handle_reset_button(void)
|
|||
*/
|
||||
env_set_default_vars(1, (char * const *)vars, 0);
|
||||
|
||||
ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
|
||||
if (ret) {
|
||||
printf("omnia_mcu_read failed: %i, reset status unknown!\n",
|
||||
ret);
|
||||
reset_status = omnia_mcu_get_reset();
|
||||
if (reset_status < 0)
|
||||
return;
|
||||
}
|
||||
|
||||
if (reset_status == OMNIA_RESET_TO_LOWER_DDR_SPEED)
|
||||
return omnia_eeprom_set_lower_ddr_speed();
|
||||
|
||||
env_set_ulong("omnia_reset", reset_status);
|
||||
|
||||
|
|
|
|||
|
|
@ -170,23 +170,32 @@ void spl_fdt_fixup_mars_cm(void *fdt)
|
|||
{
|
||||
const char *compat;
|
||||
const char *model;
|
||||
int compat_size;
|
||||
|
||||
spl_fdt_fixup_mars(fdt);
|
||||
|
||||
if (!get_mmc_size_from_eeprom()) {
|
||||
int offset;
|
||||
static const char
|
||||
compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110";
|
||||
|
||||
model = "Milk-V Mars CM Lite";
|
||||
compat = "milkv,mars-cm-lite\0starfive,jh7110";
|
||||
compat = compat_cm_lite;
|
||||
compat_size = sizeof(compat_cm_lite);
|
||||
|
||||
offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
|
||||
/* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
|
||||
fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
|
||||
} else {
|
||||
static const char
|
||||
compat_cm[] = "milkv,mars-cm\0starfive,jh7110";
|
||||
|
||||
model = "Milk-V Mars CM";
|
||||
compat = "milkv,mars-cm\0starfive,jh7110";
|
||||
compat = compat_cm;
|
||||
compat_size = sizeof(compat_cm);
|
||||
}
|
||||
fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
|
||||
fdt_setprop(fdt, fdt_path_offset(fdt, "/"),
|
||||
"compatible", compat, compat_size);
|
||||
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -139,8 +139,13 @@ static int ab_control_store(struct blk_desc *dev_desc,
|
|||
{
|
||||
ulong abc_offset, abc_blocks, ret;
|
||||
|
||||
abc_offset = offset +
|
||||
offsetof(struct bootloader_message_ab, slot_suffix) /
|
||||
if (offset % part_info->blksz) {
|
||||
log_err("ANDROID: offset not block aligned\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
abc_offset = (offset +
|
||||
offsetof(struct bootloader_message_ab, slot_suffix)) /
|
||||
part_info->blksz;
|
||||
abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control),
|
||||
part_info->blksz);
|
||||
|
|
|
|||
|
|
@ -36,6 +36,14 @@ static int do_ialign16(struct cmd_tbl *cmdtp, int flag, int argc,
|
|||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static int do_rdcycle(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
printf("cycle = 0x%lx\n", csr_read(CSR_CYCLE));
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
}
|
||||
|
||||
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
|
|
@ -62,6 +70,8 @@ static struct cmd_tbl cmd_sub[] = {
|
|||
"", ""),
|
||||
U_BOOT_CMD_MKENT(ialign16, CONFIG_SYS_MAXARGS, 1, do_ialign16,
|
||||
"", ""),
|
||||
U_BOOT_CMD_MKENT(rdcycle, CONFIG_SYS_MAXARGS, 1, do_rdcycle,
|
||||
"", ""),
|
||||
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
|
||||
"", ""),
|
||||
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
|
||||
|
|
@ -74,7 +84,8 @@ U_BOOT_LONGHELP(exception,
|
|||
" compressed - compressed instruction\n"
|
||||
" ebreak - breakpoint\n"
|
||||
" ialign16 - 16 bit aligned instruction\n"
|
||||
" undefined - illegal instruction\n"
|
||||
" unaligned - load address misaligned\n");
|
||||
" rdcycle - read cycle CSR\n"
|
||||
" unaligned - load address misaligned\n"
|
||||
" undefined - illegal instruction\n");
|
||||
|
||||
#include <exception.h>
|
||||
|
|
|
|||
|
|
@ -986,7 +986,8 @@ config ANDROID_AB_BACKUP_OFFSET
|
|||
help
|
||||
If non-zero, a backup bootloader message starting at this offset in
|
||||
the partition will tried in the event that the primary one (starting
|
||||
at offset 0) fails its checksum.
|
||||
at offset 0) fails its checksum. The offset is in bytes and must be
|
||||
multiple of the block size.
|
||||
|
||||
endmenu
|
||||
|
||||
|
|
|
|||
|
|
@ -92,7 +92,6 @@ CONFIG_SPL_OF_TRANSLATE=y
|
|||
CONFIG_AHCI_PCI=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_MV=y
|
||||
CONFIG_DM_MTD=y
|
||||
|
|
|
|||
|
|
@ -82,9 +82,9 @@ A bash script similar to the one below may be used:
|
|||
Adopted toolchains
|
||||
------------------
|
||||
|
||||
Please check:
|
||||
https://www.denx.de/wiki/U-Boot/ColdFireNotes
|
||||
|
||||
Currently the `kernel.org cross-development toolchains
|
||||
<https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/>`_ are
|
||||
used in the project CI builds.
|
||||
|
||||
ColdFire specific configuration options/settings
|
||||
------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -8,9 +8,8 @@ Notes for the MIPS architecture port of U-Boot
|
|||
Toolchains
|
||||
----------
|
||||
|
||||
* `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
|
||||
* `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
|
||||
* `Buildroot <http://buildroot.uclibc.org/>`_
|
||||
* `kernel.org cross-development toolchains <https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/>`_
|
||||
|
||||
Known Issues
|
||||
------------
|
||||
|
|
|
|||
|
|
@ -23,9 +23,8 @@ Management Summary
|
|||
Phases of the Development Process
|
||||
---------------------------------
|
||||
|
||||
U-Boot development takes place in `Release Cycles
|
||||
<https://www.denx.de/wiki/U-Boot/ReleaseCycle>`_. A Release Cycle lasts
|
||||
normally for three months.
|
||||
U-Boot development takes place in a :doc:`release_cycle`. A Release Cycle
|
||||
lasts normally for three months.
|
||||
|
||||
The first three weeks of each Release Cycle are called *Merge Window*.
|
||||
|
||||
|
|
|
|||
|
|
@ -73,12 +73,13 @@ General Patch Submission Rules
|
|||
cover letter why they are ignored is desired.
|
||||
|
||||
* Send your patches as plain text messages: no HTML, no MIME, no links, no
|
||||
compression, no attachments. Just plain text. The best way the generate
|
||||
patches is by using the ``git format-patch`` command. Please use the
|
||||
``master`` branch of the mainline U-Boot git repository
|
||||
(``https://source.denx.de/u-boot/u-boot.git``) as reference, unless (usually
|
||||
late in a release cycle) there has been an announcement to use the ``next``
|
||||
branch of this repository instead.
|
||||
compression, no attachments. Just plain text. The best way to generate
|
||||
patches is by using the ``git format-patch`` command. For a patch that is
|
||||
fixing a bug or regression of some sort, please use the ``master`` branch of
|
||||
the mainline U-Boot git repository located at
|
||||
https://source.denx.de/u-boot/u-boot.git as reference. For new features, if
|
||||
the ``next`` branch has been opened (which happens with the release of
|
||||
``-rc2``) that branch should be used, otherwise ``master`` is acceptable.
|
||||
|
||||
* Make sure that your mailer does not mangle the patch by automatic changes
|
||||
like wrapping of longer lines etc.
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ release that came out in October 2020. Release candidates are tagged every few
|
|||
weeks as the project heads to the next release. So 2020.10-rc1 was the first
|
||||
release candidate (RC), tagged soon after 2020.07 was released.
|
||||
|
||||
See https://www.denx.de/wiki/view/U-Boot/ReleaseCycle for full details.
|
||||
See :doc:`release_cycle` for full details.
|
||||
|
||||
Within the build system, various Makefile variables are created, making use of
|
||||
VERSION, PATCHLEVEL and EXTRAVERSION defined at the top of 'Makefile'. There is
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
Bootcount Configuration
|
||||
This is the implementation of the feature as described in
|
||||
https://www.denx.de/wiki/DULG/UBootBootCountLimit.
|
||||
https://docs.u-boot.org/en/latest/api/bootcount.html
|
||||
|
||||
Required Properties:
|
||||
- compatible: must be "u-boot,bootcount-syscon".
|
||||
|
|
|
|||
|
|
@ -153,4 +153,4 @@ The directory in which all capsule files be placed
|
|||
Written by AKASHI Takahiro <takahiro.akashi@linaro.org>
|
||||
|
||||
.SH HOMEPAGE
|
||||
http://www.denx.de/wiki/U-Boot/WebHome
|
||||
http://www.u-boot.org/
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ menuconfig BOOTCOUNT_LIMIT
|
|||
bool "Enable support for checking boot count limit"
|
||||
help
|
||||
Enable checking for exceeding the boot count limit.
|
||||
More information: http://www.denx.de/wiki/DULG/UBootBootCountLimit
|
||||
More information: https://docs.u-boot.org/en/latest/api/bootcount.html
|
||||
|
||||
if BOOTCOUNT_LIMIT
|
||||
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
|
|||
{
|
||||
if (post_divr_freq < MIN_POST_DIVR_FREQ ||
|
||||
post_divr_freq > MAX_POST_DIVR_FREQ) {
|
||||
WARN(1, "%s: post-divider reference freq out of range: %lu",
|
||||
WARN(1, "%s: post-divider reference freq out of range: %lu\n",
|
||||
__func__, post_divr_freq);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
|
@ -229,7 +229,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
|
|||
int range;
|
||||
|
||||
if (c->flags == 0) {
|
||||
WARN(1, "%s called with uninitialized PLL config", __func__);
|
||||
WARN(1, "%s called with uninitialized PLL config\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -335,7 +335,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
|
|||
u64 n;
|
||||
|
||||
if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
|
||||
WARN(1, "external feedback mode not yet supported");
|
||||
WARN(1, "external feedback mode not yet supported\n");
|
||||
return ULONG_MAX;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
|
|||
};
|
||||
|
||||
/* List of clock controls provided by the PRCI */
|
||||
struct __prci_clock __prci_init_clocks_fu540[] = {
|
||||
static struct __prci_clock __prci_init_clocks_fu540[] = {
|
||||
[PRCI_CLK_COREPLL] = {
|
||||
.name = "corepll",
|
||||
.parent_name = "hfclk",
|
||||
|
|
@ -83,3 +83,8 @@ struct __prci_clock __prci_init_clocks_fu540[] = {
|
|||
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
|
||||
},
|
||||
};
|
||||
|
||||
const struct prci_clk_desc prci_clk_fu540 = {
|
||||
.clks = __prci_init_clocks_fu540,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020-2021 SiFive, Inc.
|
||||
* Zong Li
|
||||
* Pragnesh Patel
|
||||
*/
|
||||
|
||||
#ifndef __SIFIVE_CLK_FU540_PRCI_H
|
||||
#define __SIFIVE_CLK_FU540_PRCI_H
|
||||
|
||||
#include "sifive-prci.h"
|
||||
|
||||
#define NUM_CLOCK_FU540 4
|
||||
|
||||
extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu540 = {
|
||||
.clks = __prci_init_clocks_fu540,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
||||
};
|
||||
|
||||
#endif /* __SIFIVE_CLK_FU540_PRCI_H */
|
||||
|
|
@ -102,7 +102,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
|
|||
};
|
||||
|
||||
/* List of clock controls provided by the PRCI */
|
||||
struct __prci_clock __prci_init_clocks_fu740[] = {
|
||||
static struct __prci_clock __prci_init_clocks_fu740[] = {
|
||||
[FU740_PRCI_CLK_COREPLL] = {
|
||||
.name = "corepll",
|
||||
.parent_name = "hfclk",
|
||||
|
|
@ -156,3 +156,8 @@ struct __prci_clock __prci_init_clocks_fu740[] = {
|
|||
.pwd = &__prci_pcieaux_data,
|
||||
}
|
||||
};
|
||||
|
||||
const struct prci_clk_desc prci_clk_fu740 = {
|
||||
.clks = __prci_init_clocks_fu740,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020-2021 SiFive, Inc.
|
||||
* Zong Li
|
||||
* Pragnesh Patel
|
||||
*/
|
||||
|
||||
#ifndef __SIFIVE_CLK_FU740_PRCI_H
|
||||
#define __SIFIVE_CLK_FU740_PRCI_H
|
||||
|
||||
#include "sifive-prci.h"
|
||||
|
||||
#define NUM_CLOCK_FU740 9
|
||||
|
||||
extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu740 = {
|
||||
.clks = __prci_init_clocks_fu740,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
|
||||
};
|
||||
|
||||
#endif /* __SIFIVE_CLK_FU740_PRCI_H */
|
||||
|
|
@ -33,8 +33,7 @@
|
|||
#include <linux/math64.h>
|
||||
#include <dt-bindings/clock/sifive-fu740-prci.h>
|
||||
|
||||
#include "fu540-prci.h"
|
||||
#include "fu740-prci.h"
|
||||
#include "sifive-prci.h"
|
||||
|
||||
/*
|
||||
* Private functions
|
||||
|
|
|
|||
|
|
@ -320,4 +320,8 @@ unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc,
|
|||
|
||||
int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable);
|
||||
|
||||
/* Clock driver data */
|
||||
extern const struct prci_clk_desc prci_clk_fu540;
|
||||
extern const struct prci_clk_desc prci_clk_fu740;
|
||||
|
||||
#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
|
||||
|
|
|
|||
|
|
@ -387,6 +387,7 @@ static int rpc_hf_probe(struct udevice *dev)
|
|||
static const struct udevice_id rpc_hf_ids[] = {
|
||||
{ .compatible = "renesas,r7s72100-rpc-if" },
|
||||
{ .compatible = "renesas,rcar-gen3-rpc-if" },
|
||||
{ .compatible = "renesas,rcar-gen4-rpc-if" },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -145,6 +145,12 @@
|
|||
#define RPC_PHYCNT_WBUF BIT(2)
|
||||
#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
|
||||
|
||||
#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
|
||||
#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
|
||||
|
||||
#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
|
||||
#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
|
||||
|
||||
#define RPC_PHYINT 0x0088 /* R/W */
|
||||
#define RPC_PHYINT_RSTEN BIT(18)
|
||||
#define RPC_PHYINT_WPEN BIT(17)
|
||||
|
|
@ -227,6 +233,12 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
|
|||
struct udevice *bus = dev->parent;
|
||||
struct rpc_spi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
|
||||
RPCIF_PHYOFFSET1_DDRTMG(3));
|
||||
clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
|
||||
RPCIF_PHYOFFSET2_OCTTMG(7),
|
||||
RPCIF_PHYOFFSET2_OCTTMG(4));
|
||||
|
||||
/* NOTE: The 0x260 are undocumented bits, but they must be set. */
|
||||
writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
|
||||
priv->regs + RPC_PHYCNT);
|
||||
|
|
@ -277,24 +289,24 @@ static int rpc_spi_mem_exec_op(struct spi_slave *spi,
|
|||
writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR);
|
||||
smenr |= RPC_DRENR_CDE;
|
||||
|
||||
writel(0, priv->regs + RPC_DREAR);
|
||||
if (op->addr.nbytes == 4) {
|
||||
writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1),
|
||||
priv->regs + RPC_DREAR);
|
||||
smenr |= RPC_DRENR_ADE(0xF);
|
||||
} else if (op->addr.nbytes == 3) {
|
||||
writel(0, priv->regs + RPC_DREAR);
|
||||
smenr |= RPC_DRENR_ADE(0x7);
|
||||
} else {
|
||||
writel(0, priv->regs + RPC_DREAR);
|
||||
smenr |= RPC_DRENR_ADE(0);
|
||||
}
|
||||
|
||||
writel(0, priv->regs + RPC_DRDMCR);
|
||||
if (op->dummy.nbytes) {
|
||||
writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
|
||||
if (op->dummy.nbytes)
|
||||
smenr |= RPC_DRENR_DME;
|
||||
}
|
||||
|
||||
writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR);
|
||||
writel(0, priv->regs + RPC_DROPR);
|
||||
writel(0, priv->regs + RPC_DRDRENR);
|
||||
writel(smenr, priv->regs + RPC_DRENR);
|
||||
|
||||
memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes);
|
||||
|
|
@ -453,6 +465,7 @@ static const struct dm_spi_ops rpc_spi_ops = {
|
|||
static const struct udevice_id rpc_spi_ids[] = {
|
||||
{ .compatible = "renesas,r7s72100-rpc-if" },
|
||||
{ .compatible = "renesas,rcar-gen3-rpc-if" },
|
||||
{ .compatible = "renesas,rcar-gen4-rpc-if" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -185,9 +185,6 @@ endif
|
|||
dtsi_include_list = $(strip $(u_boot_dtsi_options_debug) \
|
||||
$(notdir $(firstword $(u_boot_dtsi_options))))
|
||||
|
||||
# The CONFIG_DEVICE_TREE_INCLUDES also need to be included
|
||||
dtsi_include_list += $(CONFIG_DEVICE_TREE_INCLUDES)
|
||||
|
||||
# Modified for U-Boot
|
||||
upstream_dtsi_include = $(addprefix -I, $(srctree)/dts/upstream/src/ \
|
||||
$(sort $(dir $(wildcard $(srctree)/dts/upstream/src/$(ARCH)/*/*))) \
|
||||
|
|
@ -350,7 +347,7 @@ quiet_cmd_dtc = DTC $@
|
|||
# And finally any custom .dtsi fragments specified with CONFIG_DEVICE_TREE_INCLUDES
|
||||
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
|
||||
(cat $< > $(pre-tmp)); \
|
||||
$(foreach f,$(subst $(quote),,$(dtsi_include_list)), \
|
||||
$(foreach f,$(subst $(quote),,$(dtsi_include_list) $(CONFIG_DEVICE_TREE_INCLUDES)), \
|
||||
echo '$(pound)include "$(f)"' >> $(pre-tmp);) \
|
||||
$(HOSTCC) -E $(dtc_cpp_flags) -I$(obj) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \
|
||||
$(DTC) -O dtb -o $@ -b 0 \
|
||||
|
|
|
|||
|
|
@ -221,7 +221,7 @@ FIPs so that binman and other tools can access the entire image correctly.
|
|||
|
||||
.. _FIP: https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#firmware-image-package-fip
|
||||
.. _`TF-A source tree`: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
|
||||
.. _`send a patch`: https://www.denx.de/wiki/U-Boot/Patches
|
||||
.. _`send a patch`: https://docs.u-boot.org/en/latest/develop/sending_patches.html
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -163,7 +163,7 @@ class Entry_atf_fip(Entry_section):
|
|||
|
||||
.. _FIP: https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#firmware-image-package-fip
|
||||
.. _`TF-A source tree`: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
|
||||
.. _`send a patch`: https://www.denx.de/wiki/U-Boot/Patches
|
||||
.. _`send a patch`: https://docs.u-boot.org/en/latest/develop/sending_patches.html
|
||||
"""
|
||||
def __init__(self, section, etype, node):
|
||||
# Put this here to allow entry-docs and help to work without libfdt
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue