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dm: i2c: Add an explicit test mode to the sandbox I2C driver
At present this driver has a few test features. They are needed for running the driver model unit tests but are confusing and unnecessary if using sandbox at the command line. Add a flag to enable the test mode, and don't enable it by default. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
ba3864f803
commit
182bf92d19
4 changed files with 42 additions and 11 deletions
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@ -17,6 +17,16 @@
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#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
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#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
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#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
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#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
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/**
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* sandbox_i2c_set_test_mode() - set test mode for running unit tests
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*
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* See sandbox_i2c_xfer() for the behaviour changes.
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*
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* @bus: sandbox I2C bus to adjust
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* @test_mode: true to select test mode, false to run normally
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*/
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void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
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enum sandbox_i2c_eeprom_test_mode {
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enum sandbox_i2c_eeprom_test_mode {
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SIE_TEST_MODE_NONE,
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SIE_TEST_MODE_NONE,
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/* Permits read/write of only one byte per I2C transaction */
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/* Permits read/write of only one byte per I2C transaction */
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@ -18,8 +18,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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struct dm_sandbox_i2c_emul_priv {
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struct sandbox_i2c_priv {
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struct udevice *emul;
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bool test_mode;
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};
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};
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static int get_emul(struct udevice *dev, struct udevice **devp,
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static int get_emul(struct udevice *dev, struct udevice **devp,
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@ -47,17 +47,25 @@ static int get_emul(struct udevice *dev, struct udevice **devp,
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return 0;
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return 0;
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}
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}
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void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode)
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{
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struct sandbox_i2c_priv *priv = dev_get_priv(bus);
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priv->test_mode = test_mode;
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}
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static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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int nmsgs)
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{
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{
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struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
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struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
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struct sandbox_i2c_priv *priv = dev_get_priv(bus);
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struct dm_i2c_ops *ops;
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struct dm_i2c_ops *ops;
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struct udevice *emul, *dev;
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struct udevice *emul, *dev;
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bool is_read;
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bool is_read;
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int ret;
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int ret;
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/* Special test code to return success but with no emulation */
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/* Special test code to return success but with no emulation */
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if (msg->addr == SANDBOX_I2C_TEST_ADDR)
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if (priv->test_mode && msg->addr == SANDBOX_I2C_TEST_ADDR)
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return 0;
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return 0;
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ret = i2c_get_chip(bus, msg->addr, 1, &dev);
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ret = i2c_get_chip(bus, msg->addr, 1, &dev);
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@ -68,15 +76,18 @@ static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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if (ret)
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if (ret)
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return ret;
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return ret;
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/*
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if (priv->test_mode) {
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* For testing, don't allow writing above 100KHz for writes and
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/*
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* 400KHz for reads
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* For testing, don't allow writing above 100KHz for writes and
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*/
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* 400KHz for reads.
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is_read = nmsgs > 1;
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*/
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if (i2c->speed_hz > (is_read ? 400000 : 100000)) {
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is_read = nmsgs > 1;
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debug("%s: Max speed exceeded\n", __func__);
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if (i2c->speed_hz > (is_read ? 400000 : 100000)) {
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return -EINVAL;
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debug("%s: Max speed exceeded\n", __func__);
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return -EINVAL;
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}
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}
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}
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return ops->xfer(emul, msg, nmsgs);
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return ops->xfer(emul, msg, nmsgs);
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}
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}
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@ -94,4 +105,5 @@ U_BOOT_DRIVER(i2c_sandbox) = {
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.id = UCLASS_I2C,
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.id = UCLASS_I2C,
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.of_match = sandbox_i2c_ids,
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.of_match = sandbox_i2c_ids,
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.ops = &sandbox_i2c_ops,
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.ops = &sandbox_i2c_ops,
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.priv_auto_alloc_size = sizeof(struct sandbox_i2c_priv),
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};
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};
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@ -54,6 +54,7 @@ struct dm_i2c_chip {
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uint flags;
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uint flags;
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#ifdef CONFIG_SANDBOX
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#ifdef CONFIG_SANDBOX
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struct udevice *emul;
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struct udevice *emul;
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bool test_mode;
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#endif
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#endif
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};
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};
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@ -66,6 +66,9 @@ static int dm_test_i2c_speed(struct dm_test_state *dms)
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uint8_t buf[5];
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uint8_t buf[5];
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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/* Use test mode so we create the required errors for invalid speeds */
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sandbox_i2c_set_test_mode(bus, true);
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ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
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ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
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ut_assertok(dm_i2c_set_bus_speed(bus, 100000));
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ut_assertok(dm_i2c_set_bus_speed(bus, 100000));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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@ -73,6 +76,7 @@ static int dm_test_i2c_speed(struct dm_test_state *dms)
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ut_asserteq(400000, dm_i2c_get_bus_speed(bus));
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ut_asserteq(400000, dm_i2c_get_bus_speed(bus));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_assertok(dm_i2c_read(dev, 0, buf, 5));
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ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5));
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ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5));
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sandbox_i2c_set_test_mode(bus, false);
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return 0;
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return 0;
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}
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}
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@ -100,7 +104,11 @@ static int dm_test_i2c_probe_empty(struct dm_test_state *dms)
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struct udevice *bus, *dev;
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struct udevice *bus, *dev;
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
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/* Use test mode so that this chip address will always probe */
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sandbox_i2c_set_test_mode(bus, true);
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ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
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ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
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sandbox_i2c_set_test_mode(bus, false);
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return 0;
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return 0;
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}
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}
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