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arm64: zynqmp: Switch to amd.com emails

Browse source 
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-07-10 14:35:49 +02:00
parent 378f4eef09
commit 174d728471
101 changed files with 116 additions and 116 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/dts/avnet-ultra96-rev1.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2018 - 2020, Xilinx, Inc. * (C) Copyright 2018 - 2020, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/versal-mini-emmc0.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018-2019, Xilinx, Inc. * (C) Copyright 2018-2019, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/versal-mini-emmc1.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018-2019, Xilinx, Inc. * (C) Copyright 2018-2019, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/versal-mini-ospi.dtsi
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018-2019, Xilinx, Inc. * (C) Copyright 2018-2019, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/versal-mini-qspi.dtsi
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018-2019, Xilinx, Inc. * (C) Copyright 2018-2019, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/versal-mini.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynq-dlc20-rev1.0.dts
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@ -2,7 +2,7 @@
/* /*
* Copyright (C) 2018 Xilinx, Inc. * Copyright (C) 2018 Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;
#include "zynq-7000.dtsi" #include "zynq-7000.dtsi"

2
arch/arm/dts/zynq-minized.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2018, Xilinx, Inc. * (C) Copyright 2017 - 2018, Xilinx, Inc.
* *
* Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> * Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-a2197-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-clk-ccf.dtsi
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <dt-bindings/clock/xlnx-zynqmp-clk.h> #include <dt-bindings/clock/xlnx-zynqmp-clk.h>

2
arch/arm/dts/zynqmp-dlc21-revA.dts
View file

@ -4,7 +4,7 @@
* *
* (C) Copyright 2019 - 2021, Xilinx, Inc. * (C) Copyright 2019 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019 - 2021, Xilinx, Inc. * (C) Copyright 2019 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-mini-emmc0.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2018, Xilinx, Inc. * (C) Copyright 2018, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-mini-emmc1.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2018, Xilinx, Inc. * (C) Copyright 2018, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-mini-nand.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018, Xilinx, Inc. * (C) Copyright 2018, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-mini-qspi.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2015 - 2020, Xilinx, Inc. * (C) Copyright 2015 - 2020, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-mini.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017, Xilinx, Inc. * (C) Copyright 2017, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2019, Xilinx, Inc. * (C) Copyright 2019, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-r5.dts
View file

@ -4,7 +4,7 @@
* *
* (C) Copyright 2018, Xilinx, Inc. * (C) Copyright 2018, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-sck-kr-g-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2021, Xilinx, Inc. * (C) Copyright 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>

2
arch/arm/dts/zynqmp-sck-kr-g-revB.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2021 - 2022, Xilinx, Inc. * (C) Copyright 2021 - 2022, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>

2
arch/arm/dts/zynqmp-sck-kv-g-revA.dts
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@ -9,7 +9,7 @@
* "Y" – A01 board modified with legacy interposer (Nexperia) * "Y" – A01 board modified with legacy interposer (Nexperia)
* "Z" – A01 board modified with Diode interposer * "Z" – A01 board modified with Diode interposer
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>

2
arch/arm/dts/zynqmp-sck-kv-g-revB.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2020 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>

2
arch/arm/dts/zynqmp-sm-k26-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2020 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-smk-k26-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2020 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include "zynqmp-sm-k26-revA.dts" #include "zynqmp-sm-k26-revA.dts"

2
arch/arm/dts/zynqmp-zc1232-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-zc1254-revA.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2015 - 2020, Xilinx, Inc. * (C) Copyright 2015 - 2020, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2015 - 2021, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2015 - 2021, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2021, Xilinx, Inc. * (C) Copyright 2016 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2015 - 2021, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2015 - 2021, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu100-revC.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2021, Xilinx, Inc. * (C) Copyright 2016 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Nathalie Chan King Choy * Nathalie Chan King Choy
*/ */

2
arch/arm/dts/zynqmp-zcu102-rev1.0.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2020, Xilinx, Inc. * (C) Copyright 2016 - 2020, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include "zynqmp-zcu102-revB.dts" #include "zynqmp-zcu102-revB.dts"

2
arch/arm/dts/zynqmp-zcu102-rev1.1.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2020, Xilinx, Inc. * (C) Copyright 2016 - 2020, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include "zynqmp-zcu102-rev1.0.dts" #include "zynqmp-zcu102-rev1.0.dts"

2
arch/arm/dts/zynqmp-zcu102-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2015 - 2021, Xilinx, Inc. * (C) Copyright 2015 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu102-revB.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2020, Xilinx, Inc. * (C) Copyright 2016 - 2020, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include "zynqmp-zcu102-revA.dts" #include "zynqmp-zcu102-revA.dts"

2
arch/arm/dts/zynqmp-zcu104-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu104-revC.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu106-rev1.0.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2022, Xilinx, Inc. * (C) Copyright 2016 - 2022, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include "zynqmp-zcu106-revA.dts" #include "zynqmp-zcu106-revA.dts"

2
arch/arm/dts/zynqmp-zcu106-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2016 - 2021, Xilinx, Inc. * (C) Copyright 2016 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu111-revA.dts
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@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-zcu1275-revA.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-zcu1275-revB.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018 - 2021, Xilinx, Inc. * (C) Copyright 2018 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

4
arch/arm/dts/zynqmp-zcu1285-revA.dts
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@ -4,8 +4,8 @@
* *
* (C) Copyright 2018 - 2021, Xilinx, Inc. * (C) Copyright 2018 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu208-revA.dts
View file

@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp-zcu216-revA.dts
View file

@ -4,7 +4,7 @@
* *
* (C) Copyright 2017 - 2021, Xilinx, Inc. * (C) Copyright 2017 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/dts/zynqmp.dtsi
View file

@ -4,7 +4,7 @@
* *
* (C) Copyright 2014 - 2021, Xilinx, Inc. * (C) Copyright 2014 - 2021, Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as

2
arch/arm/mach-tegra/arm64-mmu.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* (This file derived from arch/arm/mach-zynqmp/cpu.c) * (This file derived from arch/arm/mach-zynqmp/cpu.c)
* *
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.

2
arch/arm/mach-versal/Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
# (C) Copyright 2016 - 2018 Xilinx, Inc. # (C) Copyright 2016 - 2018 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com> # Michal Simek <michal.simek@amd.com>
# #
obj-y += clk.o obj-y += clk.o

2
arch/arm/mach-versal/clk.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2016 - 2018 Xilinx, Inc. * (C) Copyright 2016 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-versal/cpu.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2016 - 2018 Xilinx, Inc. * (C) Copyright 2016 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-versal/mp.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* (C) Copyright 2019 Xilinx, Inc. * (C) Copyright 2019 Xilinx, Inc.
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-zynqmp/Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
# (C) Copyright 2014 - 2015 Xilinx, Inc. # (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com> # Michal Simek <michal.simek@amd.com>
obj-y += clk.o obj-y += clk.o
obj-y += cpu.o obj-y += cpu.o

2
arch/arm/mach-zynqmp/clk.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-zynqmp/cpu.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-zynqmp/handoff.c
View file

@ -2,7 +2,7 @@
/* /*
* Copyright 2016 - 2017 Xilinx, Inc. * Copyright 2016 - 2017 Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-zynqmp/include/mach/clk.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#ifndef _ASM_ARCH_CLK_H_ #ifndef _ASM_ARCH_CLK_H_

2
arch/arm/mach-zynqmp/include/mach/hardware.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#ifndef _ASM_ARCH_HARDWARE_H #ifndef _ASM_ARCH_HARDWARE_H

2
arch/arm/mach-zynqmp/include/mach/sys_proto.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#ifndef _ASM_ARCH_SYS_PROTO_H #ifndef _ASM_ARCH_SYS_PROTO_H

2
arch/arm/mach-zynqmp/mp.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/arm/mach-zynqmp/psu_spl_init.c
View file

@ -2,7 +2,7 @@
/* /*
* Copyright 2018 Xilinx, Inc. * Copyright 2018 Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>

2
arch/arm/mach-zynqmp/spl.c
View file

@ -2,7 +2,7 @@
/* /*
* Copyright 2015 - 2016 Xilinx, Inc. * Copyright 2015 - 2016 Xilinx, Inc.
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/microblaze/cpu/spl.c
View file

@ -2,7 +2,7 @@
/* /*
* (C) Copyright 2013 - 2014 Xilinx, Inc * (C) Copyright 2013 - 2014 Xilinx, Inc
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
arch/microblaze/cpu/u-boot-spl.lds
View file

@ -2,7 +2,7 @@
/* /*
* (C) Copyright 2013 - 2014 Xilinx, Inc * (C) Copyright 2013 - 2014 Xilinx, Inc
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <asm-offsets.h> #include <asm-offsets.h>

2
arch/microblaze/include/asm/spl.h
View file

@ -2,7 +2,7 @@
/* /*
* (C) Copyright 2013 - 2014 Xilinx, Inc * (C) Copyright 2013 - 2014 Xilinx, Inc
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#ifndef _ASM_MICROBLAZE_SPL_H_ #ifndef _ASM_MICROBLAZE_SPL_H_

2
board/xilinx/common/Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
# #
# (C) Copyright 2020 Xilinx, Inc. # (C) Copyright 2020 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com> # Michal Simek <michal.simek@amd.com>
# #
obj-y += board.o obj-y += board.o

2
board/xilinx/common/board.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
/* /*
* (C) Copyright 2020 Xilinx, Inc. * (C) Copyright 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#ifndef _BOARD_XILINX_COMMON_BOARD_H #ifndef _BOARD_XILINX_COMMON_BOARD_H

2
board/xilinx/common/cpu-info.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2020 Xilinx, Inc. * (C) Copyright 2014 - 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
board/xilinx/common/fru.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */ /* SPDX-License-Identifier: GPL-2.0+ */
/* /*
* (C) Copyright 2019 Xilinx, Inc. * (C) Copyright 2019 Xilinx, Inc.
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#ifndef __FRU_H #ifndef __FRU_H

2
board/xilinx/versal/Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
# (C) Copyright 2016 - 2018 Xilinx, Inc. # (C) Copyright 2016 - 2018 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com> # Michal Simek <michal.simek@amd.com>
# #
obj-y := board.o obj-y := board.o

2
board/xilinx/versal/board.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2018 Xilinx, Inc. * (C) Copyright 2014 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <command.h> #include <command.h>

2
board/xilinx/versal/cmds.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* (C) Copyright 2020 Xilinx, Inc. * (C) Copyright 2020 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <cpu_func.h> #include <cpu_func.h>

2
board/xilinx/zynqmp/Makefile
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
# (C) Copyright 2014 - 2016 Xilinx, Inc. # (C) Copyright 2014 - 2016 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com> # Michal Simek <michal.simek@amd.com>
obj-y := zynqmp.o obj-y := zynqmp.o

2
board/xilinx/zynqmp/cmds.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* (C) Copyright 2018 Xilinx, Inc. * (C) Copyright 2018 Xilinx, Inc.
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#include <common.h> #include <common.h>

2
board/xilinx/zynqmp/zynqmp.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>

2
common/spl/spl_ram.c
View file

@ -6,7 +6,7 @@
* (C) Copyright 2016 * (C) Copyright 2016
* Toradex AG * Toradex AG
* *
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Stefan Agner <stefan.agner@toradex.com> * Stefan Agner <stefan.agner@toradex.com>
*/ */
#include <common.h> #include <common.h>

2
drivers/ata/sata_ceva.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2015 - 2016 Xilinx, Inc. * (C) Copyright 2015 - 2016 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>

2
drivers/clk/clk_versal.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2019 Xilinx, Inc. * (C) Copyright 2019 Xilinx, Inc.
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#include <common.h> #include <common.h>

2
drivers/fpga/versalpl.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* (C) Copyright 2019, Xilinx, Inc, * (C) Copyright 2019, Xilinx, Inc,
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#include <common.h> #include <common.h>

4
drivers/fpga/zynqmppl.c
View file

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* (C) Copyright 2015 - 2016, Xilinx, Inc, * (C) Copyright 2015 - 2016, Xilinx, Inc,
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
*/ */
#include <console.h> #include <console.h>

2
drivers/net/xilinx_axi_mrmac.c
View file

@ -3,7 +3,7 @@
* Xilinx Multirate Ethernet MAC(MRMAC) driver * Xilinx Multirate Ethernet MAC(MRMAC) driver
* *
* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* Copyright (C) 2021 Xilinx, Inc. All rights reserved. * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
*/ */

2
drivers/net/xilinx_axi_mrmac.h
View file

@ -3,7 +3,7 @@
* Xilinx Multirate Ethernet MAC(MRMAC) driver * Xilinx Multirate Ethernet MAC(MRMAC) driver
* *
* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* Copyright (C) 2021 Xilinx, Inc. All rights reserved. * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
*/ */

2
drivers/pinctrl/pinctrl-zynqmp.c
View file

@ -3,7 +3,7 @@
* Xilinx pinctrl driver for ZynqMP * Xilinx pinctrl driver for ZynqMP
* *
* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* Copyright (C) 2021 Xilinx, Inc. All rights reserved. * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
*/ */

2
drivers/soc/soc_xilinx_zynqmp.c
View file

@ -3,7 +3,7 @@
* Xilinx ZynqMP SOC driver * Xilinx ZynqMP SOC driver
* *
* Copyright (C) 2021 Xilinx, Inc. * Copyright (C) 2021 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>

2
drivers/watchdog/xilinx_tb_wdt.c
View file

@ -2,7 +2,7 @@
/* /*
* Xilinx AXI platforms watchdog timer driver. * Xilinx AXI platforms watchdog timer driver.
* *
* Author(s): Michal Simek <michal.simek@xilinx.com> * Author(s): Michal Simek <michal.simek@amd.com>
* Shreenidhi Shedi <yesshedi@gmail.com> * Shreenidhi Shedi <yesshedi@gmail.com>
* *
* Copyright (c) 2011-2018 Xilinx Inc. * Copyright (c) 2011-2018 Xilinx Inc.

2
drivers/watchdog/xilinx_wwdt.c
View file

@ -2,7 +2,7 @@
/* /*
* Xilinx window watchdog timer driver. * Xilinx window watchdog timer driver.
* *
* Author(s): Michal Simek <michal.simek@xilinx.com> * Author(s): Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> * Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
* *
* Copyright (c) 2020, Xilinx Inc. * Copyright (c) 2020, Xilinx Inc.

2
include/configs/xilinx_versal.h
View file

@ -2,7 +2,7 @@
/* /*
* Configuration for Xilinx Versal * Configuration for Xilinx Versal
* (C) Copyright 2016 - 2018 Xilinx, Inc. * (C) Copyright 2016 - 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* Based on Configuration for Xilinx ZynqMP * Based on Configuration for Xilinx ZynqMP
*/ */

4
include/configs/xilinx_versal_mini.h
View file

@ -3,8 +3,8 @@
* Configuration for Xilinx Versal MINI configuration * Configuration for Xilinx Versal MINI configuration
* *
* (C) Copyright 2018-2019 Xilinx, Inc. * (C) Copyright 2018-2019 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#ifndef __CONFIG_VERSAL_MINI_H #ifndef __CONFIG_VERSAL_MINI_H

2
include/configs/xilinx_zynqmp.h
View file

@ -2,7 +2,7 @@
/* /*
* Configuration for Xilinx ZynqMP * Configuration for Xilinx ZynqMP
* (C) Copyright 2014 - 2015 Xilinx, Inc. * (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* *
* Based on Configuration for Versatile Express * Based on Configuration for Versatile Express
*/ */

4
include/configs/xilinx_zynqmp_mini.h
View file

@ -3,8 +3,8 @@
* Configuration for Xilinx ZynqMP Flash utility * Configuration for Xilinx ZynqMP Flash utility
* *
* (C) Copyright 2018 Xilinx, Inc. * (C) Copyright 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#ifndef __CONFIG_ZYNQMP_MINI_H #ifndef __CONFIG_ZYNQMP_MINI_H

4
include/configs/xilinx_zynqmp_mini_nand.h
View file

@ -3,8 +3,8 @@
* Configuration for Xilinx ZynqMP Nand Flash utility * Configuration for Xilinx ZynqMP Nand Flash utility
* *
* (C) Copyright 2018 Xilinx, Inc. * (C) Copyright 2018 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#ifndef __CONFIG_ZYNQMP_MINI_NAND_H #ifndef __CONFIG_ZYNQMP_MINI_NAND_H

2
include/versalpl.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
/* /*
* (C) Copyright 2019 Xilinx, Inc, * (C) Copyright 2019 Xilinx, Inc,
* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
*/ */
#ifndef _VERSALPL_H_ #ifndef _VERSALPL_H_

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include/zynqmppl.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
/* /*
* (C) Copyright 2015 Xilinx, Inc, * (C) Copyright 2015 Xilinx, Inc,
* Michal Simek <michal.simek@xilinx.com> * Michal Simek <michal.simek@amd.com>
*/ */
#ifndef _ZYNQMPPL_H_ #ifndef _ZYNQMPPL_H_

2
tools/zynqmp_psu_init_minimize.sh
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@ -1,6 +1,6 @@
#!/bin/bash #!/bin/bash
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2018 Michal Simek <michal.simek@xilinx.com> # Copyright (C) 2018 Michal Simek <michal.simek@amd.com>
# Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net> # Copyright (C) 2019 Luca Ceresoli <luca@lucaceresoli.net>
# Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG # Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
# Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> # Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>

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tools/zynqmpimage.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* Copyright (C) 2016 Michal Simek <michals@xilinx.com> * Copyright (C) 2016 Michal Simek <michal.simek@amd.com>
* Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com> * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
* *
* The following Boot Header format/structures and values are defined in the * The following Boot Header format/structures and values are defined in the

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