Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-19 19:34:35 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

board: rockchip: Add the Turing RK1 SoM

Browse source 
The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.

Specifications:

    Rockchip RK3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    8/16/32GB memory LPDDR4x
    Mali G610MC4 GPU
    32GB eMMC HS400
    2x USB 2.0, 2x USB 3.0
    2x MIPI CSI 4x lanes
    1x MIPI-DSI DPHY 2x lanes
    PCIe 2.0 x1, PCIe 3.0 x4
    1x HDMI 2.1 output, 1x DP 1.4 output
    Gigabit Ethernet
    Size: 69.6mm x 45mm (260-pin SO-DIMM connector)

Kernel commit:
2806a69f3fef ("arm64: dts: rockchip: Add Turing RK1 SoM support")

Signed-off-by: Joshua Riek <jjriek@verizon.net>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Joshua Riek 2024-01-09 20:30:24 -05:00 • committed by Kever Yang
parent 595a7184e5
commit 153ac950a5
12 changed files with 903 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/dts/Makefile
View file

@ -196,6 +196,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
rk3588-turing-rk1.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb

25
arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Joshua Riek <jjriek@verizon.net>
*
*/
#include "rk3588-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
};
};
&sdhci {
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
};
&uart9 {
bootph-pre-ram;
clock-frequency = <24000000>;
status = "okay";
};

21
arch/arm/dts/rk3588-turing-rk1.dts Normal file
View file

@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* This device tree covers the common case where the RK1 is used as a
* "compute node" system, where the carrier board is functioning more like a
* generic backplane (with no non-autoenumerable peripherals of its own) than
* like a device that the SoM is meant to enable.
*
* Copyright (c) 2023 Sam Edwards <CFSworks@gmail.com>
*/
/dts-v1/;
#include "rk3588-turing-rk1.dtsi"
/ {
model = "Turing Machines RK1";
compatible = "turing,rk1", "rockchip,rk3588";
chosen {
stdout-path = "serial9:115200n8";
};
};

614
arch/arm/dts/rk3588-turing-rk1.dtsi Normal file
View file

@ -0,0 +1,614 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device tree definitions for the Turing RK1 SoM.
*
* Copyright (c) 2023 Sam Edwards <CFSworks@gmail.com>
*
* Based on RK3588-EVB1 devicetree
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3588.dtsi"
/ {
compatible = "turing,rk1", "rockchip,rk3588";
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
serial2 = &uart2;
serial9 = &uart9;
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 25 95 145 195 255>;
fan-supply = <&vcc5v0_sys>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0m2_pins &fan_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
pwms = <&pwm0 0 50000 0>;
#cooling-cells = <2>;
};
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie30_en>;
startup-delay-us = <5000>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy2_psu {
status = "okay";
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&gmac1 {
clock_in_out = "output";
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii-rxid";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
pinctrl-names = "default";
rx_delay = <0x00>;
tx_delay = <0x43>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big0_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";
reg = <0x43>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_big1_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1m2_xfer>;
status = "okay";
vdd_npu_s0: regulator@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c6 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&mdio1 {
rgmii_phy: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;
reset-assert-us = <15000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
&pcie2x1l1 {
linux,pci-domain = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_reset>;
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
status = "okay";
};
&pcie3x4 {
linux,pci-domain = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie3_reset>;
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
status = "okay";
};
&pinctrl {
fan {
fan_int: fan-int {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie2 {
pcie2_reset: pcie2-reset {
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie3 {
pcie3_reset: pcie3-reset {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc3v3_pcie30_en: pcie3-reg {
rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
rtl8211f {
rtl8211f_rst: rtl8211f-rst {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&spi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
num-cs = <1>;
pmic@0 {
compatible = "rockchip,rk806";
spi-max-frequency = <1000000>;
reg = <0x0>;
interrupt-parent = <&gpio0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc5v0_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc5v0_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc5v0_sys>;
gpio-controller;
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
regulators {
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_log_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_log_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <675000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vdd2_ddr_s3: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_2v0_pldo_s3: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_2v0_pldo_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2000000>;
};
};
vcc_3v3_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vddq_ddr_s0: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avcc_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "avcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
avdd_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "avdd_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vcc_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12500>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdd_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
avdd_0v75_s0: nldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "avdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdd_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";
};
&uart9 {
pinctrl-0 = <&uart9m0_xfer>;
status = "okay";
};

24
arch/arm/mach-rockchip/rk3588/Kconfig
View file

@ -132,6 +132,29 @@ config TARGET_QUARTZPRO64_RK3588
Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
Computer) by Pine64.
config TARGET_TURINGRK1_RK3588
bool "Turing Machines RK1 RK3588 board"
select BOARD_LATE_INIT
help
The Turing RK1 is a Rockchip RK3588 based SoM from Turing Machines.
There are three variants depending on the DRAM size : 8G, 16G and 32G.
Specifications:
Rockchip RK3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
8/16/32GB memory LPDDR4x
Mali G610MC4 GPU
32GB eMMC HS400
2x USB 2.0, 2x USB 3.0
2x MIPI CSI 4x lanes
1x MIPI-DSI DPHY 2x lanes
PCIe 2.0 x1, PCIe 3.0 x4
1x HDMI 2.1 output, 1x DP 1.4 output
Gigabit Ethernet
Size: 69.6mm x 45mm (260-pin SO-DIMM connector)
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
@ -147,6 +170,7 @@ config SYS_MALLOC_F_LEN
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
source board/pine64/quartzpro64-rk3588/Kconfig
source board/turing/turing-rk1-rk3588/Kconfig
source board/rockchip/evb_rk3588/Kconfig
source board/radxa/rock5a-rk3588s/Kconfig
source board/radxa/rock5b-rk3588/Kconfig

15
board/turing/turing-rk1-rk3588/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_TURINGRK1_RK3588
config SYS_BOARD
default "turing-rk1-rk3588"
config SYS_VENDOR
default "turing"
config SYS_CONFIG_NAME
default "turing-rk1-rk3588"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

9
board/turing/turing-rk1-rk3588/MAINTAINERS Normal file
View file

@ -0,0 +1,9 @@
TURINGRK1-RK3588
M: Joshua Riek <jjriek@verizon.net>
S: Maintained
F: board/turing/turing-rk1-rk3588
F: include/configs/turing-rk1-rk3588.h
F: configs/turing-rk1-rk3588_defconfig
F: arch/arm/dts/rk3588-turing-rk1.dts
F: arch/arm/dts/rk3588-turing-rk1.dtsi
F: arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi

6
board/turing/turing-rk1-rk3588/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
#
obj-y += turing-rk1-rk3588.o

39
board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c Normal file
View file

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
*/
#include <fdtdec.h>
#include <fdt_support.h>
#ifdef CONFIG_OF_BOARD_SETUP
int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
{
struct fdt_memory gap1 = {
.start = 0x3fc000000,
.end = 0x3fc4fffff,
};
struct fdt_memory gap2 = {
.start = 0x3fff00000,
.end = 0x3ffffffff,
};
unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
unsigned int ret;
/*
* Inject the reserved-memory nodes into the DTS
*/
ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
NULL, flags);
if (ret)
return ret;
return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
NULL, flags);
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
return turing_rk1_add_reserved_memory_fdt_nodes(blob);
}
#endif

133
configs/turing-rk1-rk3588_defconfig Normal file
View file

@ -0,0 +1,133 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_TURINGRK1_RK3588=y
CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEBC0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_SCSI=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_ROCKUSB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TFTPSRV=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SPL_CLK=y
# CONFIG_USB_FUNCTION_FASTBOOT is not set
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=5
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_PHYLIB=y
CONFIG_RTL8169=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_PHY_ROCKCHIP_USBDP=y
CONFIG_SPL_PINCTRL=y
CONFIG_PHY_REALTEK=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
CONFIG_REGULATOR_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_BAUDRATE=115200
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_XHCI_PCI=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x350b
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_ERRNO_STR=y

1
doc/board/rockchip/rockchip.rst
View file

@ -117,6 +117,7 @@ List of mainline supported Rockchip boards:
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- Turing Machines RK1 (turing-rk1-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)

15
include/configs/turing-rk1-rk3588.h Normal file
View file

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#ifndef __TURINGRK1_RK3588_H
#define __TURINGRK1_RK3588_H
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3588_common.h>
#endif /* __TURINGRK1_RK3588_H */