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drivers: ddr: Remove duplicate newlines
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
Tom Rini
parent
c821d05c14
commit
1528a7e562
15 changed files with 0 additions and 24 deletions
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@ -645,7 +645,6 @@ static int of_sdram_firewall_setup(const void *blob)
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writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
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writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
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for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
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sprintf(name, "%s", firewall_table[i].prop_name);
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ret = fdtdec_get_int_array(blob, child, name,
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@ -689,7 +689,6 @@ static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
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}
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}
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/* apply and load delay on both DQS and OCT out1 */
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static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
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u32 write_group, u32 delay)
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@ -2580,7 +2579,6 @@ static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
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&sticky_bit_chk,
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left_edge, right_edge, use_read_test);
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/* Search for the right edge of the window for each bit */
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ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
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start_dqs, start_dqs_en,
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@ -164,7 +164,6 @@ struct param_type {
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u32 write_correct_mask_vg;
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};
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/* global variable holder */
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struct gbl_type {
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uint32_t phy_debug_mode_flags;
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@ -19,7 +19,6 @@
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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/*
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* regs has the to-be-set values for DDR controller registers
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* ctrl_num is the DDR controller number
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@ -1209,7 +1209,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
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for (i = 0; i < 18; i++)
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printf("%c", spd->mpart[i]);
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printf("<<* 73 Manufacturer's Part Number *\n");
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printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
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@ -1227,7 +1226,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
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for (i = 0; i < 27; i++)
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printf("%02x", spd->mspec[i]);
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printf("* 99 Manufacturer Specific Data *\n");
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}
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#endif
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@ -1946,7 +1944,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
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if (argc == 0)
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continue;
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if (strcmp(argv[0], "help") == 0) {
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puts(usage);
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continue;
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@ -2042,7 +2039,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
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debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
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src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
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switch (step_mask) {
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case STEP_GET_SPD:
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@ -2117,7 +2113,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
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if (error)
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continue;
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/* Check arguments */
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/* ERROR: If no steps were found */
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@ -191,7 +191,6 @@ compute_cas_latency(const unsigned int ctrl_num,
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lowest_good_caslat);
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outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
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/*
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* Compute a common 'de-rated' CAS latency.
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*
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@ -78,7 +78,6 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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fsp_msg++;
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}
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@ -75,7 +75,6 @@ int ddr3_init(void)
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#endif
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}
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status = ddr3_silicon_post_init();
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if (MV_OK != status) {
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printf("DDR3 Post Init - FAILED 0x%x\n", status);
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@ -89,7 +88,6 @@ int ddr3_init(void)
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return status;
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}
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/* Post MC/PHY initializations */
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mv_ddr_post_training_soc_config(ddr_type);
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@ -285,7 +285,6 @@ int ddr3_tip_tune_training_params(u32 dev_num,
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if (params->g_rtt_park != PARAM_UNDEFINED)
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g_rtt_park = params->g_rtt_park;
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DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
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("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
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g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
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@ -870,7 +869,6 @@ int ddr3_tip_validate_algo_components(u8 dev_num)
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return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
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}
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int ddr3_pre_algo_config(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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@ -1114,7 +1112,6 @@ int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
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mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
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}
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/*
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* Phy read-modify-write
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*/
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@ -1406,7 +1403,6 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
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t2t = (cs_num == 1) ? 0 : 1;
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}
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if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
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/* Use 1T mode if 1:1 ratio configured */
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if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
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@ -82,7 +82,6 @@
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#define ADDR_SIZE_8GB 0x40000000
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#define ADDR_SIZE_16GB 0x80000000
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enum hws_edge_compare {
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EDGE_PF,
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EDGE_FP,
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@ -1677,7 +1677,6 @@ static int mpr_rd_frmt_config(
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u32 val, mask;
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u8 cs_bitmask_inv;
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if (dis_auto_refresh == 1) {
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ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG,
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ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS,
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@ -79,7 +79,6 @@
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#define MV_DEBUG_WL_FULL
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#endif
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/* The following is a list of Marvell status */
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#define MV_ERROR (-1)
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#define MV_OK (0x00) /* Operation succeeded */
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@ -1144,7 +1144,6 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
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uint64_t cs_mem_size = 0;
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uint64_t mem_total_size_c, cs_mem_size_c;
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#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
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u32 physical_mem_size;
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u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
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@ -55,7 +55,6 @@
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#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
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#define REG_DEVICE_SAR1_ADDR 0xe4204
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
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@ -520,5 +520,4 @@ enum {
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#define RESULT_PHY_RX_OFFS 5
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#define RESULT_PHY_TX_OFFS 0
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#endif /* _MV_DDR_REGS_H */
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