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drivers: ddr: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2024-07-20 14:40:33 +02:00 • committed by Tom Rini
parent c821d05c14
commit 1528a7e562
15 changed files with 0 additions and 24 deletions
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1
drivers/ddr/altera/sdram_arria10.c
View file

@ -645,7 +645,6 @@ static int of_sdram_firewall_setup(const void *blob)
writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable); writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
writel(0, &socfpga_noc_fw_ddr_l3_base->enable); writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
for (i = 0; i < ARRAY_SIZE(firewall_table); i++) { for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
sprintf(name, "%s", firewall_table[i].prop_name); sprintf(name, "%s", firewall_table[i].prop_name);
ret = fdtdec_get_int_array(blob, child, name, ret = fdtdec_get_int_array(blob, child, name,

2
drivers/ddr/altera/sequencer.c
View file

@ -689,7 +689,6 @@ static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
} }
} }
/* apply and load delay on both DQS and OCT out1 */ /* apply and load delay on both DQS and OCT out1 */
static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq, static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
u32 write_group, u32 delay) u32 write_group, u32 delay)
@ -2580,7 +2579,6 @@ static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
&sticky_bit_chk, &sticky_bit_chk,
left_edge, right_edge, use_read_test); left_edge, right_edge, use_read_test);
/* Search for the right edge of the window for each bit */ /* Search for the right edge of the window for each bit */
ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group, ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
start_dqs, start_dqs_en, start_dqs, start_dqs_en,

1
drivers/ddr/altera/sequencer.h
View file

@ -164,7 +164,6 @@ struct param_type {
u32 write_correct_mask_vg; u32 write_correct_mask_vg;
}; };
/* global variable holder */ /* global variable holder */
struct gbl_type { struct gbl_type {
uint32_t phy_debug_mode_flags; uint32_t phy_debug_mode_flags;

1
drivers/ddr/fsl/arm_ddr_gen3.c
View file

@ -19,7 +19,6 @@
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif #endif
/* /*
* regs has the to-be-set values for DDR controller registers * regs has the to-be-set values for DDR controller registers
* ctrl_num is the DDR controller number * ctrl_num is the DDR controller number

5
drivers/ddr/fsl/interactive.c
View file

@ -1209,7 +1209,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
for (i = 0; i < 18; i++) for (i = 0; i < 18; i++)
printf("%c", spd->mpart[i]); printf("%c", spd->mpart[i]);
printf("<<* 73 Manufacturer's Part Number *\n"); printf("<<* 73 Manufacturer's Part Number *\n");
printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
@ -1227,7 +1226,6 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
for (i = 0; i < 27; i++) for (i = 0; i < 27; i++)
printf("%02x", spd->mspec[i]); printf("%02x", spd->mspec[i]);
printf("* 99 Manufacturer Specific Data *\n"); printf("* 99 Manufacturer Specific Data *\n");
} }
#endif #endif
@ -1946,7 +1944,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
if (argc == 0) if (argc == 0)
continue; continue;
if (strcmp(argv[0], "help") == 0) { if (strcmp(argv[0], "help") == 0) {
puts(usage); puts(usage);
continue; continue;
@ -2042,7 +2039,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
switch (step_mask) { switch (step_mask) {
case STEP_GET_SPD: case STEP_GET_SPD:
@ -2117,7 +2113,6 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
if (error) if (error)
continue; continue;
/* Check arguments */ /* Check arguments */
/* ERROR: If no steps were found */ /* ERROR: If no steps were found */

1
drivers/ddr/fsl/lc_common_dimm_params.c
View file

@ -191,7 +191,6 @@ compute_cas_latency(const unsigned int ctrl_num,
lowest_good_caslat); lowest_good_caslat);
outpdimm->lowest_common_spd_caslat = lowest_good_caslat; outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
/* /*
* Compute a common 'de-rated' CAS latency. * Compute a common 'de-rated' CAS latency.
* *

1
drivers/ddr/imx/phy/ddrphy_train.c
View file

@ -78,7 +78,6 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
dwc_ddrphy_apb_wr(0xd0000, 0x1); dwc_ddrphy_apb_wr(0xd0000, 0x1);
fsp_msg++; fsp_msg++;
} }

2
drivers/ddr/marvell/a38x/ddr3_init.c
View file

@ -75,7 +75,6 @@ int ddr3_init(void)
#endif #endif
} }
status = ddr3_silicon_post_init(); status = ddr3_silicon_post_init();
if (MV_OK != status) { if (MV_OK != status) {
printf("DDR3 Post Init - FAILED 0x%x\n", status); printf("DDR3 Post Init - FAILED 0x%x\n", status);
@ -89,7 +88,6 @@ int ddr3_init(void)
return status; return status;
} }
/* Post MC/PHY initializations */ /* Post MC/PHY initializations */
mv_ddr_post_training_soc_config(ddr_type); mv_ddr_post_training_soc_config(ddr_type);

4
drivers/ddr/marvell/a38x/ddr3_training.c
View file

@ -285,7 +285,6 @@ int ddr3_tip_tune_training_params(u32 dev_num,
if (params->g_rtt_park != PARAM_UNDEFINED) if (params->g_rtt_park != PARAM_UNDEFINED)
g_rtt_park = params->g_rtt_park; g_rtt_park = params->g_rtt_park;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n", ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data, g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
@ -870,7 +869,6 @@ int ddr3_tip_validate_algo_components(u8 dev_num)
return (status == 1) ? MV_OK : MV_NOT_INITIALIZED; return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
} }
int ddr3_pre_algo_config(void) int ddr3_pre_algo_config(void)
{ {
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
@ -1114,7 +1112,6 @@ int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE); mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
} }
/* /*
* Phy read-modify-write * Phy read-modify-write
*/ */
@ -1406,7 +1403,6 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
t2t = (cs_num == 1) ? 0 : 1; t2t = (cs_num == 1) ? 0 : 1;
} }
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) { if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
/* Use 1T mode if 1:1 ratio configured */ /* Use 1T mode if 1:1 ratio configured */
if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) { if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {

1
drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
View file

@ -82,7 +82,6 @@
#define ADDR_SIZE_8GB 0x40000000 #define ADDR_SIZE_8GB 0x40000000
#define ADDR_SIZE_16GB 0x80000000 #define ADDR_SIZE_16GB 0x80000000
enum hws_edge_compare { enum hws_edge_compare {
EDGE_PF, EDGE_PF,
EDGE_FP, EDGE_FP,

1
drivers/ddr/marvell/a38x/ddr3_training_leveling.c
View file

@ -1677,7 +1677,6 @@ static int mpr_rd_frmt_config(
u32 val, mask; u32 val, mask;
u8 cs_bitmask_inv; u8 cs_bitmask_inv;
if (dis_auto_refresh == 1) { if (dis_auto_refresh == 1) {
ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG, ddr3_tip_if_write(0, ACCESS_TYPE_UNICAST, 0, ODPG_CTRL_CTRL_REG,
ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS, ODPG_CTRL_AUTO_REFRESH_DIS << ODPG_CTRL_AUTO_REFRESH_OFFS,

1
drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
View file

@ -79,7 +79,6 @@
#define MV_DEBUG_WL_FULL #define MV_DEBUG_WL_FULL
#endif #endif
/* The following is a list of Marvell status */ /* The following is a list of Marvell status */
#define MV_ERROR (-1) #define MV_ERROR (-1)
#define MV_OK (0x00) /* Operation succeeded */ #define MV_OK (0x00) /* Operation succeeded */

1
drivers/ddr/marvell/a38x/mv_ddr_plat.c
View file

@ -1144,7 +1144,6 @@ static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
uint64_t cs_mem_size = 0; uint64_t cs_mem_size = 0;
uint64_t mem_total_size_c, cs_mem_size_c; uint64_t mem_total_size_c, cs_mem_size_c;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
u32 physical_mem_size; u32 physical_mem_size;
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE; u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;

1
drivers/ddr/marvell/a38x/mv_ddr_plat.h
View file

@ -55,7 +55,6 @@
#define MARVELL_BOARD MARVELL_BOARD_ID_BASE #define MARVELL_BOARD MARVELL_BOARD_ID_BASE
#define REG_DEVICE_SAR1_ADDR 0xe4204 #define REG_DEVICE_SAR1_ADDR 0xe4204
#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f

1
drivers/ddr/marvell/a38x/mv_ddr_regs.h
View file

@ -520,5 +520,4 @@ enum {
#define RESULT_PHY_RX_OFFS 5 #define RESULT_PHY_RX_OFFS 5
#define RESULT_PHY_TX_OFFS 0 #define RESULT_PHY_TX_OFFS 0
#endif /* _MV_DDR_REGS_H */ #endif /* _MV_DDR_REGS_H */