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arm: Remove flea3 board
This board has not been converted to CONFIG_DM by the deadline. Remove it. As this is the last mx35 platform, remove that support as well. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Tom Rini
parent
570320da3b
commit
14b38cb0c2
29 changed files with 7 additions and 3435 deletions
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@ -605,11 +605,6 @@ config TARGET_STV0991
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select SPI_FLASH
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imply CMD_DM
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config TARGET_FLEA3
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bool "Support flea3"
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select CPU_ARM1136
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select GPIO_EXTRA_HEADER
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config ARCH_BCM283X
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bool "Broadcom BCM283X family"
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select DM
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@ -2149,7 +2144,6 @@ source "board/armltd/total_compute/Kconfig"
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source "board/bosch/shc/Kconfig"
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source "board/bosch/guardian/Kconfig"
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source "board/CarMediaLab/flea3/Kconfig"
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source "board/Marvell/aspenite/Kconfig"
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source "board/Marvell/octeontx/Kconfig"
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source "board/Marvell/octeontx2/Kconfig"
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@ -111,7 +111,7 @@ libs-y += arch/arm/cpu/
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libs-y += arch/arm/lib/
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ifeq ($(CONFIG_SPL_BUILD),y)
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ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
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ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
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libs-y += arch/arm/mach-imx/
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endif
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else
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@ -7,4 +7,3 @@ extra-y = start.o
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obj-y += ../arm11/
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obj-$(CONFIG_MX31) += mx31/
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obj-$(CONFIG_MX35) += mx35/
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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obj-y += generic.o
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obj-y += timer.o
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obj-y += mx35_sdram.o
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obj-y += relocate.o
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@ -1,530 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <command.h>
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#include <div64.h>
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#include <init.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#ifdef CONFIG_FSL_ESDHC_IMX
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#include <fsl_esdhc_imx.h>
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#endif
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#include <netdev.h>
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#include <spl.h>
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#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
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#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
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#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
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#define CLK_CODE_PATH(c) ((c) & 0xFF)
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#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
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#ifdef CONFIG_FSL_ESDHC_IMX
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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static int g_clk_mux_auto[8] = {
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CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
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CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
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};
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static int g_clk_mux_consumer[16] = {
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CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
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-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
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CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
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-1, -1, CLK_CODE(4, 2, 0), -1,
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};
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static int hsp_div_table[3][16] = {
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{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
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{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
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{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
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};
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u32 get_cpu_rev(void)
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{
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int reg;
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struct iim_regs *iim =
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(struct iim_regs *)IIM_BASE_ADDR;
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reg = readl(&iim->iim_srev);
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if (!reg) {
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reg = readw(ROMPATCH_REV);
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reg <<= 4;
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} else {
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reg += CHIP_REV_1_0;
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}
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return 0x35000 + (reg & 0xFF);
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}
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static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
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{
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int *pclk_mux;
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
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pclk_mux = g_clk_mux_consumer +
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
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} else {
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pclk_mux = g_clk_mux_auto +
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((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
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MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
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}
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if ((*pclk_mux) == -1)
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return -1;
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if (fi && fd) {
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if (!CLK_CODE_PATH(*pclk_mux)) {
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*fi = *fd = 1;
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return CLK_CODE_ARM(*pclk_mux);
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}
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
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*fi = 3;
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*fd = 4;
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} else {
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*fi = 2;
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*fd = 3;
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}
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}
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return CLK_CODE_ARM(*pclk_mux);
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}
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static int get_ahb_div(u32 pdr0)
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{
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int *pclk_mux;
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pclk_mux = g_clk_mux_consumer +
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
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if ((*pclk_mux) == -1)
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return -1;
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return CLK_CODE_AHB(*pclk_mux);
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}
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static u32 decode_pll(u32 reg, u32 infreq)
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{
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u32 mfi = (reg >> 10) & 0xf;
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s32 mfn = reg & 0x3ff;
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u32 mfd = (reg >> 16) & 0x3ff;
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u32 pd = (reg >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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mfn = mfn >= 512 ? mfn - 1024 : mfn;
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mfd += 1;
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pd += 1;
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return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
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mfd * pd);
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}
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static u32 get_mcu_main_clk(void)
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{
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u32 arm_div = 0, fi = 0, fd = 0;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
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fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
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return fi / (arm_div * fd);
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}
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static u32 get_ipg_clk(void)
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{
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u32 freq = get_mcu_main_clk();
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 pdr0 = readl(&ccm->pdr0);
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return freq / (get_ahb_div(pdr0) * 2);
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}
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static u32 get_ipg_per_clk(void)
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{
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u32 freq = get_mcu_main_clk();
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 pdr0 = readl(&ccm->pdr0);
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u32 pdr4 = readl(&ccm->pdr4);
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u32 div;
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if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
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div = CCM_GET_DIVIDER(pdr4,
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MXC_CCM_PDR4_PER0_PODF_MASK,
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
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} else {
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div = CCM_GET_DIVIDER(pdr0,
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MXC_CCM_PDR0_PER_PODF_MASK,
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MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
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div *= get_ahb_div(pdr0);
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}
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return freq / div;
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}
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u32 imx_get_uartclk(void)
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{
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u32 freq;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 pdr4 = readl(&ccm->pdr4);
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if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
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freq = get_mcu_main_clk();
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else
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freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
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freq /= CCM_GET_DIVIDER(pdr4,
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MXC_CCM_PDR4_UART_PODF_MASK,
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MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
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return freq;
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}
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unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
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{
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u32 nfc_pdf, hsp_podf;
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u32 pll, ret_val = 0, usb_podf;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 reg = readl(&ccm->pdr0);
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u32 reg4 = readl(&ccm->pdr4);
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reg |= 0x1;
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switch (clk) {
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case CPU_CLK:
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ret_val = get_mcu_main_clk();
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break;
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case AHB_CLK:
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ret_val = get_mcu_main_clk();
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break;
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case HSP_CLK:
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if (reg & CLKMODE_CONSUMER) {
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hsp_podf = (reg >> 20) & 0x3;
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pll = get_mcu_main_clk();
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hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
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if (hsp_podf > 0) {
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ret_val = pll / hsp_podf;
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} else {
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puts("mismatch HSP with ARM clock setting\n");
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ret_val = 0;
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}
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} else {
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ret_val = get_mcu_main_clk();
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}
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break;
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case IPG_CLK:
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ret_val = get_ipg_clk();
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break;
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case IPG_PER_CLK:
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ret_val = get_ipg_per_clk();
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break;
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case NFC_CLK:
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nfc_pdf = (reg4 >> 28) & 0xF;
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pll = get_mcu_main_clk();
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/* AHB/nfc_pdf */
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ret_val = pll / (nfc_pdf + 1);
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break;
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case USB_CLK:
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usb_podf = (reg4 >> 22) & 0x3F;
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if (reg4 & 0x200)
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pll = get_mcu_main_clk();
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else
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pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
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ret_val = pll / (usb_podf + 1);
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break;
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default:
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printf("Unknown clock: %d\n", clk);
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break;
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}
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return ret_val;
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}
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unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
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{
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u32 ret_val = 0, pdf, pre_pdf, clk_sel;
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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u32 mpdr2 = readl(&ccm->pdr2);
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u32 mpdr3 = readl(&ccm->pdr3);
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u32 mpdr4 = readl(&ccm->pdr4);
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switch (clk) {
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case UART1_BAUD:
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case UART2_BAUD:
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case UART3_BAUD:
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clk_sel = mpdr3 & (1 << 14);
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pdf = (mpdr4 >> 10) & 0x3F;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
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break;
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case SSI1_BAUD:
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pre_pdf = (mpdr2 >> 24) & 0x7;
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pdf = mpdr2 & 0x3F;
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clk_sel = mpdr2 & (1 << 6);
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case SSI2_BAUD:
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pre_pdf = (mpdr2 >> 27) & 0x7;
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pdf = (mpdr2 >> 8) & 0x3F;
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clk_sel = mpdr2 & (1 << 6);
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case CSI_BAUD:
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clk_sel = mpdr2 & (1 << 7);
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pdf = (mpdr2 >> 16) & 0x3F;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
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break;
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case MSHC_CLK:
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pre_pdf = readl(&ccm->pdr1);
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clk_sel = (pre_pdf & 0x80);
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pdf = (pre_pdf >> 22) & 0x3F;
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pre_pdf = (pre_pdf >> 28) & 0x7;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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case ESDHC1_CLK:
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clk_sel = mpdr3 & 0x40;
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pdf = mpdr3 & 0x3F;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
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break;
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case ESDHC2_CLK:
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clk_sel = mpdr3 & 0x40;
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pdf = (mpdr3 >> 8) & 0x3F;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
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break;
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case ESDHC3_CLK:
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clk_sel = mpdr3 & 0x40;
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pdf = (mpdr3 >> 16) & 0x3F;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
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break;
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case SPDIF_CLK:
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clk_sel = mpdr3 & 0x400000;
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pre_pdf = (mpdr3 >> 29) & 0x7;
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pdf = (mpdr3 >> 23) & 0x3F;
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
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decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
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((pre_pdf + 1) * (pdf + 1));
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break;
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default:
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printf("%s(): This clock: %d not supported yet\n",
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__func__, clk);
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break;
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}
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return ret_val;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_AHB_CLK:
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break;
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_IPG_PERCLK:
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case MXC_I2C_CLK:
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return get_ipg_per_clk();
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case MXC_UART_CLK:
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return imx_get_uartclk();
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case MXC_ESDHC1_CLK:
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return mxc_get_peri_clock(ESDHC1_CLK);
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case MXC_ESDHC2_CLK:
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return mxc_get_peri_clock(ESDHC2_CLK);
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case MXC_ESDHC3_CLK:
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return mxc_get_peri_clock(ESDHC3_CLK);
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case MXC_USB_CLK:
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return mxc_get_main_clock(USB_CLK);
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case MXC_FEC_CLK:
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return get_ipg_clk();
|
||||
case MXC_CSPI_CLK:
|
||||
return get_ipg_clk();
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
/*
|
||||
* The MX35 has no fuse for MAC, return a NULL MAC
|
||||
*/
|
||||
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
|
||||
{
|
||||
memset(mac, 0, 6);
|
||||
}
|
||||
|
||||
u32 imx_get_fecclk(void)
|
||||
{
|
||||
return mxc_get_clock(MXC_IPG_CLK);
|
||||
}
|
||||
#endif
|
||||
|
||||
int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
char *const argv[])
|
||||
{
|
||||
u32 cpufreq = get_mcu_main_clk();
|
||||
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
|
||||
printf("ipg clock : %dHz\n", get_ipg_clk());
|
||||
printf("ipg per clock : %dHz\n", get_ipg_per_clk());
|
||||
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
|
||||
"display clocks",
|
||||
""
|
||||
);
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
/* read RCSR register from CCM module */
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
|
||||
u32 cause = readl(&ccm->rcsr) & 0x0F;
|
||||
|
||||
switch (cause) {
|
||||
case 0x0000:
|
||||
return "POR";
|
||||
case 0x0002:
|
||||
return "JTAG";
|
||||
case 0x0004:
|
||||
return "RST";
|
||||
case 0x0008:
|
||||
return "WDOG";
|
||||
default:
|
||||
return "unknown reset";
|
||||
}
|
||||
}
|
||||
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
u32 srev = get_cpu_rev();
|
||||
|
||||
printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
|
||||
(srev & 0xF0) >> 4, (srev & 0x0F),
|
||||
get_mcu_main_clk() / 1000000);
|
||||
|
||||
printf("Reset cause: %s\n", get_reset_cause());
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers.
|
||||
* to override, implement board_eth_init()
|
||||
*/
|
||||
int cpu_eth_init(struct bd_info *bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
rc = fecmxc_initialize(bis);
|
||||
#endif
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
/*
|
||||
* Initializes on-chip MMC controllers.
|
||||
* to override, implement board_mmc_init()
|
||||
*/
|
||||
int cpu_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
return fsl_esdhc_mmc_init(bis);
|
||||
}
|
||||
#endif
|
||||
|
||||
int get_clocks(void)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
#else
|
||||
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
|
||||
#endif
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RCSR_MEM_CTL_WEIM 0
|
||||
#define RCSR_MEM_CTL_NAND 1
|
||||
#define RCSR_MEM_CTL_ATA 2
|
||||
#define RCSR_MEM_CTL_EXPANSION 3
|
||||
#define RCSR_MEM_TYPE_NOR 0
|
||||
#define RCSR_MEM_TYPE_ONENAND 2
|
||||
#define RCSR_MEM_TYPE_SD 0
|
||||
#define RCSR_MEM_TYPE_I2C 2
|
||||
#define RCSR_MEM_TYPE_SPI 3
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
|
||||
u32 rcsr = readl(&ccm->rcsr);
|
||||
u32 mem_type, mem_ctl;
|
||||
|
||||
/* In external mode, no boot device is returned */
|
||||
if ((rcsr >> 10) & 0x03)
|
||||
return BOOT_DEVICE_NONE;
|
||||
|
||||
mem_ctl = (rcsr >> 25) & 0x03;
|
||||
mem_type = (rcsr >> 23) & 0x03;
|
||||
|
||||
switch (mem_ctl) {
|
||||
case RCSR_MEM_CTL_WEIM:
|
||||
switch (mem_type) {
|
||||
case RCSR_MEM_TYPE_NOR:
|
||||
return BOOT_DEVICE_NOR;
|
||||
case RCSR_MEM_TYPE_ONENAND:
|
||||
return BOOT_DEVICE_ONENAND;
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
case RCSR_MEM_CTL_NAND:
|
||||
return BOOT_DEVICE_NAND;
|
||||
case RCSR_MEM_CTL_EXPANSION:
|
||||
switch (mem_type) {
|
||||
case RCSR_MEM_TYPE_SD:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
case RCSR_MEM_TYPE_I2C:
|
||||
return BOOT_DEVICE_I2C;
|
||||
case RCSR_MEM_TYPE_SPI:
|
||||
return BOOT_DEVICE_SPI;
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
#define ESDCTL_DDR2_EMR2 0x04000000
|
||||
#define ESDCTL_DDR2_EMR3 0x06000000
|
||||
#define ESDCTL_PRECHARGE 0x00000400
|
||||
#define ESDCTL_DDR2_EN_DLL 0x02000400
|
||||
#define ESDCTL_DDR2_RESET_DLL 0x00000333
|
||||
#define ESDCTL_DDR2_MR 0x00000233
|
||||
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
|
||||
|
||||
enum {
|
||||
SMODE_NORMAL = 0,
|
||||
SMODE_PRECHARGE,
|
||||
SMODE_AUTO_REFRESH,
|
||||
SMODE_LOAD_REG,
|
||||
SMODE_MANUAL_REFRESH
|
||||
};
|
||||
|
||||
#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
|
||||
|
||||
static inline void dram_wait(unsigned int count)
|
||||
{
|
||||
volatile unsigned int wait = count;
|
||||
|
||||
while (wait--)
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
|
||||
u32 row, u32 col, u32 dsize, u32 refresh)
|
||||
{
|
||||
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
|
||||
u32 *cfg_reg, *ctl_reg;
|
||||
u32 val;
|
||||
u32 ctlval;
|
||||
|
||||
switch (start_address) {
|
||||
case CSD0_BASE_ADDR:
|
||||
cfg_reg = &esdc->esdcfg0;
|
||||
ctl_reg = &esdc->esdctl0;
|
||||
break;
|
||||
case CSD1_BASE_ADDR:
|
||||
cfg_reg = &esdc->esdcfg1;
|
||||
ctl_reg = &esdc->esdctl1;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
/* The MX35 supports 11 up to 14 rows */
|
||||
if (row < 11 || row > 14 || col < 8 || col > 10)
|
||||
return;
|
||||
ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
|
||||
|
||||
/* Initialize MISC register for DDR2 */
|
||||
val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
|
||||
ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
|
||||
writel(val, &esdc->esdmisc);
|
||||
val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
|
||||
writel(val, &esdc->esdmisc);
|
||||
|
||||
/*
|
||||
* according to DDR2 specs, wait a while before
|
||||
* the PRECHARGE_ALL command
|
||||
*/
|
||||
dram_wait(0x20000);
|
||||
|
||||
/* Load DDR2 config and timing */
|
||||
writel(ddr2_config, cfg_reg);
|
||||
|
||||
/* Precharge ALL */
|
||||
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
|
||||
ctl_reg);
|
||||
writel(0xda, start_address + ESDCTL_PRECHARGE);
|
||||
|
||||
/* Load mode */
|
||||
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
|
||||
ctl_reg);
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
|
||||
|
||||
/* Precharge ALL */
|
||||
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
|
||||
ctl_reg);
|
||||
writel(0xda, start_address + ESDCTL_PRECHARGE);
|
||||
|
||||
/* Set mode auto refresh : at least two refresh are required */
|
||||
writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
|
||||
ctl_reg);
|
||||
writel(0xda, start_address);
|
||||
writel(0xda, start_address);
|
||||
|
||||
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
|
||||
ctl_reg);
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_MR);
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
|
||||
|
||||
/* OCD mode exit */
|
||||
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
|
||||
|
||||
/* Set normal mode */
|
||||
writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
|
||||
ctl_reg);
|
||||
|
||||
dram_wait(0x20000);
|
||||
|
||||
/* Do not set delay lines, only for MDDR */
|
||||
}
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* relocate - i.MX35-specific vector relocation
|
||||
*
|
||||
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/*
|
||||
* The i.MX35 SoC is very specific with respect to exceptions: it
|
||||
* does not provide RAM at the high vectors address (0xFFFF0000),
|
||||
* thus only the low address (0x00000000) is useable; but that is
|
||||
* in ROM, so let's avoid relocating the vectors.
|
||||
*/
|
||||
.section .text.relocate_vectors,"ax",%progbits
|
||||
|
||||
ENTRY(relocate_vectors)
|
||||
|
||||
bx lr
|
||||
|
||||
ENDPROC(relocate_vectors)
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* Sascha Hauer, Pengutronix
|
||||
*
|
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/* General purpose timers bitfields */
|
||||
#define GPTCR_SWR (1<<15) /* Software reset */
|
||||
#define GPTCR_FRR (1<<9) /* Freerun / restart */
|
||||
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
|
||||
#define GPTCR_TEN (1) /* Timer enable */
|
||||
|
||||
/*
|
||||
* nothing really to do with interrupts, just starts up a counter.
|
||||
* The 32KHz 32-bit timer overruns in 134217 seconds
|
||||
*/
|
||||
int timer_init(void)
|
||||
{
|
||||
int i;
|
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
|
||||
struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
|
||||
|
||||
/* setup GP Timer 1 */
|
||||
writel(GPTCR_SWR, &gpt->ctrl);
|
||||
|
||||
writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
|
||||
|
||||
for (i = 0; i < 100; i++)
|
||||
writel(0, &gpt->ctrl); /* We have no udelay by now */
|
||||
writel(0, &gpt->pre); /* prescaler = 1 */
|
||||
/* Freerun Mode, 32KHz input */
|
||||
writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
|
||||
&gpt->ctrl);
|
||||
writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
#ifdef CONFIG_MX35_HCLK_FREQ
|
||||
#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
|
||||
#else
|
||||
#define MXC_HCLK 24000000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MX35_CLK32
|
||||
#define MXC_CLK32 CONFIG_MX35_CLK32
|
||||
#else
|
||||
#define MXC_CLK32 32768
|
||||
#endif
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK,
|
||||
MXC_AHB_CLK,
|
||||
MXC_IPG_CLK,
|
||||
MXC_IPG_PERCLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC1_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_ESDHC3_CLK,
|
||||
MXC_USB_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_FEC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
};
|
||||
|
||||
enum mxc_main_clock {
|
||||
CPU_CLK,
|
||||
AHB_CLK,
|
||||
IPG_CLK,
|
||||
IPG_PER_CLK,
|
||||
NFC_CLK,
|
||||
USB_CLK,
|
||||
HSP_CLK,
|
||||
};
|
||||
|
||||
enum mxc_peri_clock {
|
||||
UART1_BAUD,
|
||||
UART2_BAUD,
|
||||
UART3_BAUD,
|
||||
SSI1_BAUD,
|
||||
SSI2_BAUD,
|
||||
CSI_BAUD,
|
||||
MSHC_CLK,
|
||||
ESDHC1_CLK,
|
||||
ESDHC2_CLK,
|
||||
ESDHC3_CLK,
|
||||
SPDIF_CLK,
|
||||
SPI1_CLK,
|
||||
SPI2_CLK,
|
||||
};
|
||||
|
||||
u32 imx_get_uartclk(void);
|
||||
u32 imx_get_fecclk(void);
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,243 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2004-2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
|
||||
#define __CPU_ARM1136_MX35_CRM_REGS_H__
|
||||
|
||||
/* Register bit definitions */
|
||||
#define MXC_CCM_CCMR_WFI (1 << 30)
|
||||
#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29)
|
||||
#define MXC_CCM_CCMR_VSTBY (1 << 28)
|
||||
#define MXC_CCM_CCMR_WBEN (1 << 27)
|
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20
|
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
|
||||
#define MXC_CCM_CCMR_ROMW_OFFSET 18
|
||||
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCMR_RAMW_OFFSET 16
|
||||
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCMR_LPM_OFFSET 14
|
||||
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCMR_UPE (1 << 9)
|
||||
#define MXC_CCM_CCMR_MPE (1 << 3)
|
||||
|
||||
#define MXC_CCM_PDR0_PER_SEL (1 << 26)
|
||||
#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23)
|
||||
#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20
|
||||
#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
|
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16
|
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
|
||||
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
|
||||
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
|
||||
#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
|
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
|
||||
#define MXC_CCM_PDR0_AUTO_CON 0x1
|
||||
|
||||
#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28
|
||||
#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
|
||||
#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22
|
||||
#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22)
|
||||
#define MXC_CCM_PDR1_MSHC_M_U (1 << 7)
|
||||
|
||||
#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27
|
||||
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
|
||||
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
|
||||
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
|
||||
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
|
||||
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
|
||||
#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
|
||||
#define MXC_CCM_PDR2_SSI_M_U (1 << 6)
|
||||
#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0
|
||||
#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F)
|
||||
|
||||
#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29
|
||||
#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
|
||||
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
|
||||
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
|
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
|
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_PDR3_UART_M_U (1 << 14)
|
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
|
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8)
|
||||
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
|
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
|
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
|
||||
|
||||
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
|
||||
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
|
||||
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
|
||||
#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22)
|
||||
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
|
||||
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
|
||||
#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10)
|
||||
#define MXC_CCM_PDR4_USB_M_U (1 << 9)
|
||||
|
||||
/* Bit definitions for RCSR */
|
||||
#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29)
|
||||
#define MXC_CCM_RCSR_BUS_16BIT (1 << 29)
|
||||
#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27)
|
||||
#define MXC_CCM_RCSR_PAGE_512 (0 << 27)
|
||||
#define MXC_CCM_RCSR_PAGE_2K (1 << 27)
|
||||
#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27)
|
||||
#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27)
|
||||
#define MXC_CCM_RCSR_SOFT_RESET (1 << 15)
|
||||
#define MXC_CCM_RCSR_NF16B (1 << 14)
|
||||
#define MXC_CCM_RCSR_NFC_4K (1 << 9)
|
||||
#define MXC_CCM_RCSR_NFC_FMS (1 << 8)
|
||||
|
||||
/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
|
||||
#define MXC_CCM_PCTL_BRM 0x80000000
|
||||
#define MXC_CCM_PCTL_PD_OFFSET 26
|
||||
#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
|
||||
#define MXC_CCM_PCTL_MFD_OFFSET 16
|
||||
#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
|
||||
#define MXC_CCM_PCTL_MFI_OFFSET 10
|
||||
#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
|
||||
#define MXC_CCM_PCTL_MFN_OFFSET 0
|
||||
#define MXC_CCM_PCTL_MFN_MASK 0x3FF
|
||||
|
||||
/* Bit definitions for Audio clock mux register*/
|
||||
#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12
|
||||
#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12)
|
||||
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8
|
||||
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8)
|
||||
#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4
|
||||
#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4)
|
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0
|
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
|
||||
|
||||
/* Bit definitions for Clock gating Register*/
|
||||
#define MXC_CCM_CGR_CG_MASK 0x3
|
||||
#define MXC_CCM_CGR_CG_OFF 0x0
|
||||
#define MXC_CCM_CGR_CG_RUN_ON 0x1
|
||||
#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2
|
||||
#define MXC_CCM_CGR_CG_ON 0x3
|
||||
|
||||
#define MXC_CCM_CGR0_ASRC_OFFSET 0
|
||||
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
|
||||
#define MXC_CCM_CGR0_ATA_OFFSET 2
|
||||
#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CGR0_CAN1_OFFSET 6
|
||||
#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CGR0_CAN2_OFFSET 8
|
||||
#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CGR0_CSPI1_OFFSET 10
|
||||
#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CGR0_CSPI2_OFFSET 12
|
||||
#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CGR0_ECT_OFFSET 14
|
||||
#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CGR0_EDIO_OFFSET 16
|
||||
#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CGR0_EMI_OFFSET 18
|
||||
#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CGR0_EPIT1_OFFSET 20
|
||||
#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CGR0_EPIT2_OFFSET 22
|
||||
#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CGR0_ESAI_OFFSET 24
|
||||
#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CGR0_ESDHC1_OFFSET 26
|
||||
#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CGR0_ESDHC2_OFFSET 28
|
||||
#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CGR0_ESDHC3_OFFSET 30
|
||||
#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30)
|
||||
|
||||
#define MXC_CCM_CGR1_FEC_OFFSET 0
|
||||
#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0)
|
||||
#define MXC_CCM_CGR1_GPIO1_OFFSET 2
|
||||
#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CGR1_GPIO2_OFFSET 4
|
||||
#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CGR1_GPIO3_OFFSET 6
|
||||
#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CGR1_GPT_OFFSET 8
|
||||
#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CGR1_I2C1_OFFSET 10
|
||||
#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CGR1_I2C2_OFFSET 12
|
||||
#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CGR1_I2C3_OFFSET 14
|
||||
#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CGR1_IOMUXC_OFFSET 16
|
||||
#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CGR1_IPU_OFFSET 18
|
||||
#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CGR1_KPP_OFFSET 20
|
||||
#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CGR1_MLB_OFFSET 22
|
||||
#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CGR1_MSHC_OFFSET 24
|
||||
#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CGR1_OWIRE_OFFSET 26
|
||||
#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CGR1_PWM_OFFSET 28
|
||||
#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CGR1_RNGC_OFFSET 30
|
||||
#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30)
|
||||
|
||||
#define MXC_CCM_CGR2_RTC_OFFSET 0
|
||||
#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0)
|
||||
#define MXC_CCM_CGR2_RTIC_OFFSET 2
|
||||
#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CGR2_SCC_OFFSET 4
|
||||
#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CGR2_SDMA_OFFSET 6
|
||||
#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CGR2_SPBA_OFFSET 8
|
||||
#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CGR2_SPDIF_OFFSET 10
|
||||
#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CGR2_SSI1_OFFSET 12
|
||||
#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CGR2_SSI2_OFFSET 14
|
||||
#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CGR2_UART1_OFFSET 16
|
||||
#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CGR2_UART2_OFFSET 18
|
||||
#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CGR2_UART3_OFFSET 20
|
||||
#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CGR2_USBOTG_OFFSET 22
|
||||
#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CGR2_WDOG_OFFSET 24
|
||||
#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CGR2_MAX_OFFSET 26
|
||||
#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26)
|
||||
#define MXC_CCM_CGR2_AUDMUX_OFFSET 30
|
||||
#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30)
|
||||
|
||||
#define MXC_CCM_CGR3_CSI_OFFSET 0
|
||||
#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0)
|
||||
#define MXC_CCM_CGR3_IIM_OFFSET 2
|
||||
#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CGR3_GPU2D_OFFSET 4
|
||||
#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4)
|
||||
|
||||
#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F
|
||||
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
|
||||
#define MXC_CCM_COSR_CLKOEN (1 << 5)
|
||||
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
|
||||
#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10)
|
||||
#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10
|
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
|
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
|
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18
|
||||
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20
|
||||
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22)
|
||||
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22
|
||||
#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24)
|
||||
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26)
|
||||
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26
|
||||
|
||||
#endif
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_ARCH_MX35_GPIO_H
|
||||
#define __ASM_ARCH_MX35_GPIO_H
|
||||
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -1,356 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX35_H
|
||||
#define __ASM_ARCH_MX35_H
|
||||
|
||||
#define ARCH_MXC
|
||||
|
||||
/*
|
||||
* IRAM
|
||||
*/
|
||||
#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
|
||||
#define IRAM_SIZE 0x00020000 /* 128 KB */
|
||||
|
||||
#define LOW_LEVEL_SRAM_STACK 0x1001E000
|
||||
|
||||
/*
|
||||
* AIPS 1
|
||||
*/
|
||||
#define AIPS1_BASE_ADDR 0x43F00000
|
||||
#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
|
||||
#define MAX_BASE_ADDR 0x43F04000
|
||||
#define EVTMON_BASE_ADDR 0x43F08000
|
||||
#define CLKCTL_BASE_ADDR 0x43F0C000
|
||||
#define I2C1_BASE_ADDR 0x43F80000
|
||||
#define I2C3_BASE_ADDR 0x43F84000
|
||||
#define ATA_BASE_ADDR 0x43F8C000
|
||||
#define UART1_BASE 0x43F90000
|
||||
#define UART2_BASE 0x43F94000
|
||||
#define I2C2_BASE_ADDR 0x43F98000
|
||||
#define CSPI1_BASE_ADDR 0x43FA4000
|
||||
#define IOMUXC_BASE_ADDR 0x43FAC000
|
||||
|
||||
/*
|
||||
* SPBA
|
||||
*/
|
||||
#define SPBA_BASE_ADDR 0x50000000
|
||||
#define UART3_BASE 0x5000C000
|
||||
#define CSPI2_BASE_ADDR 0x50010000
|
||||
#define ATA_DMA_BASE_ADDR 0x50020000
|
||||
#define FEC_BASE_ADDR 0x50038000
|
||||
#define SPBA_CTRL_BASE_ADDR 0x5003C000
|
||||
|
||||
/*
|
||||
* AIPS 2
|
||||
*/
|
||||
#define AIPS2_BASE_ADDR 0x53F00000
|
||||
#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
|
||||
#define CCM_BASE_ADDR 0x53F80000
|
||||
#define GPT1_BASE_ADDR 0x53F90000
|
||||
#define EPIT1_BASE_ADDR 0x53F94000
|
||||
#define EPIT2_BASE_ADDR 0x53F98000
|
||||
#define GPIO3_BASE_ADDR 0x53FA4000
|
||||
#define MMC_SDHC1_BASE_ADDR 0x53FB4000
|
||||
#define MMC_SDHC2_BASE_ADDR 0x53FB8000
|
||||
#define MMC_SDHC3_BASE_ADDR 0x53FBC000
|
||||
#define IPU_CTRL_BASE_ADDR 0x53FC0000
|
||||
#define GPIO1_BASE_ADDR 0x53FCC000
|
||||
#define GPIO2_BASE_ADDR 0x53FD0000
|
||||
#define SDMA_BASE_ADDR 0x53FD4000
|
||||
#define RTC_BASE_ADDR 0x53FD8000
|
||||
#define WDOG1_BASE_ADDR 0x53FDC000
|
||||
#define PWM_BASE_ADDR 0x53FE0000
|
||||
#define RTIC_BASE_ADDR 0x53FEC000
|
||||
#define IIM_BASE_ADDR 0x53FF0000
|
||||
#define IMX_USB_BASE 0x53FF4000
|
||||
#define IMX_USB_PORT_OFFSET 0x400
|
||||
|
||||
#define IMX_CCM_BASE CCM_BASE_ADDR
|
||||
|
||||
/*
|
||||
* ROMPATCH and AVIC
|
||||
*/
|
||||
#define ROMPATCH_BASE_ADDR 0x60000000
|
||||
#define AVIC_BASE_ADDR 0x68000000
|
||||
|
||||
/*
|
||||
* NAND, SDRAM, WEIM, M3IF, EMI controllers
|
||||
*/
|
||||
#define EXT_MEM_CTRL_BASE 0xB8000000
|
||||
#define ESDCTL_BASE_ADDR 0xB8001000
|
||||
#define WEIM_BASE_ADDR 0xB8002000
|
||||
#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
|
||||
#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
|
||||
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
|
||||
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
|
||||
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
|
||||
#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
|
||||
#define M3IF_BASE_ADDR 0xB8003000
|
||||
#define EMI_BASE_ADDR 0xB8004000
|
||||
|
||||
#define NFC_BASE_ADDR 0xBB000000
|
||||
|
||||
/*
|
||||
* Memory regions and CS
|
||||
*/
|
||||
#define IPU_MEM_BASE_ADDR 0x70000000
|
||||
#define CSD0_BASE_ADDR 0x80000000
|
||||
#define CSD1_BASE_ADDR 0x90000000
|
||||
#define CS0_BASE_ADDR 0xA0000000
|
||||
#define CS1_BASE_ADDR 0xA8000000
|
||||
#define CS2_BASE_ADDR 0xB0000000
|
||||
#define CS3_BASE_ADDR 0xB2000000
|
||||
#define CS4_BASE_ADDR 0xB4000000
|
||||
#define CS5_BASE_ADDR 0xB6000000
|
||||
|
||||
/*
|
||||
* IRQ Controller Register Definitions.
|
||||
*/
|
||||
#define AVIC_NIMASK 0x04
|
||||
#define AVIC_INTTYPEH 0x18
|
||||
#define AVIC_INTTYPEL 0x1C
|
||||
|
||||
/* L210 */
|
||||
#define L2CC_BASE_ADDR 0x30000000
|
||||
#define L2_CACHE_LINE_SIZE 32
|
||||
#define L2_CACHE_CTL_REG 0x100
|
||||
#define L2_CACHE_AUX_CTL_REG 0x104
|
||||
#define L2_CACHE_SYNC_REG 0x730
|
||||
#define L2_CACHE_INV_LINE_REG 0x770
|
||||
#define L2_CACHE_INV_WAY_REG 0x77C
|
||||
#define L2_CACHE_CLEAN_LINE_REG 0x7B0
|
||||
#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
|
||||
#define L2_CACHE_DBG_CTL_REG 0xF40
|
||||
|
||||
#define CLKMODE_AUTO 0
|
||||
#define CLKMODE_CONSUMER 1
|
||||
|
||||
#define PLL_PD(x) (((x) & 0xf) << 26)
|
||||
#define PLL_MFD(x) (((x) & 0x3ff) << 16)
|
||||
#define PLL_MFI(x) (((x) & 0xf) << 10)
|
||||
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
|
||||
|
||||
#define _PLL_BRM(x) ((x) << 31)
|
||||
#define _PLL_PD(x) (((x) - 1) << 26)
|
||||
#define _PLL_MFD(x) (((x) - 1) << 16)
|
||||
#define _PLL_MFI(x) ((x) << 10)
|
||||
#define _PLL_MFN(x) (x)
|
||||
#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
|
||||
(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
|
||||
_PLL_MFN(mfn))
|
||||
|
||||
#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
|
||||
#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
|
||||
#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
|
||||
|
||||
#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
|
||||
#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
|
||||
#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
|
||||
|
||||
#define IIM_SREV 0x24
|
||||
#define ROMPATCH_REV 0x40
|
||||
|
||||
#define IPU_CONF IPU_CTRL_BASE_ADDR
|
||||
|
||||
#define IPU_CONF_PXL_ENDIAN (1<<8)
|
||||
#define IPU_CONF_DU_EN (1<<7)
|
||||
#define IPU_CONF_DI_EN (1<<6)
|
||||
#define IPU_CONF_ADC_EN (1<<5)
|
||||
#define IPU_CONF_SDC_EN (1<<4)
|
||||
#define IPU_CONF_PF_EN (1<<3)
|
||||
#define IPU_CONF_ROT_EN (1<<2)
|
||||
#define IPU_CONF_IC_EN (1<<1)
|
||||
#define IPU_CONF_CSI_EN (1<<0)
|
||||
|
||||
/*
|
||||
* CSPI register definitions
|
||||
*/
|
||||
#define MXC_SPI_BASE_ADDRESSES \
|
||||
0x43fa4000, \
|
||||
0x50010000,
|
||||
|
||||
#define GPIO_PORT_NUM 3
|
||||
#define GPIO_NUM_PIN 32
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_2_0 0x20
|
||||
|
||||
#define BOARD_REV_1_0 0x0
|
||||
#define BOARD_REV_2_0 0x1
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
|
||||
/* Clock Control Module (CCM) registers */
|
||||
struct ccm_regs {
|
||||
u32 ccmr; /* Control */
|
||||
u32 pdr0; /* Post divider 0 */
|
||||
u32 pdr1; /* Post divider 1 */
|
||||
u32 pdr2; /* Post divider 2 */
|
||||
u32 pdr3; /* Post divider 3 */
|
||||
u32 pdr4; /* Post divider 4 */
|
||||
u32 rcsr; /* CCM Status */
|
||||
u32 mpctl; /* Core PLL Control */
|
||||
u32 ppctl; /* Peripheral PLL Control */
|
||||
u32 acmr; /* Audio clock mux */
|
||||
u32 cosr; /* Clock out source */
|
||||
u32 cgr0; /* Clock Gating Control 0 */
|
||||
u32 cgr1; /* Clock Gating Control 1 */
|
||||
u32 cgr2; /* Clock Gating Control 2 */
|
||||
u32 cgr3; /* Clock Gating Control 3 */
|
||||
u32 reserved;
|
||||
u32 dcvr0; /* DPTC Comparator 0 */
|
||||
u32 dcvr1; /* DPTC Comparator 0 */
|
||||
u32 dcvr2; /* DPTC Comparator 0 */
|
||||
u32 dcvr3; /* DPTC Comparator 0 */
|
||||
u32 ltr0; /* Load Tracking 0 */
|
||||
u32 ltr1; /* Load Tracking 1 */
|
||||
u32 ltr2; /* Load Tracking 2 */
|
||||
u32 ltr3; /* Load Tracking 3 */
|
||||
u32 ltbr0; /* Load Tracking Buffer 0 */
|
||||
};
|
||||
|
||||
/* IIM control registers */
|
||||
struct iim_regs {
|
||||
u32 iim_stat;
|
||||
u32 iim_statm;
|
||||
u32 iim_err;
|
||||
u32 iim_emask;
|
||||
u32 iim_fctl;
|
||||
u32 iim_ua;
|
||||
u32 iim_la;
|
||||
u32 iim_sdat;
|
||||
u32 iim_prev;
|
||||
u32 iim_srev;
|
||||
u32 iim_prg_p;
|
||||
u32 iim_scs0;
|
||||
u32 iim_scs1;
|
||||
u32 iim_scs2;
|
||||
u32 iim_scs3;
|
||||
u32 res1[0x1f1];
|
||||
struct fuse_bank {
|
||||
u32 fuse_regs[0x20];
|
||||
u32 fuse_rsvd[0xe0];
|
||||
} bank[3];
|
||||
};
|
||||
|
||||
struct fuse_bank0_regs {
|
||||
u32 fuse0_7[8];
|
||||
u32 uid[8];
|
||||
u32 fuse16_31[0x10];
|
||||
};
|
||||
|
||||
struct fuse_bank1_regs {
|
||||
u32 fuse0_21[0x16];
|
||||
u32 usr;
|
||||
u32 fuse23_31[9];
|
||||
};
|
||||
|
||||
/* General Purpose Timer (GPT) registers */
|
||||
struct gpt_regs {
|
||||
u32 ctrl; /* control */
|
||||
u32 pre; /* prescaler */
|
||||
u32 stat; /* status */
|
||||
u32 intr; /* interrupt */
|
||||
u32 cmp[3]; /* output compare 1-3 */
|
||||
u32 capt[2]; /* input capture 1-2 */
|
||||
u32 counter; /* counter */
|
||||
};
|
||||
|
||||
struct esdc_regs {
|
||||
u32 esdctl0;
|
||||
u32 esdcfg0;
|
||||
u32 esdctl1;
|
||||
u32 esdcfg1;
|
||||
u32 esdmisc;
|
||||
u32 reserved[4];
|
||||
u32 esdcdly[5];
|
||||
u32 esdcdlyl;
|
||||
};
|
||||
|
||||
#define ESDC_MISC_RST (1 << 1)
|
||||
#define ESDC_MISC_MDDR_EN (1 << 2)
|
||||
#define ESDC_MISC_MDDR_DL_RST (1 << 3)
|
||||
#define ESDC_MISC_DDR_EN (1 << 8)
|
||||
#define ESDC_MISC_DDR2_EN (1 << 9)
|
||||
|
||||
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
|
||||
struct max_regs {
|
||||
u32 mpr0;
|
||||
u32 pad00[3];
|
||||
u32 sgpcr0;
|
||||
u32 pad01[59];
|
||||
u32 mpr1;
|
||||
u32 pad02[3];
|
||||
u32 sgpcr1;
|
||||
u32 pad03[59];
|
||||
u32 mpr2;
|
||||
u32 pad04[3];
|
||||
u32 sgpcr2;
|
||||
u32 pad05[59];
|
||||
u32 mpr3;
|
||||
u32 pad06[3];
|
||||
u32 sgpcr3;
|
||||
u32 pad07[59];
|
||||
u32 mpr4;
|
||||
u32 pad08[3];
|
||||
u32 sgpcr4;
|
||||
u32 pad09[251];
|
||||
u32 mgpcr0;
|
||||
u32 pad10[63];
|
||||
u32 mgpcr1;
|
||||
u32 pad11[63];
|
||||
u32 mgpcr2;
|
||||
u32 pad12[63];
|
||||
u32 mgpcr3;
|
||||
u32 pad13[63];
|
||||
u32 mgpcr4;
|
||||
u32 pad14[63];
|
||||
u32 mgpcr5;
|
||||
};
|
||||
|
||||
/* AHB <-> IP-Bus Interface (AIPS) */
|
||||
struct aips_regs {
|
||||
u32 mpr_0_7;
|
||||
u32 mpr_8_15;
|
||||
u32 pad0[6];
|
||||
u32 pacr_0_7;
|
||||
u32 pacr_8_15;
|
||||
u32 pacr_16_23;
|
||||
u32 pacr_24_31;
|
||||
u32 pad1[4];
|
||||
u32 opacr_0_7;
|
||||
u32 opacr_8_15;
|
||||
u32 opacr_16_23;
|
||||
u32 opacr_24_31;
|
||||
u32 opacr_32_39;
|
||||
};
|
||||
|
||||
/*
|
||||
* NFMS bit in RCSR register for pagesize of nandflash
|
||||
*/
|
||||
#define NFMS_BIT 8
|
||||
#define NFMS_NF_DWIDTH 14
|
||||
#define NFMS_NF_PG_SZ 8
|
||||
|
||||
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Generic timer support
|
||||
*/
|
||||
#ifdef CONFIG_MX35_CLK32
|
||||
#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32
|
||||
#else
|
||||
#define CONFIG_SYS_TIMER_RATE 32768
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36)
|
||||
|
||||
#endif /* __ASM_ARCH_MX35_H */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,125 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
/*
|
||||
* AIPS setup - Only setup MPROTx registers.
|
||||
* The PACR default values are good.
|
||||
*
|
||||
* Default argument values:
|
||||
* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
|
||||
* user-mode.
|
||||
* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
|
||||
* SDMA to access them.
|
||||
*/
|
||||
.macro init_aips mpr=0x77777777, opacr=0x00000000
|
||||
ldr r0, =AIPS1_BASE_ADDR
|
||||
ldr r1, =\mpr
|
||||
str r1, [r0, #AIPS_MPR_0_7]
|
||||
str r1, [r0, #AIPS_MPR_8_15]
|
||||
ldr r2, =AIPS2_BASE_ADDR
|
||||
str r1, [r2, #AIPS_MPR_0_7]
|
||||
str r1, [r2, #AIPS_MPR_8_15]
|
||||
|
||||
/* Did not change the AIPS control registers access type. */
|
||||
ldr r1, =\opacr
|
||||
str r1, [r0, #AIPS_OPACR_0_7]
|
||||
str r1, [r0, #AIPS_OPACR_8_15]
|
||||
str r1, [r0, #AIPS_OPACR_16_23]
|
||||
str r1, [r0, #AIPS_OPACR_24_31]
|
||||
str r1, [r0, #AIPS_OPACR_32_39]
|
||||
str r1, [r2, #AIPS_OPACR_0_7]
|
||||
str r1, [r2, #AIPS_OPACR_8_15]
|
||||
str r1, [r2, #AIPS_OPACR_16_23]
|
||||
str r1, [r2, #AIPS_OPACR_24_31]
|
||||
str r1, [r2, #AIPS_OPACR_32_39]
|
||||
.endm
|
||||
|
||||
/*
|
||||
* MAX (Multi-Layer AHB Crossbar Switch) setup
|
||||
*
|
||||
* Default argument values:
|
||||
* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
|
||||
* - SGPCR: always park on last master
|
||||
* - MGPCR: restore default values
|
||||
*/
|
||||
.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
|
||||
ldr r0, =MAX_BASE_ADDR
|
||||
ldr r1, =\mpr
|
||||
str r1, [r0, #MAX_MPR0] /* for S0 */
|
||||
str r1, [r0, #MAX_MPR1] /* for S1 */
|
||||
str r1, [r0, #MAX_MPR2] /* for S2 */
|
||||
str r1, [r0, #MAX_MPR3] /* for S3 */
|
||||
str r1, [r0, #MAX_MPR4] /* for S4 */
|
||||
ldr r1, =\sgpcr
|
||||
str r1, [r0, #MAX_SGPCR0] /* for S0 */
|
||||
str r1, [r0, #MAX_SGPCR1] /* for S1 */
|
||||
str r1, [r0, #MAX_SGPCR2] /* for S2 */
|
||||
str r1, [r0, #MAX_SGPCR3] /* for S3 */
|
||||
str r1, [r0, #MAX_SGPCR4] /* for S4 */
|
||||
ldr r1, =\mgpcr
|
||||
str r1, [r0, #MAX_MGPCR0] /* for M0 */
|
||||
str r1, [r0, #MAX_MGPCR1] /* for M1 */
|
||||
str r1, [r0, #MAX_MGPCR2] /* for M2 */
|
||||
str r1, [r0, #MAX_MGPCR3] /* for M3 */
|
||||
str r1, [r0, #MAX_MGPCR4] /* for M4 */
|
||||
str r1, [r0, #MAX_MGPCR5] /* for M5 */
|
||||
.endm
|
||||
|
||||
/*
|
||||
* M3IF setup
|
||||
*
|
||||
* Default argument values:
|
||||
* - CTL:
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
.macro init_m3if ctl=0x00000040
|
||||
/* M3IF Control Register (M3IFCTL) */
|
||||
write32 M3IF_BASE_ADDR, \ctl
|
||||
.endm
|
||||
|
||||
.macro core_init
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
|
||||
/* Set branch prediction enable */
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
orr r0, r0, #7
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
orr r1, r1, #1 << 11
|
||||
|
||||
/* Set unaligned access enable */
|
||||
orr r1, r1, #1 << 22
|
||||
|
||||
/* Set low int latency enable */
|
||||
orr r1, r1, #1 << 21
|
||||
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
|
||||
mov r0, #0
|
||||
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
|
||||
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
|
||||
mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
|
||||
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
|
||||
|
||||
/* Setup the Peripheral Port Memory Remap Register */
|
||||
ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
.endm
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef MMC_HOST_DEF_H
|
||||
#define MMC_HOST_DEF_H
|
||||
|
||||
/* Driver definitions */
|
||||
#define MMCSD_SECTOR_SIZE 512
|
||||
|
||||
#endif /* MMC_HOST_DEF_H */
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*/
|
||||
|
||||
#ifndef _MX35_SYS_PROTO_H_
|
||||
#define _MX35_SYS_PROTO_H_
|
||||
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
|
||||
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
|
||||
u32 col, u32 dsize, u32 refresh);
|
||||
|
||||
#endif
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
#include <linux/kbuild.h>
|
||||
#include <linux/arm-smccc.h>
|
||||
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) \
|
||||
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#endif
|
||||
|
|
@ -97,56 +97,6 @@ int main(void)
|
|||
offsetof(struct system_control_regs, fmcr));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX35)
|
||||
/* Round up to make sure size gives nice stack alignment */
|
||||
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
|
||||
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
|
||||
DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
|
||||
DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
|
||||
DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
|
||||
DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
|
||||
DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
|
||||
DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
|
||||
DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
|
||||
DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
|
||||
DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
|
||||
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
|
||||
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
|
||||
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
|
||||
DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
|
||||
|
||||
/* Multi-Layer AHB Crossbar Switch */
|
||||
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
|
||||
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
|
||||
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
|
||||
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
|
||||
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
|
||||
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
|
||||
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
|
||||
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
|
||||
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
|
||||
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
|
||||
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
|
||||
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
|
||||
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
|
||||
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
|
||||
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
|
||||
DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
|
||||
|
||||
/* AHB <-> IP-Bus Interface */
|
||||
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
|
||||
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
|
||||
DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
|
||||
DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
|
||||
DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
|
||||
DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
|
||||
DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
|
||||
DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
|
||||
DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
|
||||
DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
|
||||
DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
|
||||
/* Round up to make sure size gives nice stack alignment */
|
||||
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
if TARGET_FLEA3
|
||||
|
||||
config SYS_BOARD
|
||||
default "flea3"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "CarMediaLab"
|
||||
|
||||
config SYS_SOC
|
||||
default "mx35"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "flea3"
|
||||
|
||||
endif
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
FLEA3 BOARD
|
||||
M: Stefano Babic <sbabic@denx.de>
|
||||
S: Maintained
|
||||
F: board/CarMediaLab/flea3/
|
||||
F: include/configs/flea3.h
|
||||
F: configs/flea3_defconfig
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y := flea3.o
|
||||
obj-y += lowlevel_init.o
|
||||
|
|
@ -1,227 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <env.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/iomux-mx35.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <netdev.h>
|
||||
#include <fdt_support.h>
|
||||
#include <mtd_node.h>
|
||||
#include <jffs2/load_kernel.h>
|
||||
|
||||
#ifndef CONFIG_BOARD_EARLY_INIT_F
|
||||
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
|
||||
#endif
|
||||
|
||||
#define CCM_CCMR_CONFIG 0x003F4208
|
||||
|
||||
#define ESDCTL_DDR2_CONFIG 0x007FFC3F
|
||||
|
||||
static inline void dram_wait(unsigned int count)
|
||||
{
|
||||
volatile unsigned int wait = count;
|
||||
|
||||
while (wait--)
|
||||
;
|
||||
}
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
|
||||
PHYS_SDRAM_1_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void board_setup_sdram(void)
|
||||
{
|
||||
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
|
||||
|
||||
/* Initialize with default values both CSD0/1 */
|
||||
writel(0x2000, &esdc->esdctl0);
|
||||
writel(0x2000, &esdc->esdctl1);
|
||||
|
||||
|
||||
mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
|
||||
13, 10, 2, 0x8080);
|
||||
}
|
||||
|
||||
static void setup_iomux_uart3(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t uart3_pads[] = {
|
||||
MX35_PAD_RTS2__UART3_RXD_MUX,
|
||||
MX35_PAD_CTS2__UART3_TXD_MUX,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
|
||||
|
||||
static void setup_iomux_i2c(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t i2c_pads[] = {
|
||||
NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
|
||||
|
||||
NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
|
||||
}
|
||||
|
||||
|
||||
static void setup_iomux_spi(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t spi_pads[] = {
|
||||
MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
|
||||
MX35_PAD_CSPI1_MISO__CSPI1_MISO,
|
||||
MX35_PAD_CSPI1_SS0__CSPI1_SS0,
|
||||
MX35_PAD_CSPI1_SS1__CSPI1_SS1,
|
||||
MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t fec_pads[] = {
|
||||
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
|
||||
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
|
||||
MX35_PAD_FEC_RX_DV__FEC_RX_DV,
|
||||
MX35_PAD_FEC_COL__FEC_COL,
|
||||
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
|
||||
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
|
||||
MX35_PAD_FEC_TX_EN__FEC_TX_EN,
|
||||
MX35_PAD_FEC_MDC__FEC_MDC,
|
||||
MX35_PAD_FEC_MDIO__FEC_MDIO,
|
||||
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
|
||||
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
|
||||
MX35_PAD_FEC_CRS__FEC_CRS,
|
||||
MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
|
||||
MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
|
||||
MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
|
||||
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
|
||||
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
|
||||
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
|
||||
/* GPIO used to power off ethernet */
|
||||
MX35_PAD_STXFS4__GPIO2_31,
|
||||
};
|
||||
|
||||
/* setup pins for FEC */
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct ccm_regs *ccm =
|
||||
(struct ccm_regs *)IMX_CCM_BASE;
|
||||
|
||||
/* setup GPIO3_1 to set HighVCore signal */
|
||||
imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
|
||||
gpio_direction_output(65, 1);
|
||||
|
||||
/* initialize PLL and clock configuration */
|
||||
writel(CCM_CCMR_CONFIG, &ccm->ccmr);
|
||||
|
||||
writel(CCM_MPLL_532_HZ, &ccm->mpctl);
|
||||
writel(CCM_PPLL_300_HZ, &ccm->ppctl);
|
||||
|
||||
/* Set the core to run at 532 Mhz */
|
||||
writel(0x00001000, &ccm->pdr0);
|
||||
|
||||
/* Set-up RAM */
|
||||
board_setup_sdram();
|
||||
|
||||
/* enable clocks */
|
||||
writel(readl(&ccm->cgr0) |
|
||||
MXC_CCM_CGR0_EMI_MASK |
|
||||
MXC_CCM_CGR0_EDIO_MASK |
|
||||
MXC_CCM_CGR0_EPIT1_MASK,
|
||||
&ccm->cgr0);
|
||||
|
||||
writel(readl(&ccm->cgr1) |
|
||||
MXC_CCM_CGR1_FEC_MASK |
|
||||
MXC_CCM_CGR1_GPIO1_MASK |
|
||||
MXC_CCM_CGR1_GPIO2_MASK |
|
||||
MXC_CCM_CGR1_GPIO3_MASK |
|
||||
MXC_CCM_CGR1_I2C1_MASK |
|
||||
MXC_CCM_CGR1_I2C2_MASK |
|
||||
MXC_CCM_CGR1_I2C3_MASK,
|
||||
&ccm->cgr1);
|
||||
|
||||
/* Set-up NAND */
|
||||
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
|
||||
|
||||
/* Set pinmux for the required peripherals */
|
||||
setup_iomux_uart3();
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_fec();
|
||||
setup_iomux_spi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
/* Enable power for ethernet */
|
||||
gpio_direction_output(63, 0);
|
||||
|
||||
udelay(2000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_REVISION_TAG
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
int rev = 0;
|
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* called prior to booting kernel or by 'fdt boardsetup' command
|
||||
*
|
||||
*/
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
static const struct node_info nodes[] = {
|
||||
{ "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
|
||||
{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
|
||||
};
|
||||
|
||||
if (env_get("fdt_noauto")) {
|
||||
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <asm/arch/lowlevel_macro.S>
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
core_init
|
||||
|
||||
init_aips
|
||||
|
||||
init_max
|
||||
|
||||
init_m3if
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SYS_DCACHE_OFF=y
|
||||
CONFIG_TARGET_FLEA3=y
|
||||
CONFIG_SYS_TEXT_BASE=0xA0000000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_SYS_I2C_MXC_I2C2=y
|
||||
CONFIG_SYS_I2C_MXC_I2C3=y
|
||||
CONFIG_SYS_MALLOC_LEN=0x110000
|
||||
CONFIG_SYS_LOAD_ADDR=0x80800000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="flea3 U-Boot > "
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SPI=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_ENV_ADDR=0xA0080000
|
||||
CONFIG_ENV_ADDR_REDUND=0xA0090000
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_SYS_I2C_LEGACY=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_SYS_MXC_I2C3_SLAVE=0xfe
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_PROTECTION=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_MXC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_FDT_FIXUP_PARTITIONS=y
|
||||
|
|
@ -11,7 +11,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/io.h>
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || \
|
||||
defined(CONFIG_MX51) || defined(CONFIG_MX53)
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#define is_mxc_nfc_1() 1
|
||||
#define is_mxc_nfc_21() 0
|
||||
#define is_mxc_nfc_32() 0
|
||||
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
|
||||
#elif defined(CONFIG_MX25)
|
||||
#define MXC_NFC_V2_1
|
||||
#define is_mxc_nfc_1() 0
|
||||
#define is_mxc_nfc_21() 1
|
||||
|
|
|
|||
|
|
@ -645,8 +645,7 @@ config MCFUART
|
|||
|
||||
config MXC_UART
|
||||
bool "IMX serial port support"
|
||||
depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
|
||||
|| MX5 || MX6 || MX7 || IMX8M
|
||||
depends on ARCH_MX25 || ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
|
||||
help
|
||||
If you have a machine based on a Motorola IMX CPU you
|
||||
can enable its onboard serial port by enabling this option.
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* MX35 and older is CSPI */
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35)
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
|
||||
#define MXC_CSPI
|
||||
struct cspi_regs {
|
||||
u32 rxdata;
|
||||
|
|
@ -48,7 +48,7 @@ struct cspi_regs {
|
|||
#define MXC_CSPICTRL_RXOVF BIT(6)
|
||||
#define MXC_CSPIPERIOD_32KHZ BIT(15)
|
||||
#define MAX_SPI_BYTES 4
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
|
||||
#if defined(CONFIG_MX25)
|
||||
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
|
||||
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
|
||||
#define MXC_CSPICTRL_TC BIT(7)
|
||||
|
|
@ -211,9 +211,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
|
|||
MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
|
||||
MXC_CSPICTRL_DATARATE(div) |
|
||||
MXC_CSPICTRL_EN |
|
||||
#ifdef CONFIG_MX35
|
||||
MXC_CSPICTRL_SSCTL |
|
||||
#endif
|
||||
MXC_CSPICTRL_MODE;
|
||||
|
||||
if (mode & SPI_CPHA)
|
||||
|
|
|
|||
|
|
@ -147,55 +147,6 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
|
|||
if (!(flags & MXC_EHCI_TTL_ENABLED))
|
||||
v |= MX31_H2_DT_BIT;
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
#elif defined(CONFIG_MX35)
|
||||
switch (port) {
|
||||
case 0: /* OTG port */
|
||||
v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
|
||||
MX35_OTG_OCPOL_BIT);
|
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX35_OTG_PM_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
|
||||
v |= MX35_OTG_PP_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
|
||||
v |= MX35_OTG_OCPOL_BIT;
|
||||
|
||||
break;
|
||||
case 1: /* H1 port */
|
||||
v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
|
||||
MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
|
||||
MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
|
||||
MX35_H1_IPPUE_UP_BIT);
|
||||
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
|
||||
|
||||
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
|
||||
v |= MX35_H1_PM_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
|
||||
v |= MX35_H1_PP_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
|
||||
v |= MX35_H1_OCPOL_BIT;
|
||||
|
||||
if (!(flags & MXC_EHCI_TTL_ENABLED))
|
||||
v |= MX35_H1_TLL_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_INTERNAL_PHY)
|
||||
v |= MX35_H1_USBTE_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_IPPUE_DOWN)
|
||||
v |= MX35_H1_IPPUE_DOWN_BIT;
|
||||
|
||||
if (flags & MXC_EHCI_IPPUE_UP)
|
||||
v |= MX35_H1_IPPUE_UP_BIT;
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
|
@ -230,10 +181,6 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
|||
setbits_le32(&ehci->usbmode, CM_HOST);
|
||||
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
|
||||
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
|
||||
#ifdef CONFIG_MX35
|
||||
/* Workaround for ENGcm11601 */
|
||||
__raw_writel(0, &ehci->sbuscfg);
|
||||
#endif
|
||||
|
||||
udelay(10000);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,155 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* Configuration for the flea3 board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_MX35
|
||||
|
||||
/* Set TEXT at the beginning of the NOR flash */
|
||||
|
||||
/* This is required to setup the ESDC controller */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */
|
||||
|
||||
/*
|
||||
* UART (console)
|
||||
*/
|
||||
#define CONFIG_MXC_UART_BASE UART3_BASE
|
||||
|
||||
/*
|
||||
* Command definition
|
||||
*/
|
||||
|
||||
#define CONFIG_NET_RETRY_COUNT 100
|
||||
|
||||
/*
|
||||
* Ethernet on SOC (FEC)
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_GBL_DATA_OFFSET)
|
||||
|
||||
/*
|
||||
* MTD Command for mtdparts
|
||||
*/
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
/* Monitor at beginning of flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
|
||||
/*
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
|
||||
/* A non-standard buffered write algorithm */
|
||||
|
||||
/*
|
||||
* NAND FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
|
||||
/*
|
||||
* Default environment and default scripts
|
||||
* to update uboot and load kernel
|
||||
*/
|
||||
|
||||
#define CONFIG_HOSTNAME "flea3"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip_sta=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
|
||||
"addip=if test -n ${ipdyn};then run addip_dyn;" \
|
||||
"else run addip_sta;fi\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=ttymxc2,${baudrate}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
|
||||
"loadaddr=80800000\0" \
|
||||
"kernel_addr_r=80800000\0" \
|
||||
"hostname=" CONFIG_HOSTNAME "\0" \
|
||||
"bootfile=" CONFIG_HOSTNAME "/uImage\0" \
|
||||
"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
|
||||
"net_self=if run net_self_load;then " \
|
||||
"run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
|
||||
"else echo Images not loades;fi\0" \
|
||||
"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
|
||||
"update=protect off ${uboot_addr} +80000;" \
|
||||
"erase ${uboot_addr} +80000;" \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
"else echo Error updating u-boot !;" \
|
||||
"echo Board without bootloader !!;" \
|
||||
"fi;" \
|
||||
"else echo U-Boot not downloaded..exiting;fi\0" \
|
||||
"bootcmd=run net_nfs\0"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Add table
Reference in a new issue