mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-17 02:15:02 +00:00
Merge branch 'next'
This commit is contained in:
Tom Rini
commit
146a82c017
632 changed files with 17418 additions and 15606 deletions
|
|
@ -391,12 +391,12 @@ stages:
|
|||
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
|
||||
grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
|
||||
if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
|
||||
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
|
||||
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
# the below corresponds to .gitlab-ci.yml "script"
|
||||
cd ${WORK_DIR}
|
||||
|
|
|
|||
|
|
@ -29,12 +29,12 @@ stages:
|
|||
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
|
||||
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
|
||||
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
|
||||
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
|
||||
wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
|
||||
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ;
|
||||
export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
|
||||
fi
|
||||
|
||||
after_script:
|
||||
|
|
|
|||
|
|
@ -343,6 +343,7 @@ F: drivers/rtc/armada38x.c
|
|||
F: drivers/spi/kirkwood_spi.c
|
||||
F: drivers/spi/mvebu_a3700_spi.c
|
||||
F: drivers/pci/pcie_dw_mvebu.c
|
||||
F: drivers/pci/pcie-xilinx-nwl.c
|
||||
F: drivers/watchdog/armada-37xx-wdt.c
|
||||
F: drivers/watchdog/orion_wdt.c
|
||||
F: include/configs/mv-common.h
|
||||
|
|
@ -755,6 +756,7 @@ F: drivers/spi/zynq_qspi.c
|
|||
F: drivers/spi/zynq_spi.c
|
||||
F: drivers/timer/cadence-ttc.c
|
||||
F: drivers/video/seps525.c
|
||||
F: drivers/video/zynqmp/
|
||||
F: drivers/watchdog/cdns_wdt.c
|
||||
F: include/zynqmppl.h
|
||||
F: include/zynqmp_firmware.h
|
||||
|
|
|
|||
14
Makefile
14
Makefile
|
|
@ -423,7 +423,8 @@ DTC_MIN_VERSION := 010406
|
|||
CHECK = sparse
|
||||
|
||||
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
|
||||
-Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
|
||||
-Wbitwise -Wno-return-void -Wno-unknown-attribute \
|
||||
-D__CHECK_ENDIAN__ $(CF)
|
||||
|
||||
KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
|
||||
|
||||
|
|
@ -1032,6 +1033,9 @@ ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
|
|||
LDFLAGS_u-boot += -Ttext $(CONFIG_TEXT_BASE)
|
||||
endif
|
||||
|
||||
# make the checker run with the right architecture
|
||||
CHECKFLAGS += --arch=$(ARCH)
|
||||
|
||||
# insure the checker run with the right endianness
|
||||
CHECKFLAGS += $(if $(CONFIG_CPU_BIG_ENDIAN),-mbig-endian,-mlittle-endian)
|
||||
|
||||
|
|
@ -1808,7 +1812,7 @@ quiet_cmd_gen_envp = ENVP $@
|
|||
rm -f $@; \
|
||||
touch $@ ; \
|
||||
fi
|
||||
include/generated/env.in: include/generated/env.txt FORCE
|
||||
include/generated/env.in: include/generated/env.txt
|
||||
$(call cmd,gen_envp)
|
||||
|
||||
# Regenerate the environment if it changes
|
||||
|
|
@ -1826,7 +1830,7 @@ quiet_cmd_envc = ENVC $@
|
|||
touch $@ ; \
|
||||
fi
|
||||
|
||||
include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
|
||||
include/generated/env.txt: $(wildcard $(ENV_FILE))
|
||||
$(call cmd,envc)
|
||||
|
||||
# Write out the resulting environment, converted to a C string
|
||||
|
|
@ -2148,7 +2152,7 @@ CHANGELOG:
|
|||
|
||||
# Directories & files removed with 'make clean'
|
||||
CLEAN_DIRS += $(MODVERDIR) \
|
||||
$(foreach d, spl tpl, $(patsubst %,$d/%, \
|
||||
$(foreach d, spl tpl vpl, $(patsubst %,$d/%, \
|
||||
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
|
||||
|
||||
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
|
||||
|
|
@ -2163,7 +2167,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
|
|||
idbloader-spi.img lib/efi_loader/helloworld_efi.S
|
||||
|
||||
# Directories & files removed with 'make mrproper'
|
||||
MRPROPER_DIRS += include/config include/generated spl tpl \
|
||||
MRPROPER_DIRS += include/config include/generated spl tpl vpl \
|
||||
.tmp_objdiff doc/output include/asm
|
||||
|
||||
# Remove include/asm symlink created by U-Boot before v2014.01
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ config ESBC_HDR_LS
|
|||
|
||||
config ESBC_ADDR_64BIT
|
||||
def_bool y
|
||||
depends on ESBC_HDR_LS && FSL_LAYERSCAPE
|
||||
depends on FSL_LAYERSCAPE
|
||||
help
|
||||
For Layerscape based platforms, ESBC image Address in Header is 64bit.
|
||||
|
||||
|
|
@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH
|
|||
default ""
|
||||
help
|
||||
Set the key hash for U-Boot here if public/private key pair used to
|
||||
sign U-boot are different from the SRK hash put in the fuse. Example
|
||||
sign U-Boot are different from the SRK hash put in the fuse. Example
|
||||
of a key hash is
|
||||
41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
|
||||
Otherwise leave this empty.
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ static inline void sync(void)
|
|||
|
||||
/*
|
||||
* We add memory barriers for __raw_readX / __raw_writeX accessors same way as
|
||||
* it is done for readX and writeX accessors as lots of U-boot driver uses
|
||||
* it is done for readX and writeX accessors as lots of U-Boot driver uses
|
||||
* __raw_readX / __raw_writeX instead of proper accessor with barrier.
|
||||
*/
|
||||
#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ config ARMV7_LPAE
|
|||
config ARMV7_SET_CORTEX_SMPEN
|
||||
bool
|
||||
help
|
||||
Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
|
||||
Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
|
||||
|
||||
config SPL_ARMV7_SET_CORTEX_SMPEN
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -311,11 +311,11 @@ ENTRY(psci_cpu_entry)
|
|||
bl psci_arch_cpu_entry
|
||||
|
||||
bl psci_get_cpu_id @ CPU ID => r0
|
||||
mov r2, r0 @ CPU ID => r2
|
||||
bl psci_get_context_id @ context id => r0
|
||||
mov r1, r0 @ context id => r1
|
||||
mov r0, r2 @ CPU ID => r0
|
||||
push {r0} @ save context id
|
||||
bl psci_get_cpu_id @ CPU ID => r0
|
||||
bl psci_get_target_pc @ target PC => r0
|
||||
pop {r1} @ context id => r1
|
||||
b _do_nonsec_entry
|
||||
ENDPROC(psci_cpu_entry)
|
||||
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ config ARMV8_PSCI
|
|||
bool "Enable PSCI support" if EXPERT
|
||||
help
|
||||
PSCI is Power State Coordination Interface defined by ARM.
|
||||
The PSCI in U-boot provides a general framework and each platform
|
||||
The PSCI in U-Boot provides a general framework and each platform
|
||||
can implement their own specific PSCI functions.
|
||||
Say Y here to enable PSCI support on ARMv8 platform.
|
||||
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ mcinitcmd: This environment variable is defined to initiate MC and DPL deploymen
|
|||
from the location where it is stored(NOR, NAND, SD, SATA, USB)during
|
||||
u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
|
||||
will be null and MC will not be booted and DPL will not be applied
|
||||
during U-boot booting.However the MC, DPC and DPL can be applied from
|
||||
during U-Boot booting.However the MC, DPC and DPL can be applied from
|
||||
console independently.
|
||||
The variable needs to be set from the console once and then on
|
||||
rebooting the parameters set in the variable will automatically be
|
||||
|
|
|
|||
|
|
@ -187,8 +187,10 @@ dtb-$(CONFIG_ARCH_S5P4418) += \
|
|||
s5p4418-nanopi2.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_MESON) += \
|
||||
meson-a1-ad401.dtb \
|
||||
meson-axg-s400.dtb \
|
||||
meson-axg-jethome-jethub-j100.dtb \
|
||||
meson-gxbb-kii-pro.dtb \
|
||||
meson-gxbb-nanopi-k2.dtb \
|
||||
meson-gxbb-odroidc2.dtb \
|
||||
meson-gxbb-nanopi-k2.dtb \
|
||||
|
|
@ -451,7 +453,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
|
|||
am4372-generic.dtb \
|
||||
am437x-cm-t43.dtb
|
||||
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
|
||||
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
|
||||
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_SOCFPGA) += \
|
||||
|
|
@ -1053,7 +1054,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
|
|||
r8a77965-ulcb-u-boot.dtb \
|
||||
r8a77965-salvator-x-u-boot.dtb \
|
||||
r8a77970-eagle-u-boot.dtb \
|
||||
r8a77970-v3msk-u-boot.dtb \
|
||||
r8a77980-condor-u-boot.dtb \
|
||||
r8a77980-v3hsk-u-boot.dtb \
|
||||
r8a77990-ebisu-u-boot.dtb \
|
||||
r8a77995-draak-u-boot.dtb
|
||||
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@
|
|||
};
|
||||
|
||||
partition@1 {
|
||||
label = "U-boot";
|
||||
label = "U-Boot";
|
||||
reg = <0x00080000 0x001e0000>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@
|
|||
reg = <0x0 0x200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "U-boot Env";
|
||||
label = "U-Boot Env";
|
||||
reg = <0x200000 0x10000>;
|
||||
};
|
||||
partition@210000 {
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
reg = <0x88200000 0x77e00000>;
|
||||
};
|
||||
|
||||
nvmxip-qspi@08000000 {
|
||||
nvmxip: nvmxip-qspi@08000000 {
|
||||
compatible = "nvmxip,qspi";
|
||||
reg = <0x08000000 0x2000000>;
|
||||
lba_shift = <9>;
|
||||
|
|
@ -106,6 +106,11 @@
|
|||
method = "smc";
|
||||
};
|
||||
|
||||
fwu-mdata {
|
||||
compatible = "u-boot,fwu-mdata-gpt";
|
||||
fwu-mdata-store = <&nvmxip>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -1,12 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dm8168-evm U-Boot Additions
|
||||
*
|
||||
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
|
||||
*/
|
||||
|
||||
/ {
|
||||
ocp {
|
||||
bootph-all;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/dts-v1/;
|
||||
|
||||
#include "dm816x.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "DM8168 EVM";
|
||||
compatible = "ti,dm8168-evm", "ti,dm8168";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000 /* 1 GB */
|
||||
0xc0000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
/* FDC6331L controlled by SD_POW pin */
|
||||
vmmcsd_fixed: fixedregulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dm816x_pinmux {
|
||||
mcspi1_pins: pinmux_mcspi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */
|
||||
DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */
|
||||
DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */
|
||||
DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc_pins: pinmux_mmc_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
|
||||
DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
|
||||
DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
|
||||
DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
|
||||
DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
|
||||
DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
|
||||
DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
|
||||
DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
|
||||
DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
|
||||
>;
|
||||
};
|
||||
|
||||
usb0_pins: pinmux_usb0_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: pinmux_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
extgpio0: pcf8575@20 {
|
||||
compatible = "nxp,pcf8575";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
extgpio1: pcf8575@20 {
|
||||
compatible = "nxp,pcf8575";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
partition@0 {
|
||||
label = "X-Loader";
|
||||
reg = <0 0x80000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "U-Boot";
|
||||
reg = <0x80000 0x1c0000>;
|
||||
};
|
||||
partition@1c0000 {
|
||||
label = "Environment";
|
||||
reg = <0x240000 0x40000>;
|
||||
};
|
||||
partition@280000 {
|
||||
label = "Kernel";
|
||||
reg = <0x280000 0x500000>;
|
||||
};
|
||||
partition@780000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x780000 0xf880000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mcspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi1_pins>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "w25x32";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* At least dm8168-evm rev c won't support multipoint, later may */
|
||||
&usb0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
mentor,multipoint = <0>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
mentor,multipoint = <0>;
|
||||
};
|
||||
|
|
@ -1,246 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
&scrm {
|
||||
main_fapll: main_fapll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm816-fapll-clock";
|
||||
reg = <0x400 0x40>;
|
||||
clocks = <&sys_clkin_ck &sys_clkin_ck>;
|
||||
clock-indices = <1>, <2>, <3>, <4>, <5>,
|
||||
<6>, <7>;
|
||||
clock-output-names = "main_pll_clk1",
|
||||
"main_pll_clk2",
|
||||
"main_pll_clk3",
|
||||
"main_pll_clk4",
|
||||
"main_pll_clk5",
|
||||
"main_pll_clk6",
|
||||
"main_pll_clk7";
|
||||
};
|
||||
|
||||
ddr_fapll: ddr_fapll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm816-fapll-clock";
|
||||
reg = <0x440 0x30>;
|
||||
clocks = <&sys_clkin_ck &sys_clkin_ck>;
|
||||
clock-indices = <1>, <2>, <3>, <4>;
|
||||
clock-output-names = "ddr_pll_clk1",
|
||||
"ddr_pll_clk2",
|
||||
"ddr_pll_clk3",
|
||||
"ddr_pll_clk4";
|
||||
};
|
||||
|
||||
video_fapll: video_fapll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm816-fapll-clock";
|
||||
reg = <0x470 0x30>;
|
||||
clocks = <&sys_clkin_ck &sys_clkin_ck>;
|
||||
clock-indices = <1>, <2>, <3>;
|
||||
clock-output-names = "video_pll_clk1",
|
||||
"video_pll_clk2",
|
||||
"video_pll_clk3";
|
||||
};
|
||||
|
||||
audio_fapll: audio_fapll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "ti,dm816-fapll-clock";
|
||||
reg = <0x4a0 0x30>;
|
||||
clocks = <&main_fapll 7>, < &sys_clkin_ck>;
|
||||
clock-indices = <1>, <2>, <3>, <4>, <5>;
|
||||
clock-output-names = "audio_pll_clk1",
|
||||
"audio_pll_clk2",
|
||||
"audio_pll_clk3",
|
||||
"audio_pll_clk4",
|
||||
"audio_pll_clk5";
|
||||
};
|
||||
};
|
||||
|
||||
&scrm_clocks {
|
||||
secure_32k_ck: secure_32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_32k_ck: sys_32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* 0x48180000 */
|
||||
&prcm_clocks {
|
||||
clkout_pre_ck: clkout_pre_ck@100 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
|
||||
&audio_fapll 1>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
clkout_div_ck: clkout_div_ck@100 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&clkout_pre_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,max-div = <8>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
clkout_ck: clkout_ck@100 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout_div_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
/* CM_DPLL clocks p1795 */
|
||||
sysclk1_ck: sysclk1_ck@300 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&main_fapll 1>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0300>;
|
||||
};
|
||||
|
||||
sysclk2_ck: sysclk2_ck@304 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&main_fapll 2>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0304>;
|
||||
};
|
||||
|
||||
sysclk3_ck: sysclk3_ck@308 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&main_fapll 3>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0308>;
|
||||
};
|
||||
|
||||
sysclk4_ck: sysclk4_ck@30c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&main_fapll 4>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x030c>;
|
||||
};
|
||||
|
||||
sysclk5_ck: sysclk5_ck@310 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sysclk4_ck>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x0310>;
|
||||
};
|
||||
|
||||
sysclk6_ck: sysclk6_ck@314 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&main_fapll 4>;
|
||||
ti,dividers = <2>, <4>;
|
||||
reg = <0x0314>;
|
||||
};
|
||||
|
||||
sysclk10_ck: sysclk10_ck@324 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&ddr_fapll 2>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x0324>;
|
||||
};
|
||||
|
||||
sysclk24_ck: sysclk24_ck@3b4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&main_fapll 5>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x03b4>;
|
||||
};
|
||||
|
||||
mpu_ck: mpu_ck@15dc {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sysclk2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x15dc>;
|
||||
};
|
||||
|
||||
audio_pll_a_ck: audio_pll_a_ck@35c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&audio_fapll 1>;
|
||||
ti,max-div = <7>;
|
||||
reg = <0x035c>;
|
||||
};
|
||||
|
||||
sysclk18_ck: sysclk18_ck@378 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
|
||||
reg = <0x0378>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck@390 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0390>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck@394 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0394>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck@398 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0398>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck@39c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x039c>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck@3a0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x03a0>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck@3a4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x03a4>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck@3a8 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x03a8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,517 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/omap.h>
|
||||
|
||||
/ {
|
||||
compatible = "ti,dm816";
|
||||
interrupt-parent = <&intc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupts = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the dm816x interconnect.
|
||||
* The real dm816x interconnect network is quite complex. Since
|
||||
* it will not bring real advantage to represent that in DT
|
||||
* for the moment, just use a fake OCP bus entry to represent
|
||||
* the whole bus hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x44000000 0x10000>;
|
||||
interrupts = <9 10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
prcm: prcm@48180000 {
|
||||
compatible = "ti,dm816-prcm", "simple-bus";
|
||||
reg = <0x48180000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x48180000 0x4000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@48140000 {
|
||||
compatible = "ti,dm816-scrm", "simple-bus";
|
||||
reg = <0x48140000 0x21000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#pinctrl-cells = <1>;
|
||||
ranges = <0 0x48140000 0x21000>;
|
||||
|
||||
dm816x_pinmux: pinmux@800 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x800 0x50a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#pinctrl-cells = <1>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xf>;
|
||||
};
|
||||
|
||||
/* Device Configuration Registers */
|
||||
scm_conf: syscon@600 {
|
||||
compatible = "syscon", "simple-bus";
|
||||
reg = <0x600 0x110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x600 0x110>;
|
||||
|
||||
usb_phy0: usb-phy@20 {
|
||||
compatible = "ti,dm8168-usb-phy";
|
||||
reg = <0x20 0x8>;
|
||||
reg-names = "phy";
|
||||
clocks = <&main_fapll 6>;
|
||||
clock-names = "refclk";
|
||||
#phy-cells = <0>;
|
||||
syscon = <&scm_conf>;
|
||||
};
|
||||
|
||||
usb_phy1: usb-phy@28 {
|
||||
compatible = "ti,dm8168-usb-phy";
|
||||
reg = <0x28 0x8>;
|
||||
reg-names = "phy";
|
||||
clocks = <&main_fapll 6>;
|
||||
clock-names = "refclk";
|
||||
#phy-cells = <0>;
|
||||
syscon = <&scm_conf>;
|
||||
};
|
||||
};
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
|
||||
reg = <0x49000000 0x10000>,
|
||||
<0x44e10f90 0x40>;
|
||||
interrupts = <12 13 14>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,816-elm";
|
||||
ti,hwmods = "elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
gpio1: gpio@48032000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
ti,gpio-always-on;
|
||||
reg = <0x48032000 0x1000>;
|
||||
interrupts = <96>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@4804c000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
ti,gpio-always-on;
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupts = <98>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
reg = <0x50000000 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <100>;
|
||||
dmas = <&edma 52>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <6>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48028000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
ti,hwmods = "i2c1";
|
||||
reg = <0x48028000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <70>;
|
||||
dmas = <&edma 58 &edma 59>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
i2c2: i2c@4802a000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
ti,hwmods = "i2c2";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <71>;
|
||||
dmas = <&edma 60 &edma 61>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@48200000 {
|
||||
compatible = "ti,dm816-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
rtc: rtc@480c0000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0x480c0000 0x1000>;
|
||||
interrupts = <75 76>;
|
||||
ti,hwmods = "rtc";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480c8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480c8000 0x2000>;
|
||||
interrupts = <77>;
|
||||
ti,hwmods = "mailbox";
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <12>;
|
||||
mbox_dsp: mbox-dsp {
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spinbox: spinbox@480ca000 {
|
||||
compatible = "ti,omap4-hwspinlock";
|
||||
reg = <0x480ca000 0x2000>;
|
||||
ti,hwmods = "spinbox";
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
mdio: mdio@4a100800 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4a100800 0x100>;
|
||||
ti,hwmods = "davinci_mdio";
|
||||
bus_freq = <1000000>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <1>;
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@4a100000 {
|
||||
compatible = "ti,dm816-emac";
|
||||
ti,hwmods = "emac0";
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a100900 0x3700>;
|
||||
clocks = <&sysclk24_ck>;
|
||||
syscon = <&scm_conf>;
|
||||
ti,davinci-ctrl-reg-offset = <0>;
|
||||
ti,davinci-ctrl-mod-reg-offset = <0x900>;
|
||||
ti,davinci-ctrl-ram-offset = <0x2000>;
|
||||
ti,davinci-ctrl-ram-size = <0x2000>;
|
||||
interrupts = <40 41 42 43>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@4a120000 {
|
||||
compatible = "ti,dm816-emac";
|
||||
ti,hwmods = "emac1";
|
||||
reg = <0x4a120000 0x4000>;
|
||||
clocks = <&sysclk24_ck>;
|
||||
syscon = <&scm_conf>;
|
||||
ti,davinci-ctrl-reg-offset = <0>;
|
||||
ti,davinci-ctrl-mod-reg-offset = <0x900>;
|
||||
ti,davinci-ctrl-ram-offset = <0x2000>;
|
||||
ti,davinci-ctrl-ram-size = <0x2000>;
|
||||
interrupts = <44 45 46 47>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
mcspi1: spi@48030000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
reg = <0x48030000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <65>;
|
||||
ti,spi-num-cs = <4>;
|
||||
ti,hwmods = "mcspi1";
|
||||
dmas = <&edma 16 &edma 17
|
||||
&edma 18 &edma 19
|
||||
&edma 20 &edma 21
|
||||
&edma 22 &edma 23>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1",
|
||||
"tx2", "rx2", "tx3", "rx3";
|
||||
};
|
||||
|
||||
mmc1: mmc@48060000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x48060000 0x11000>;
|
||||
ti,hwmods = "mmc1";
|
||||
interrupts = <64>;
|
||||
dmas = <&edma 24 &edma 25>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
timer1: timer@4802e000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x4802e000 0x2000>;
|
||||
interrupts = <67>;
|
||||
ti,hwmods = "timer1";
|
||||
ti,timer-alwon;
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48040000 0x2000>;
|
||||
interrupts = <68>;
|
||||
ti,hwmods = "timer2";
|
||||
};
|
||||
|
||||
timer3: timer@48042000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48042000 0x2000>;
|
||||
interrupts = <69>;
|
||||
ti,hwmods = "timer3";
|
||||
};
|
||||
|
||||
timer4: timer@48044000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48044000 0x2000>;
|
||||
interrupts = <92>;
|
||||
ti,hwmods = "timer4";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer5: timer@48046000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48046000 0x2000>;
|
||||
interrupts = <93>;
|
||||
ti,hwmods = "timer5";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer6: timer@48048000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x48048000 0x2000>;
|
||||
interrupts = <94>;
|
||||
ti,hwmods = "timer6";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer7: timer@4804a000 {
|
||||
compatible = "ti,dm816-timer";
|
||||
reg = <0x4804a000 0x2000>;
|
||||
interrupts = <95>;
|
||||
ti,hwmods = "timer7";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
uart1: serial@48020000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
reg = <0x48020000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <72>;
|
||||
dmas = <&edma 26 &edma 27>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart2: serial@48022000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
reg = <0x48022000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <73>;
|
||||
dmas = <&edma 28 &edma 29>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart3: serial@48024000 {
|
||||
compatible = "ti,am3352-uart", "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
reg = <0x48024000 0x2000>;
|
||||
clock-frequency = <48000000>;
|
||||
interrupts = <74>;
|
||||
dmas = <&edma 30 &edma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
/* NOTE: USB needs a transceiver driver for phys to work */
|
||||
usb: usb_otg_hs@47401000 {
|
||||
compatible = "ti,am33xx-usb";
|
||||
reg = <0x47401000 0x400000>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,hwmods = "usb_otg_hs";
|
||||
|
||||
usb0: usb@47401000 {
|
||||
compatible = "ti,musb-dm816";
|
||||
reg = <0x47401400 0x400
|
||||
0x47401000 0x200>;
|
||||
reg-names = "mc", "control";
|
||||
interrupts = <18>;
|
||||
interrupt-names = "mc";
|
||||
dr_mode = "host";
|
||||
interface-type = <0>;
|
||||
phys = <&usb_phy0>;
|
||||
phy-names = "usb2-phy";
|
||||
mentor,multipoint = <1>;
|
||||
mentor,num-eps = <16>;
|
||||
mentor,ram-bits = <12>;
|
||||
mentor,power = <500>;
|
||||
|
||||
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
||||
&cppi41dma 2 0 &cppi41dma 3 0
|
||||
&cppi41dma 4 0 &cppi41dma 5 0
|
||||
&cppi41dma 6 0 &cppi41dma 7 0
|
||||
&cppi41dma 8 0 &cppi41dma 9 0
|
||||
&cppi41dma 10 0 &cppi41dma 11 0
|
||||
&cppi41dma 12 0 &cppi41dma 13 0
|
||||
&cppi41dma 14 0 &cppi41dma 0 1
|
||||
&cppi41dma 1 1 &cppi41dma 2 1
|
||||
&cppi41dma 3 1 &cppi41dma 4 1
|
||||
&cppi41dma 5 1 &cppi41dma 6 1
|
||||
&cppi41dma 7 1 &cppi41dma 8 1
|
||||
&cppi41dma 9 1 &cppi41dma 10 1
|
||||
&cppi41dma 11 1 &cppi41dma 12 1
|
||||
&cppi41dma 13 1 &cppi41dma 14 1>;
|
||||
dma-names =
|
||||
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
||||
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
||||
"rx14", "rx15",
|
||||
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
||||
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
||||
"tx14", "tx15";
|
||||
};
|
||||
|
||||
usb1: usb@47401800 {
|
||||
compatible = "ti,musb-dm816";
|
||||
reg = <0x47401c00 0x400
|
||||
0x47401800 0x200>;
|
||||
reg-names = "mc", "control";
|
||||
interrupts = <19>;
|
||||
interrupt-names = "mc";
|
||||
dr_mode = "host";
|
||||
interface-type = <0>;
|
||||
phys = <&usb_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
mentor,multipoint = <1>;
|
||||
mentor,num-eps = <16>;
|
||||
mentor,ram-bits = <12>;
|
||||
mentor,power = <500>;
|
||||
|
||||
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
||||
&cppi41dma 17 0 &cppi41dma 18 0
|
||||
&cppi41dma 19 0 &cppi41dma 20 0
|
||||
&cppi41dma 21 0 &cppi41dma 22 0
|
||||
&cppi41dma 23 0 &cppi41dma 24 0
|
||||
&cppi41dma 25 0 &cppi41dma 26 0
|
||||
&cppi41dma 27 0 &cppi41dma 28 0
|
||||
&cppi41dma 29 0 &cppi41dma 15 1
|
||||
&cppi41dma 16 1 &cppi41dma 17 1
|
||||
&cppi41dma 18 1 &cppi41dma 19 1
|
||||
&cppi41dma 20 1 &cppi41dma 21 1
|
||||
&cppi41dma 22 1 &cppi41dma 23 1
|
||||
&cppi41dma 24 1 &cppi41dma 25 1
|
||||
&cppi41dma 26 1 &cppi41dma 27 1
|
||||
&cppi41dma 28 1 &cppi41dma 29 1>;
|
||||
dma-names =
|
||||
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
||||
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
||||
"rx14", "rx15",
|
||||
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
||||
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
||||
"tx14", "tx15";
|
||||
};
|
||||
|
||||
cppi41dma: dma-controller@47402000 {
|
||||
compatible = "ti,am3359-cppi41";
|
||||
reg = <0x47400000 0x1000
|
||||
0x47402000 0x1000
|
||||
0x47403000 0x1000
|
||||
0x47404000 0x4000>;
|
||||
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
||||
interrupts = <17>;
|
||||
interrupt-names = "glue";
|
||||
#dma-cells = <2>;
|
||||
#dma-channels = <30>;
|
||||
#dma-requests = <256>;
|
||||
};
|
||||
};
|
||||
|
||||
wd_timer2: wd_timer@480c2000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer";
|
||||
reg = <0x480c2000 0x1000>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "dm816x-clocks.dtsi"
|
||||
|
|
@ -51,7 +51,7 @@
|
|||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* PSCI node is not added default, U-Boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "psci";
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
||||
/include/ "fsl-ls1043a.dtsi"
|
||||
#include "fsl-ls1043a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1043A QDS Board";
|
||||
|
|
|
|||
5
arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi
Normal file
5
arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 NXP */
|
||||
|
||||
#include "fsl-ls1043a-u-boot.dtsi"
|
||||
|
||||
|
|
@ -9,13 +9,17 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "fsl-ls1043a.dtsi"
|
||||
#include "fsl-ls1043a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1043A RDB Board";
|
||||
|
||||
aliases {
|
||||
spi1 = &dspi0;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
|
|||
19
arch/arm/dts/fsl-ls1043a-u-boot.dtsi
Normal file
19
arch/arm/dts/fsl-ls1043a-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 NXP */
|
||||
|
||||
&duart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&duart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&duart3 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
|
|
@ -8,7 +8,9 @@
|
|||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
||||
/include/ "skeleton64.dtsi"
|
||||
#include "skeleton64.dtsi"
|
||||
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1043a";
|
||||
|
|
@ -223,28 +225,32 @@
|
|||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(1)>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(1)>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(1)>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(1)>;
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
|
|
|
|||
5
arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi
Normal file
5
arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 NXP */
|
||||
|
||||
#include "fsl-ls1046a-u-boot.dtsi"
|
||||
|
||||
|
|
@ -2,22 +2,42 @@
|
|||
/*
|
||||
* Device Tree Include file for NXP Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2019 NXP
|
||||
* Copyright 2019-2023 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "fsl-ls1046a.dtsi"
|
||||
#include "fsl-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A FRWY Board";
|
||||
|
||||
aliases {
|
||||
spi0 = &qspi;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -34,3 +54,49 @@
|
|||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "fsl-ls1046-post.dtsi"
|
||||
|
||||
&fman0 {
|
||||
ethernet@e0000 {
|
||||
phy-handle = <&qsgmii_phy4>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&qsgmii_phy2>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&qsgmii_phy1>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&qsgmii_phy3>;
|
||||
phy-connection-type = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
qsgmii_phy1: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
qsgmii_phy2: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
qsgmii_phy3: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
qsgmii_phy4: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
* Mingkai Hu <Mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
/include/ "fsl-ls1046a.dtsi"
|
||||
#include "fsl-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A QDS Board";
|
||||
|
|
|
|||
5
arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi
Normal file
5
arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 NXP */
|
||||
|
||||
#include "fsl-ls1046a-u-boot.dtsi"
|
||||
|
||||
|
|
@ -9,17 +9,29 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "fsl-ls1046a.dtsi"
|
||||
#include "fsl-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A RDB Board";
|
||||
|
||||
aliases {
|
||||
spi0 = &qspi;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
|
|
|
|||
19
arch/arm/dts/fsl-ls1046a-u-boot.dtsi
Normal file
19
arch/arm/dts/fsl-ls1046a-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/* Copyright 2023 NXP */
|
||||
|
||||
&duart0 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&duart2 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&duart3 {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
|
|
@ -8,7 +8,9 @@
|
|||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
/include/ "skeleton64.dtsi"
|
||||
#include "skeleton64.dtsi"
|
||||
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1046a";
|
||||
|
|
@ -222,29 +224,37 @@
|
|||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(2)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(2)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(2)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
||||
QORIQ_CLK_PLL_DIV(2)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
|
|
|
|||
30
arch/arm/dts/meson-a1-ad401.dts
Normal file
30
arch/arm/dts/meson-a1-ad401.dts
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-a1.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,ad401", "amlogic,a1";
|
||||
model = "Amlogic Meson A1 AD401 Development Board";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart_AO_B;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x8000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart_AO_B {
|
||||
status = "okay";
|
||||
};
|
||||
161
arch/arm/dts/meson-a1.dtsi
Normal file
161
arch/arm/dts/meson-a1.dtsi
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/meson-a1-gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,a1";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a35";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
};
|
||||
|
||||
l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x800000>;
|
||||
alignment = <0x0 0x400000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
sm: secure-monitor {
|
||||
compatible = "amlogic,meson-gxbb-sm";
|
||||
|
||||
pwrc: power-controller {
|
||||
compatible = "amlogic,meson-a1-pwrc";
|
||||
#power-domain-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
apb: bus@fe000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xfe000000 0x0 0x1000000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
|
||||
|
||||
reset: reset-controller@0 {
|
||||
compatible = "amlogic,meson-a1-reset";
|
||||
reg = <0x0 0x0 0x0 0x8c>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
periphs_pinctrl: pinctrl@400 {
|
||||
compatible = "amlogic,meson-a1-periphs-pinctrl";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio: bank@400 {
|
||||
reg = <0x0 0x0400 0x0 0x003c>,
|
||||
<0x0 0x0480 0x0 0x0118>;
|
||||
reg-names = "mux", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&periphs_pinctrl 0 0 62>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
uart_AO: serial@1c00 {
|
||||
compatible = "amlogic,meson-gx-uart",
|
||||
"amlogic,meson-ao-uart";
|
||||
reg = <0x0 0x1c00 0x0 0x18>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>, <&xtal>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart_AO_B: serial@2000 {
|
||||
compatible = "amlogic,meson-gx-uart",
|
||||
"amlogic,meson-ao-uart";
|
||||
reg = <0x0 0x2000 0x0 0x18>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>, <&xtal>, <&xtal>;
|
||||
clock-names = "xtal", "pclk", "baud";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff901000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x0 0xff901000 0x0 0x1000>,
|
||||
<0x0 0xff902000 0x0 0x2000>,
|
||||
<0x0 0xff904000 0x0 0x2000>,
|
||||
<0x0 0xff906000 0x0 0x2000>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
xtal: xtal-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xtal";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
*/
|
||||
|
||||
/ {
|
||||
/* Keep HW order from U-boot */
|
||||
/* Keep HW order from U-Boot */
|
||||
aliases {
|
||||
/delete-property/ mmc0;
|
||||
/delete-property/ mmc1;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
*/
|
||||
|
||||
/ {
|
||||
/* Keep HW order from U-boot */
|
||||
/* Keep HW order from U-Boot */
|
||||
aliases {
|
||||
/delete-property/ mmc0;
|
||||
/delete-property/ mmc1;
|
||||
|
|
|
|||
13
arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi
Normal file
13
arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#include "meson-gx-u-boot.dtsi"
|
||||
|
||||
ðmac {
|
||||
snps,reset-gpio = <&gpio GPIOZ_14 0>;
|
||||
snps,reset-delays-us = <0>, <10000>, <1000000>;
|
||||
snps,reset-active-low;
|
||||
};
|
||||
140
arch/arm/dts/meson-gxbb-kii-pro.dts
Normal file
140
arch/arm/dts/meson-gxbb-kii-pro.dts
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2019 Mohammad Rasim <mohammad.rasim96@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-p20x.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/sound/meson-aiu.h>
|
||||
|
||||
/ {
|
||||
compatible = "videostrong,kii-pro", "amlogic,meson-gxbb";
|
||||
model = "Videostrong KII Pro";
|
||||
|
||||
spdif_dit: audio-codec-0 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "linux,spdif-dit";
|
||||
status = "okay";
|
||||
sound-name-prefix = "DIT";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led {
|
||||
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys-polled {
|
||||
compatible = "gpio-keys-polled";
|
||||
poll-interval = <20>;
|
||||
|
||||
button-reset {
|
||||
label = "reset";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "amlogic,gx-sound-card";
|
||||
model = "KII-PRO";
|
||||
assigned-clocks = <&clkc CLKID_MPLL0>,
|
||||
<&clkc CLKID_MPLL1>,
|
||||
<&clkc CLKID_MPLL2>;
|
||||
assigned-clock-parents = <0>, <0>, <0>;
|
||||
assigned-clock-rates = <294912000>,
|
||||
<270950400>,
|
||||
<393216000>;
|
||||
|
||||
dai-link-0 {
|
||||
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
|
||||
};
|
||||
|
||||
dai-link-1 {
|
||||
sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
|
||||
};
|
||||
|
||||
dai-link-2 {
|
||||
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
|
||||
codec-0 {
|
||||
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
|
||||
};
|
||||
};
|
||||
|
||||
dai-link-3 {
|
||||
sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
|
||||
|
||||
codec-0 {
|
||||
sound-dai = <&spdif_dit>;
|
||||
};
|
||||
};
|
||||
|
||||
dai-link-4 {
|
||||
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
|
||||
|
||||
codec-0 {
|
||||
sound-dai = <&hdmi_tx>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&aiu {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spdif_out_y_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
ðmac {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ð_rmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <ð_phy0>;
|
||||
phy-mode = "rmii";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth_phy0: ethernet-phy@0 {
|
||||
/* IC Plus IP101GR (0x02430c54) */
|
||||
reg = <0>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <10000>;
|
||||
reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ir {
|
||||
linux,rc-map-name = "rc-videostrong-kii-pro";
|
||||
};
|
||||
|
||||
&uart_A {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
|
||||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm4335a0";
|
||||
shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
|
||||
host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <2000000>;
|
||||
clocks = <&wifi32k>;
|
||||
clock-names = "lpo";
|
||||
};
|
||||
};
|
||||
|
|
@ -126,6 +126,8 @@
|
|||
phy-handle = <&phy0>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0007.c0f0",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
|
||||
reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
|
||||
|
|
|
|||
65
arch/arm/dts/r8a77970-v3msk-u-boot.dts
Normal file
65
arch/arm/dts/r8a77970-v3msk-u-boot.dts
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the V3MSK board
|
||||
*
|
||||
* Copyright (C) 2019 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#include "r8a77970-v3msk.dts"
|
||||
#include "r8a77970-u-boot.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
spi0 = &rpc;
|
||||
};
|
||||
|
||||
cpld {
|
||||
compatible = "renesas,v3msk-cpld";
|
||||
status = "okay";
|
||||
gpio-mdc = <&gpio1 21 0>;
|
||||
gpio-mosi = <&gpio1 22 0>;
|
||||
gpio-miso = <&gpio1 23 0>;
|
||||
gpio-enablez = <&gpio1 19 0>;
|
||||
/* Disable V3MSK Videobox Mini CANFD PHY */
|
||||
gpios = <&gpio0 12 0>, <&gpio0 14 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb0_pins: avb {
|
||||
mux {
|
||||
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
num-cs = <1>;
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
flash0: spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
303
arch/arm/dts/r8a77970-v3msk.dts
Normal file
303
arch/arm/dts/r8a77970-v3msk.dts
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the V3M Starter Kit board
|
||||
*
|
||||
* Copyright (C) 2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77970.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas V3M Starter Kit board";
|
||||
compatible = "renesas,v3msk", "renesas,r8a77970";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
serial0 = &scif0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <&vcc_d3_3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
osc5_clk: osc5-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
vcc_d1_8v: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_D1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_d3_3v: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_vddq_vin0: regulator-2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC_VDDQ_VIN0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
rx-internal-delay-ps = <1800>;
|
||||
tx-internal-delay-ps = <2000>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&osc5_clk>;
|
||||
clock-names = "du.0", "dclkin.0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hdmi@39{
|
||||
compatible = "adi,adv7511w";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
avdd-supply = <&vcc_d1_8v>;
|
||||
dvdd-supply = <&vcc_d1_8v>;
|
||||
pvdd-supply = <&vcc_d1_8v>;
|
||||
bgvdd-supply = <&vcc_d1_8v>;
|
||||
dvdd-3v-supply = <&vcc_d3_3v>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_d3_3v>;
|
||||
vqmmc-supply = <&vcc_vddq_vin0>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb_pins: avb0 {
|
||||
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
|
||||
function = "avb0";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
mmc_pins: mmc_3_3v {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
groups = "qspi0_ctrl", "qspi0_data4";
|
||||
function = "qspi0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cr7@40000 {
|
||||
reg = <0x00040000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa3@c0000 {
|
||||
reg = <0x000c0000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@140000 {
|
||||
reg = <0x00140000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x460000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x0c0000>;
|
||||
read-only;
|
||||
};
|
||||
uboot-env@700000 {
|
||||
reg = <0x00700000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
42
arch/arm/dts/r8a77980-v3hsk-u-boot.dts
Normal file
42
arch/arm/dts/r8a77980-v3hsk-u-boot.dts
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the Eagle board
|
||||
*
|
||||
* Copyright (C) 2019 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#include "r8a77980-v3hsk.dts"
|
||||
#include "r8a77980-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
spi0 = &rpc;
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
num-cs = <1>;
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
flash0: spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
cpld {
|
||||
compatible = "renesas,v3hsk-cpld";
|
||||
reg = <0x70>;
|
||||
u-boot,i2c-offset-len = <2>;
|
||||
};
|
||||
};
|
||||
292
arch/arm/dts/r8a77980-v3hsk.dts
Normal file
292
arch/arm/dts/r8a77980-v3hsk.dts
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the V3H Starter Kit board
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77980.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Renesas V3H Starter Kit board";
|
||||
compatible = "renesas,v3hsk", "renesas,r8a77980";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
serial0 = &scif0;
|
||||
ethernet0 = &gether;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <&vcc3v3_d5>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0 0x48000000 0 0x78000000>;
|
||||
};
|
||||
|
||||
osc1_clk: osc1-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
|
||||
vcc1v8_d4: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC1V8_D4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc3v3_d5: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC3V3_D5";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&osc1_clk>;
|
||||
clock-names = "du.0", "dclkin.0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
||||
&extalr_clk {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&gether {
|
||||
pinctrl-0 = <&gether_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
renesas,no-ether-link;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
avdd-supply = <&vcc1v8_d4>;
|
||||
dvdd-supply = <&vcc1v8_d4>;
|
||||
pvdd-supply = <&vcc1v8_d4>;
|
||||
bgvdd-supply = <&vcc1v8_d4>;
|
||||
dvdd-3v-supply = <&vcc3v3_d5>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
gether_pins: gether {
|
||||
groups = "gether_mdio_a", "gether_rgmii",
|
||||
"gether_txcrefclk", "gether_txcrefclk_mega";
|
||||
function = "gether";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
qspi0_pins: qspi0 {
|
||||
groups = "qspi0_ctrl", "qspi0_data4";
|
||||
function = "qspi0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
pinctrl-0 = <&qspi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spansion,s25fs512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
bootparam@0 {
|
||||
reg = <0x00000000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cr7@40000 {
|
||||
reg = <0x00040000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa3@c0000 {
|
||||
reg = <0x000c0000 0x080000>;
|
||||
read-only;
|
||||
};
|
||||
bl2@140000 {
|
||||
reg = <0x00140000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
cert_header_sa6@180000 {
|
||||
reg = <0x00180000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
bl31@1c0000 {
|
||||
reg = <0x001c0000 0x460000>;
|
||||
read-only;
|
||||
};
|
||||
uboot@640000 {
|
||||
reg = <0x00640000 0x0c0000>;
|
||||
read-only;
|
||||
};
|
||||
uboot-env@700000 {
|
||||
reg = <0x00700000 0x040000>;
|
||||
read-only;
|
||||
};
|
||||
dtb@740000 {
|
||||
reg = <0x00740000 0x080000>;
|
||||
};
|
||||
kernel@7c0000 {
|
||||
reg = <0x007c0000 0x1400000>;
|
||||
};
|
||||
user@1bc0000 {
|
||||
reg = <0x01bc0000 0x2440000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
};
|
||||
|
||||
&gmac2phy {
|
||||
/* Integrated PHY unsupported by U-boot */
|
||||
/* Integrated PHY unsupported by U-Boot */
|
||||
status = "broken";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -984,7 +984,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* U-boot Specific Change
|
||||
* U-Boot Specific Change
|
||||
*
|
||||
* The OTG controller must come after the USB host pair for it
|
||||
* to work. This is likely due to lack of support for the USB
|
||||
|
|
|
|||
|
|
@ -28,11 +28,6 @@
|
|||
button-gpio = <&gpioa 0 0>;
|
||||
};
|
||||
|
||||
dsi_host: dsi_host {
|
||||
compatible = "synopsys,dw-mipi-dsi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
led1 {
|
||||
compatible = "st,led1";
|
||||
led-gpio = <&gpioj 5 0>;
|
||||
|
|
|
|||
|
|
@ -6,6 +6,114 @@
|
|||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
&pinctrl {
|
||||
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
|
||||
<STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_sleep_pins_a: i2c1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_pins_a: i2c5-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_sleep_pins_a: i2c5-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
mcp23017_pins_a: mcp23017-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_pins_a: pwm3-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_sleep_pins_a: pwm3-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm4_pins_a: pwm4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm4_sleep_pins_a: pwm4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm8_pins_a: pwm8-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm8_sleep_pins_a: pwm8-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm14_pins_a: pwm14-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm14_sleep_pins_a: pwm14-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
|
|
@ -108,6 +216,36 @@
|
|||
};
|
||||
};
|
||||
|
||||
spi5_pins_a: spi5-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
|
||||
<STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi5_sleep_pins_a: spi5-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
|
||||
<STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
|
||||
<STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
|
||||
};
|
||||
};
|
||||
|
||||
stm32g0_intn_pins_a: stm32g0-intn-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -33,5 +33,36 @@
|
|||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc_1: adc@48003000 {
|
||||
compatible = "st,stm32mp13-adc-core";
|
||||
reg = <0x48003000 0x400>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
|
||||
clock-names = "bus", "adc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
adc1: adc@0 {
|
||||
compatible = "st,stm32mp13-adc";
|
||||
#io-channel-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&adc_1>;
|
||||
interrupts = <0>;
|
||||
dmas = <&dmamux1 9 0x400 0x80000001>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
|
||||
channel@18 {
|
||||
reg = <18>;
|
||||
label = "vrefint";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
user-pa13 {
|
||||
button-user {
|
||||
label = "User-PA13";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
|
|
@ -59,6 +59,22 @@
|
|||
};
|
||||
};
|
||||
|
||||
v3v3_sw: v3v3-sw {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3v3_sw";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_adc: vdd-adc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_adc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_sd: vdd-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_sd";
|
||||
|
|
@ -66,6 +82,101 @@
|
|||
regulator-max-microvolt = <2900000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_usb: vdd-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adc_1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&adc1_usb_cc_pins_a>;
|
||||
vdda-supply = <&vdd_adc>;
|
||||
vref-supply = <&vdd_adc>;
|
||||
status = "okay";
|
||||
adc1: adc@0 {
|
||||
status = "okay";
|
||||
/*
|
||||
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
|
||||
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
||||
* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
|
||||
* Use arbitrary margin here (e.g. 5us).
|
||||
*/
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
channel@12 {
|
||||
reg = <12>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <96>;
|
||||
i2c-scl-falling-time-ns = <3>;
|
||||
clock-frequency = <1000000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
mcp23017: pinctrl@21 {
|
||||
compatible = "microchip,mcp23017";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&gpiog>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcp23017_pins_a>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
microchip,irq-mirror;
|
||||
};
|
||||
|
||||
typec@53 {
|
||||
compatible = "st,stm32g0-typec";
|
||||
reg = <0x53>;
|
||||
/* Alert pin on PI2 */
|
||||
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
/* Internal pull-up on PI2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&stm32g0_intn_pins_a>;
|
||||
firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
|
||||
port {
|
||||
con_usb_c_g0_ep: endpoint {
|
||||
remote-endpoint = <&usbotg_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c5_pins_a>;
|
||||
pinctrl-1 = <&i2c5_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <170>;
|
||||
i2c-scl-falling-time-ns = <5>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
|
|
@ -90,8 +201,130 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&spi5 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&spi5_pins_a>;
|
||||
pinctrl-1 = <&spi5_sleep_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm3_pins_a>;
|
||||
pinctrl-1 = <&pwm3_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers4 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm4_pins_a>;
|
||||
pinctrl-1 = <&pwm4_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@3 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers8 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm8_pins_a>;
|
||||
pinctrl-1 = <&pwm8_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@7 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers14 {
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm14_pins_a>;
|
||||
pinctrl-1 = <&pwm14_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@13 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* onboard HUB */
|
||||
hub@1 {
|
||||
compatible = "usb424,2514";
|
||||
reg = <1>;
|
||||
vdd-supply = <&v3v3_sw>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
port {
|
||||
usbotg_hs_ep: endpoint {
|
||||
remote-endpoint = <&con_usb_c_g0_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,current-boost-microamp = <1000>;
|
||||
st,decrease-hs-slew-rate;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <11>;
|
||||
st,trim-hs-impedance = <2>;
|
||||
st,tune-squelch-level = <1>;
|
||||
st,enable-hs-rx-gain-eq;
|
||||
st,no-hs-ftime-ctrl;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,current-boost-microamp = <1000>;
|
||||
st,decrease-hs-slew-rate;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <11>;
|
||||
st,trim-hs-impedance = <2>;
|
||||
st,tune-squelch-level = <1>;
|
||||
st,enable-hs-rx-gain-eq;
|
||||
st,no-hs-ftime-ctrl;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1261,7 +1261,7 @@
|
|||
};
|
||||
|
||||
qspi_bk1_pins_a: qspi-bk1-0 {
|
||||
pins1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
||||
|
|
@ -1270,12 +1270,6 @@
|
|||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
|
||||
|
|
@ -1283,13 +1277,12 @@
|
|||
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
|
||||
<STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
|
||||
<STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk2_pins_a: qspi-bk2-0 {
|
||||
pins1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
||||
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
||||
|
|
@ -1298,12 +1291,6 @@
|
|||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
|
||||
|
|
@ -1311,8 +1298,37 @@
|
|||
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
|
||||
<STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
|
||||
<STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
|
||||
<STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
|
||||
<STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
|
||||
<STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */
|
||||
};
|
||||
};
|
||||
|
||||
qspi_cs1_pins_a: qspi-cs1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
|
||||
};
|
||||
};
|
||||
|
||||
qspi_cs2_pins_a: qspi-cs2-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1693,7 +1693,6 @@
|
|||
ranges = <0 0x50002000 0xa400>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&exti 0x60 0xff>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
gpio-controller;
|
||||
|
|
@ -1822,7 +1821,6 @@
|
|||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-z-pinctrl";
|
||||
ranges = <0 0x54004000 0x400>;
|
||||
pins-are-numbered;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&exti 0x60 0xff>;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
i2c3 = &i2c4;
|
||||
usb0 = &usbotg_hs;
|
||||
};
|
||||
|
||||
config {
|
||||
u-boot,boot-led = "heartbeat";
|
||||
u-boot,error-led = "error";
|
||||
|
|
|
|||
|
|
@ -4,3 +4,10 @@
|
|||
*/
|
||||
|
||||
#include "stm32mp157a-dk1-scmi-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
fwu-mdata {
|
||||
compatible = "u-boot,fwu-mdata-gpt";
|
||||
fwu-mdata-store = <&sdmmc1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,4 +14,129 @@
|
|||
spi0 = &qspi;
|
||||
usb0 = &usbotg_hs;
|
||||
};
|
||||
|
||||
fwu-mdata {
|
||||
compatible = "u-boot,fwu-mdata-gpt";
|
||||
fwu-mdata-store = <&sdmmc1>;
|
||||
};
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
bootph-pre-ram;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "fsbl1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "fsbl2";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "metadata1";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@c0000 {
|
||||
label = "metadata2";
|
||||
reg = <0x000c0000 0x00040000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "fip-a";
|
||||
reg = <0x00100000 0x00400000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "fip-b";
|
||||
reg = <0x00500000 0x00400000>;
|
||||
};
|
||||
partition@900000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x00900000 0x00080000>;
|
||||
};
|
||||
partition@980000 {
|
||||
label = "nor-user";
|
||||
reg = <0x00980000 0x03680000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fmc {
|
||||
nand-controller@4,0 {
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "fsbl1";
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "fsbl2";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "metadata1";
|
||||
reg = <0x00100000 0x00080000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "metadata2";
|
||||
reg = <0x00180000 0x00080000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "fip-a1";
|
||||
reg = <0x00200000 0x00400000>;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "fip-a2";
|
||||
reg = <0x00600000 0x00400000>;
|
||||
};
|
||||
partition@a00000 {
|
||||
label = "fip-b1";
|
||||
reg = <0x00a00000 0x00400000>;
|
||||
};
|
||||
partition@e00000 {
|
||||
label = "fip-b2";
|
||||
reg = <0x00e00000 0x00400000>;
|
||||
};
|
||||
partition@1200000 {
|
||||
label = "UBI";
|
||||
reg = <0x01200000 0x3ee00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
&qspi_clk_pins_a {
|
||||
bootph-pre-ram;
|
||||
pins {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_bk1_pins_a {
|
||||
bootph-pre-ram;
|
||||
pins1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
pins2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi_bk2_pins_a {
|
||||
bootph-pre-ram;
|
||||
pins1 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
pins2 {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,6 +23,103 @@
|
|||
|
||||
&flash0 {
|
||||
bootph-pre-ram;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
|
||||
partition@0 {
|
||||
label = "fsbl1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@80000 {
|
||||
label = "fsbl2";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "ssbl";
|
||||
reg = <0x00080000 0x00200000>;
|
||||
};
|
||||
partition@280000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x00280000 0x00080000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "nor-user";
|
||||
reg = <0x00300000 0x03d00000>;
|
||||
};
|
||||
#else
|
||||
partition@0 {
|
||||
label = "fsbl1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "fsbl2";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "fip";
|
||||
reg = <0x00080000 0x00400000>;
|
||||
};
|
||||
partition@480000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x00480000 0x00080000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "nor-user";
|
||||
reg = <0x00500000 0x03b00000>;
|
||||
};
|
||||
#endif
|
||||
};
|
||||
};
|
||||
|
||||
&fmc {
|
||||
nand-controller@4,0 {
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL)
|
||||
partition@0 {
|
||||
label = "fsbl";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "ssbl1";
|
||||
reg = <0x00200000 0x00200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "ssbl2";
|
||||
reg = <0x00400000 0x00200000>;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "UBI";
|
||||
reg = <0x00600000 0x3fa00000>;
|
||||
};
|
||||
#else
|
||||
partition@0 {
|
||||
label = "fsbl";
|
||||
reg = <0x00000000 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "fip1";
|
||||
reg = <0x00200000 0x00400000>;
|
||||
};
|
||||
partition@600000 {
|
||||
label = "fip2";
|
||||
reg = <0x00600000 0x00400000>;
|
||||
};
|
||||
partition@1200000 {
|
||||
label = "UBI";
|
||||
reg = <0x00a00000 0x3f600000>;
|
||||
};
|
||||
#endif
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
|
|
@ -55,4 +152,3 @@
|
|||
bootph-pre-ram;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include "stm32mp157c-ed1.dts"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/media/video-interfaces.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
|
||||
|
|
@ -90,7 +91,7 @@
|
|||
port {
|
||||
dcmi_0: endpoint {
|
||||
remote-endpoint = <&ov5640_0>;
|
||||
bus-type = <5>;
|
||||
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
|
|
@ -144,7 +145,7 @@
|
|||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
|
@ -255,8 +256,16 @@
|
|||
|
||||
&qspi {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
|
||||
pinctrl-0 = <&qspi_clk_pins_a
|
||||
&qspi_bk1_pins_a
|
||||
&qspi_cs1_pins_a
|
||||
&qspi_bk2_pins_a
|
||||
&qspi_cs2_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a
|
||||
&qspi_bk1_sleep_pins_a
|
||||
&qspi_cs1_sleep_pins_a
|
||||
&qspi_bk2_sleep_pins_a
|
||||
&qspi_cs2_sleep_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -393,6 +402,7 @@
|
|||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
|
||||
connector {
|
||||
compatible = "usb-a-connector";
|
||||
vbus-supply = <&vbus_sw>;
|
||||
|
|
|
|||
|
|
@ -429,8 +429,12 @@
|
|||
|
||||
&qspi {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
|
||||
pinctrl-0 = <&qspi_clk_pins_a
|
||||
&qspi_bk1_pins_a
|
||||
&qspi_cs1_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a
|
||||
&qspi_bk1_sleep_pins_a
|
||||
&qspi_cs1_sleep_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -92,6 +92,33 @@
|
|||
|
||||
&flash0 {
|
||||
bootph-pre-ram;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "fsbl1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "fsbl2";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "uboot";
|
||||
reg = <0x00080000 0x00160000>;
|
||||
};
|
||||
partition@900000 {
|
||||
label = "env1";
|
||||
reg = <0x001E0000 0x00010000>;
|
||||
};
|
||||
partition@980000 {
|
||||
label = "env2";
|
||||
reg = <0x001F0000 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
|
|
|
|||
|
|
@ -191,8 +191,12 @@
|
|||
|
||||
&qspi {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
|
||||
pinctrl-0 = <&qspi_clk_pins_a
|
||||
&qspi_bk1_pins_a
|
||||
&qspi_cs1_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a
|
||||
&qspi_bk1_sleep_pins_a
|
||||
&qspi_cs1_sleep_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,33 @@
|
|||
|
||||
&flash0 {
|
||||
bootph-pre-ram;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "fsbl1";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "fsbl2";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "uboot";
|
||||
reg = <0x00080000 0x00160000>;
|
||||
};
|
||||
partition@900000 {
|
||||
label = "env1";
|
||||
reg = <0x001E0000 0x00010000>;
|
||||
};
|
||||
partition@980000 {
|
||||
label = "env2";
|
||||
reg = <0x001F0000 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@
|
|||
|
||||
sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "STM32MP1-DK";
|
||||
label = "STM32MP15-DK";
|
||||
routing =
|
||||
"Playback" , "MCLK",
|
||||
"Capture" , "MCLK",
|
||||
|
|
@ -149,7 +149,7 @@
|
|||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
|
|
@ -509,14 +509,12 @@
|
|||
sai2a: audio-controller@4400b004 {
|
||||
#clock-cells = <0>;
|
||||
dma-names = "tx";
|
||||
clocks = <&rcc SAI2_K>;
|
||||
clock-names = "sai_ck";
|
||||
status = "okay";
|
||||
|
||||
sai2a_port: port {
|
||||
sai2a_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_tx_endpoint>;
|
||||
format = "i2s";
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
|
|
@ -534,7 +532,7 @@
|
|||
sai2b_port: port {
|
||||
sai2b_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_rx_endpoint>;
|
||||
format = "i2s";
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
|
|
@ -74,8 +74,24 @@
|
|||
};
|
||||
|
||||
partition@500000 {
|
||||
label = "Ex-OPTEE";
|
||||
reg = <0x500000 0x200000>;
|
||||
label = "MDATA-Pri";
|
||||
reg = <0x500000 0x1000>;
|
||||
};
|
||||
|
||||
partition@530000 {
|
||||
label = "MDATA-Sec";
|
||||
reg = <0x530000 0x1000>;
|
||||
};
|
||||
|
||||
/* FWU Multi bank update partitions */
|
||||
partition@600000 {
|
||||
label = "FIP-Bank0";
|
||||
reg = <0x600000 0x400000>;
|
||||
};
|
||||
|
||||
partition@a00000 {
|
||||
label = "FIP-Bank1";
|
||||
reg = <0xa00000 0x400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -102,6 +118,33 @@
|
|||
optee {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
fwu-mdata {
|
||||
compatible = "u-boot,fwu-mdata-mtd";
|
||||
fwu-mdata-store = <&flash0>;
|
||||
mdata-parts = "MDATA-Pri", "MDATA-Sec";
|
||||
|
||||
fwu-bank0 {
|
||||
id = <0>;
|
||||
label = "FIP-Bank0";
|
||||
fwu-image0 {
|
||||
id = <0>;
|
||||
offset = <0x0>;
|
||||
size = <0x400000>;
|
||||
uuid = "5a66a702-99fd-4fef-a392-c26e261a2828";
|
||||
};
|
||||
};
|
||||
fwu-bank1 {
|
||||
id = <1>;
|
||||
label = "FIP-Bank1";
|
||||
fwu-image0 {
|
||||
id = <0>;
|
||||
offset = <0x0>;
|
||||
size = <0x400000>;
|
||||
uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,10 +13,6 @@
|
|||
#include <asm/arch/clocks_am33xx.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#if defined(CONFIG_TI816X)
|
||||
#include <asm/arch/clock_ti81xx.h>
|
||||
#endif
|
||||
|
||||
#define LDELAY 1000000
|
||||
|
||||
/*CM_<clock_domain>__CLKCTRL */
|
||||
|
|
|
|||
|
|
@ -1,118 +0,0 @@
|
|||
/*
|
||||
* ti81xx.h
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
*
|
||||
* This file is released under the terms of GPL v2 and any later version.
|
||||
* See the file COPYING in the root directory of the source tree for details.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_TI81XX_H_
|
||||
#define _CLOCK_TI81XX_H_
|
||||
|
||||
#define PRCM_MOD_EN 0x2
|
||||
|
||||
#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
|
||||
#define CM_ALWON_BASE (PRCM_BASE + 0x1400)
|
||||
|
||||
struct cm_def {
|
||||
unsigned int resv0[2];
|
||||
unsigned int l3fastclkstctrl;
|
||||
unsigned int resv1[1];
|
||||
unsigned int pciclkstctrl;
|
||||
unsigned int resv2[1];
|
||||
unsigned int ducaticlkstctrl;
|
||||
unsigned int resv3[1];
|
||||
unsigned int emif0clkctrl;
|
||||
unsigned int emif1clkctrl;
|
||||
unsigned int dmmclkctrl;
|
||||
unsigned int fwclkctrl;
|
||||
unsigned int resv4[10];
|
||||
unsigned int usbclkctrl;
|
||||
unsigned int resv5[1];
|
||||
unsigned int sataclkctrl;
|
||||
unsigned int resv6[4];
|
||||
unsigned int ducaticlkctrl;
|
||||
unsigned int pciclkctrl;
|
||||
};
|
||||
|
||||
struct cm_alwon {
|
||||
unsigned int l3slowclkstctrl;
|
||||
unsigned int ethclkstctrl;
|
||||
unsigned int l3medclkstctrl;
|
||||
unsigned int mmu_clkstctrl;
|
||||
unsigned int mmucfg_clkstctrl;
|
||||
unsigned int ocmc0clkstctrl;
|
||||
#if defined(CONFIG_TI816X)
|
||||
unsigned int ocmc1clkstctrl;
|
||||
#endif
|
||||
unsigned int mpuclkstctrl;
|
||||
unsigned int sysclk4clkstctrl;
|
||||
unsigned int sysclk5clkstctrl;
|
||||
unsigned int sysclk6clkstctrl;
|
||||
unsigned int rtcclkstctrl;
|
||||
unsigned int l3fastclkstctrl;
|
||||
unsigned int resv0[67];
|
||||
unsigned int mcasp0clkctrl;
|
||||
unsigned int mcasp1clkctrl;
|
||||
unsigned int mcasp2clkctrl;
|
||||
unsigned int mcbspclkctrl;
|
||||
unsigned int uart0clkctrl;
|
||||
unsigned int uart1clkctrl;
|
||||
unsigned int uart2clkctrl;
|
||||
unsigned int gpio0clkctrl;
|
||||
unsigned int gpio1clkctrl;
|
||||
unsigned int i2c0clkctrl;
|
||||
unsigned int i2c1clkctrl;
|
||||
#if defined(CONFIG_TI816X)
|
||||
unsigned int resv1[1];
|
||||
unsigned int timer1clkctrl;
|
||||
unsigned int timer2clkctrl;
|
||||
unsigned int timer3clkctrl;
|
||||
unsigned int timer4clkctrl;
|
||||
unsigned int timer5clkctrl;
|
||||
unsigned int timer6clkctrl;
|
||||
unsigned int timer7clkctrl;
|
||||
#endif
|
||||
unsigned int wdtimerclkctrl;
|
||||
unsigned int spiclkctrl;
|
||||
unsigned int mailboxclkctrl;
|
||||
unsigned int spinboxclkctrl;
|
||||
unsigned int mmudataclkctrl;
|
||||
unsigned int resv2[2];
|
||||
unsigned int mmucfgclkctrl;
|
||||
#if defined(CONFIG_TI816X)
|
||||
unsigned int resv3[1];
|
||||
unsigned int sdioclkctrl;
|
||||
#endif
|
||||
unsigned int ocmc0clkctrl;
|
||||
#if defined(CONFIG_TI816X)
|
||||
unsigned int ocmc1clkctrl;
|
||||
#endif
|
||||
unsigned int resv4[2];
|
||||
unsigned int controlclkctrl;
|
||||
unsigned int resv5[2];
|
||||
unsigned int gpmcclkctrl;
|
||||
unsigned int ethernet0clkctrl;
|
||||
unsigned int ethernet1clkctrl;
|
||||
unsigned int mpuclkctrl;
|
||||
#if defined(CONFIG_TI816X)
|
||||
unsigned int resv6[1];
|
||||
#endif
|
||||
unsigned int l3clkctrl;
|
||||
unsigned int l4hsclkctrl;
|
||||
unsigned int l4lsclkctrl;
|
||||
unsigned int rtcclkctrl;
|
||||
unsigned int tpccclkctrl;
|
||||
unsigned int tptc0clkctrl;
|
||||
unsigned int tptc1clkctrl;
|
||||
unsigned int tptc2clkctrl;
|
||||
unsigned int tptc3clkctrl;
|
||||
#if defined(CONFIG_TI816X)
|
||||
unsigned int sr0clkctrl;
|
||||
unsigned int sr1clkctrl;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* _CLOCK_TI81XX_H_ */
|
||||
|
|
@ -369,15 +369,9 @@ struct ddr_ctrl {
|
|||
unsigned int ddrckectrl;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_TI816X
|
||||
void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
|
||||
const struct emif_regs *regs,
|
||||
const struct dmm_lisa_map_regs *lisa_regs, int nrs);
|
||||
#else
|
||||
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
|
||||
const struct ddr_data *data, const struct cmd_control *ctrl,
|
||||
const struct emif_regs *regs, int nr);
|
||||
#endif
|
||||
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
|
||||
|
||||
#endif /* _DDR_DEFS_H */
|
||||
|
|
|
|||
|
|
@ -1,37 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010 Texas Instruments
|
||||
*
|
||||
* Based on:
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
* dm644x_emac.h
|
||||
*
|
||||
* TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
|
||||
*
|
||||
* Copyright (C) 2005 Texas Instruments.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _EMAC_DEFS_H_
|
||||
#define _EMAC_DEFS_H_
|
||||
|
||||
#ifdef CONFIG_TI816X
|
||||
#define EMAC_BASE_ADDR (0x4A100000)
|
||||
#define EMAC_WRAPPER_BASE_ADDR (0x4A100900)
|
||||
#define EMAC_WRAPPER_RAM_ADDR (0x4A102000)
|
||||
#define EMAC_MDIO_BASE_ADDR (0x4A100800)
|
||||
#define EMAC_MDIO_BUS_FREQ (250000000UL)
|
||||
#define EMAC_MDIO_CLOCK_FREQ (2000000UL)
|
||||
|
||||
typedef volatile unsigned int dv_reg;
|
||||
typedef volatile unsigned int *dv_reg_p;
|
||||
|
||||
#define DAVINCI_EMAC_VERSION2
|
||||
#define DAVINCI_EMAC_GIG_ENABLE
|
||||
#endif
|
||||
|
||||
#endif /* _EMAC_DEFS_H_ */
|
||||
|
|
@ -14,8 +14,6 @@
|
|||
#include <asm/arch/omap.h>
|
||||
#ifdef CONFIG_AM33XX
|
||||
#include <asm/arch/hardware_am33xx.h>
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#include <asm/arch/hardware_ti816x.h>
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#include <asm/arch/hardware_am43xx.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* hardware_ti816x.h
|
||||
*
|
||||
* TI816x hardware specific header
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
* Based on TI-PSP-04.00.02.14
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_TI816X_H
|
||||
#define __AM33XX_HARDWARE_TI816X_H
|
||||
|
||||
/* UART */
|
||||
#define UART0_BASE 0x48020000
|
||||
#define UART1_BASE 0x48022000
|
||||
#define UART2_BASE 0x48024000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x480C2000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x48140000
|
||||
#define CTRL_DEVICE_BASE 0x48140600
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x48180000
|
||||
|
||||
#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
|
||||
#define PRM_RSTST (PRM_RSTCTRL + 8)
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x48198358
|
||||
#define VTP1_CTRL_ADDR 0x4819A358
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_PHY_CMD_ADDR 0x48198000
|
||||
#define DDR_PHY_DATA_ADDR 0x481980C8
|
||||
#define DDR_PHY_CMD_ADDR2 0x4819A000
|
||||
#define DDR_PHY_DATA_ADDR2 0x4819A0C8
|
||||
#define DDR_DATA_REGS_NR 4
|
||||
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE 0x48198000
|
||||
#define DDRPHY_1_CONFIG_BASE 0x4819A000
|
||||
#define DDRPHY_CONFIG_BASE ((emif == 0) ? \
|
||||
DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
|
||||
|
||||
/* RTC base address */
|
||||
#define RTC_BASE 0x480C0000
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_TI816X_H */
|
||||
|
|
@ -24,9 +24,4 @@
|
|||
#define OMAP_HSMMC1_BASE 0x48060000
|
||||
#define OMAP_HSMMC2_BASE 0x481D8000
|
||||
|
||||
#if defined(CONFIG_TI816X)
|
||||
#undef MMC_CLOCK_REFERENCE
|
||||
#define MMC_CLOCK_REFERENCE 48 /* MHz */
|
||||
#endif
|
||||
|
||||
#endif /* MMC_HOST_DEF_H */
|
||||
|
|
|
|||
|
|
@ -20,8 +20,6 @@
|
|||
|
||||
#ifdef CONFIG_AM33XX
|
||||
#include <asm/arch/mux_am33xx.h>
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#include <asm/arch/mux_ti816x.h>
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#include <asm/arch/mux_am43xx.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,362 +0,0 @@
|
|||
/*
|
||||
* mux_ti816x.h
|
||||
*
|
||||
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
||||
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _MUX_TI816X_H_
|
||||
#define _MUX_TI816X_H_
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#define MUX_CFG(value, offset) \
|
||||
__raw_writel(value, (CTRL_BASE + offset));
|
||||
|
||||
#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
|
||||
#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
|
||||
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
|
||||
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
|
||||
#define MODE(val) (val) /* used for Readability */
|
||||
|
||||
|
||||
/*
|
||||
* PAD CONTROL OFFSETS
|
||||
* Field names corresponds to the pad signal name
|
||||
*/
|
||||
struct pad_signals {
|
||||
int pincntl1;
|
||||
int pincntl2;
|
||||
int pincntl3;
|
||||
int pincntl4;
|
||||
int pincntl5;
|
||||
int pincntl6;
|
||||
int pincntl7;
|
||||
int pincntl8;
|
||||
int pincntl9;
|
||||
int pincntl10;
|
||||
int pincntl11;
|
||||
int pincntl12;
|
||||
int pincntl13;
|
||||
int pincntl14;
|
||||
int pincntl15;
|
||||
int pincntl16;
|
||||
int pincntl17;
|
||||
int pincntl18;
|
||||
int pincntl19;
|
||||
int pincntl20;
|
||||
int pincntl21;
|
||||
int pincntl22;
|
||||
int pincntl23;
|
||||
int pincntl24;
|
||||
int pincntl25;
|
||||
int pincntl26;
|
||||
int pincntl27;
|
||||
int pincntl28;
|
||||
int pincntl29;
|
||||
int pincntl30;
|
||||
int pincntl31;
|
||||
int pincntl32;
|
||||
int pincntl33;
|
||||
int pincntl34;
|
||||
int pincntl35;
|
||||
int pincntl36;
|
||||
int pincntl37;
|
||||
int pincntl38;
|
||||
int pincntl39;
|
||||
int pincntl40;
|
||||
int pincntl41;
|
||||
int pincntl42;
|
||||
int pincntl43;
|
||||
int pincntl44;
|
||||
int pincntl45;
|
||||
int pincntl46;
|
||||
int pincntl47;
|
||||
int pincntl48;
|
||||
int pincntl49;
|
||||
int pincntl50;
|
||||
int pincntl51;
|
||||
int pincntl52;
|
||||
int pincntl53;
|
||||
int pincntl54;
|
||||
int pincntl55;
|
||||
int pincntl56;
|
||||
int pincntl57;
|
||||
int pincntl58;
|
||||
int pincntl59;
|
||||
int pincntl60;
|
||||
int pincntl61;
|
||||
int pincntl62;
|
||||
int pincntl63;
|
||||
int pincntl64;
|
||||
int pincntl65;
|
||||
int pincntl66;
|
||||
int pincntl67;
|
||||
int pincntl68;
|
||||
int pincntl69;
|
||||
int pincntl70;
|
||||
int pincntl71;
|
||||
int pincntl72;
|
||||
int pincntl73;
|
||||
int pincntl74;
|
||||
int pincntl75;
|
||||
int pincntl76;
|
||||
int pincntl77;
|
||||
int pincntl78;
|
||||
int pincntl79;
|
||||
int pincntl80;
|
||||
int pincntl81;
|
||||
int pincntl82;
|
||||
int pincntl83;
|
||||
int pincntl84;
|
||||
int pincntl85;
|
||||
int pincntl86;
|
||||
int pincntl87;
|
||||
int pincntl88;
|
||||
int pincntl89;
|
||||
int pincntl90;
|
||||
int pincntl91;
|
||||
int pincntl92;
|
||||
int pincntl93;
|
||||
int pincntl94;
|
||||
int pincntl95;
|
||||
int pincntl96;
|
||||
int pincntl97;
|
||||
int pincntl98;
|
||||
int pincntl99;
|
||||
int pincntl100;
|
||||
int pincntl101;
|
||||
int pincntl102;
|
||||
int pincntl103;
|
||||
int pincntl104;
|
||||
int pincntl105;
|
||||
int pincntl106;
|
||||
int pincntl107;
|
||||
int pincntl108;
|
||||
int pincntl109;
|
||||
int pincntl110;
|
||||
int pincntl111;
|
||||
int pincntl112;
|
||||
int pincntl113;
|
||||
int pincntl114;
|
||||
int pincntl115;
|
||||
int pincntl116;
|
||||
int pincntl117;
|
||||
int pincntl118;
|
||||
int pincntl119;
|
||||
int pincntl120;
|
||||
int pincntl121;
|
||||
int pincntl122;
|
||||
int pincntl123;
|
||||
int pincntl124;
|
||||
int pincntl125;
|
||||
int pincntl126;
|
||||
int pincntl127;
|
||||
int pincntl128;
|
||||
int pincntl129;
|
||||
int pincntl130;
|
||||
int pincntl131;
|
||||
int pincntl132;
|
||||
int pincntl133;
|
||||
int pincntl134;
|
||||
int pincntl135;
|
||||
int pincntl136;
|
||||
int pincntl137;
|
||||
int pincntl138;
|
||||
int pincntl139;
|
||||
int pincntl140;
|
||||
int pincntl141;
|
||||
int pincntl142;
|
||||
int pincntl143;
|
||||
int pincntl144;
|
||||
int pincntl145;
|
||||
int pincntl146;
|
||||
int pincntl147;
|
||||
int pincntl148;
|
||||
int pincntl149;
|
||||
int pincntl150;
|
||||
int pincntl151;
|
||||
int pincntl152;
|
||||
int pincntl153;
|
||||
int pincntl154;
|
||||
int pincntl155;
|
||||
int pincntl156;
|
||||
int pincntl157;
|
||||
int pincntl158;
|
||||
int pincntl159;
|
||||
int pincntl160;
|
||||
int pincntl161;
|
||||
int pincntl162;
|
||||
int pincntl163;
|
||||
int pincntl164;
|
||||
int pincntl165;
|
||||
int pincntl166;
|
||||
int pincntl167;
|
||||
int pincntl168;
|
||||
int pincntl169;
|
||||
int pincntl170;
|
||||
int pincntl171;
|
||||
int pincntl172;
|
||||
int pincntl173;
|
||||
int pincntl174;
|
||||
int pincntl175;
|
||||
int pincntl176;
|
||||
int pincntl177;
|
||||
int pincntl178;
|
||||
int pincntl179;
|
||||
int pincntl180;
|
||||
int pincntl181;
|
||||
int pincntl182;
|
||||
int pincntl183;
|
||||
int pincntl184;
|
||||
int pincntl185;
|
||||
int pincntl186;
|
||||
int pincntl187;
|
||||
int pincntl188;
|
||||
int pincntl189;
|
||||
int pincntl190;
|
||||
int pincntl191;
|
||||
int pincntl192;
|
||||
int pincntl193;
|
||||
int pincntl194;
|
||||
int pincntl195;
|
||||
int pincntl196;
|
||||
int pincntl197;
|
||||
int pincntl198;
|
||||
int pincntl199;
|
||||
int pincntl200;
|
||||
int pincntl201;
|
||||
int pincntl202;
|
||||
int pincntl203;
|
||||
int pincntl204;
|
||||
int pincntl205;
|
||||
int pincntl206;
|
||||
int pincntl207;
|
||||
int pincntl208;
|
||||
int pincntl209;
|
||||
int pincntl210;
|
||||
int pincntl211;
|
||||
int pincntl212;
|
||||
int pincntl213;
|
||||
int pincntl214;
|
||||
int pincntl215;
|
||||
int pincntl216;
|
||||
int pincntl217;
|
||||
int pincntl218;
|
||||
int pincntl219;
|
||||
int pincntl220;
|
||||
int pincntl221;
|
||||
int pincntl222;
|
||||
int pincntl223;
|
||||
int pincntl224;
|
||||
int pincntl225;
|
||||
int pincntl226;
|
||||
int pincntl227;
|
||||
int pincntl228;
|
||||
int pincntl229;
|
||||
int pincntl230;
|
||||
int pincntl231;
|
||||
int pincntl232;
|
||||
int pincntl233;
|
||||
int pincntl234;
|
||||
int pincntl235;
|
||||
int pincntl236;
|
||||
int pincntl237;
|
||||
int pincntl238;
|
||||
int pincntl239;
|
||||
int pincntl240;
|
||||
int pincntl241;
|
||||
int pincntl242;
|
||||
int pincntl243;
|
||||
int pincntl244;
|
||||
int pincntl245;
|
||||
int pincntl246;
|
||||
int pincntl247;
|
||||
int pincntl248;
|
||||
int pincntl249;
|
||||
int pincntl250;
|
||||
int pincntl251;
|
||||
int pincntl252;
|
||||
int pincntl253;
|
||||
int pincntl254;
|
||||
int pincntl255;
|
||||
int pincntl256;
|
||||
int pincntl257;
|
||||
int pincntl258;
|
||||
int pincntl259;
|
||||
int pincntl260;
|
||||
int pincntl261;
|
||||
int pincntl262;
|
||||
int pincntl263;
|
||||
int pincntl264;
|
||||
int pincntl265;
|
||||
int pincntl266;
|
||||
int pincntl267;
|
||||
int pincntl268;
|
||||
int pincntl269;
|
||||
int pincntl270;
|
||||
int pincntl271;
|
||||
int pincntl272;
|
||||
int pincntl273;
|
||||
int pincntl274;
|
||||
int pincntl275;
|
||||
int pincntl276;
|
||||
int pincntl277;
|
||||
int pincntl278;
|
||||
int pincntl279;
|
||||
int pincntl280;
|
||||
int pincntl281;
|
||||
int pincntl282;
|
||||
int pincntl283;
|
||||
int pincntl284;
|
||||
int pincntl285;
|
||||
int pincntl286;
|
||||
int pincntl287;
|
||||
int pincntl288;
|
||||
int pincntl289;
|
||||
int pincntl290;
|
||||
int pincntl291;
|
||||
int pincntl292;
|
||||
int pincntl293;
|
||||
int pincntl294;
|
||||
int pincntl295;
|
||||
int pincntl296;
|
||||
int pincntl297;
|
||||
int pincntl298;
|
||||
int pincntl299;
|
||||
int pincntl300;
|
||||
int pincntl301;
|
||||
int pincntl302;
|
||||
int pincntl303;
|
||||
int pincntl304;
|
||||
int pincntl305;
|
||||
int pincntl306;
|
||||
int pincntl307;
|
||||
int pincntl308;
|
||||
int pincntl309;
|
||||
int pincntl310;
|
||||
int pincntl311;
|
||||
int pincntl312;
|
||||
int pincntl313;
|
||||
int pincntl314;
|
||||
int pincntl315;
|
||||
int pincntl316;
|
||||
int pincntl317;
|
||||
int pincntl318;
|
||||
int pincntl319;
|
||||
int pincntl320;
|
||||
int pincntl321;
|
||||
int pincntl322;
|
||||
int pincntl323;
|
||||
};
|
||||
|
||||
#endif /* endif _MUX_TI816X_H_ */
|
||||
|
|
@ -20,10 +20,6 @@
|
|||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40310000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x4030B800
|
||||
#elif defined(CONFIG_TI816X)
|
||||
#define NON_SECURE_SRAM_START 0x40300000
|
||||
#define NON_SECURE_SRAM_END 0x40320000
|
||||
#define NON_SECURE_SRAM_IMG_END 0x4031B800
|
||||
#elif defined(CONFIG_AM43XX)
|
||||
#define NON_SECURE_SRAM_START 0x402F0400
|
||||
#define NON_SECURE_SRAM_END 0x40340000
|
||||
|
|
|
|||
|
|
@ -9,19 +9,7 @@
|
|||
#define BOOT_DEVICE_NONE 0x00
|
||||
#define BOOT_DEVICE_MMC2_2 0xFF
|
||||
|
||||
#if defined(CONFIG_TI816X)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x03
|
||||
#define BOOT_DEVICE_ONENAND 0x04
|
||||
#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */
|
||||
#define BOOT_DEVICE_MMC1 0x06
|
||||
#define BOOT_DEVICE_UART 0x43
|
||||
#define BOOT_DEVICE_USB 0x45
|
||||
|
||||
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
|
||||
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
|
||||
#elif defined(CONFIG_AM33XX)
|
||||
#if defined(CONFIG_AM33XX)
|
||||
#define BOOT_DEVICE_XIP 0x01
|
||||
#define BOOT_DEVICE_XIPWAIT 0x02
|
||||
#define BOOT_DEVICE_NAND 0x05
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014-2017 Broadcom.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CONFIGS_H
|
||||
#define __ARCH_CONFIGS_H
|
||||
|
||||
#include <asm/iproc-common/configs.h>
|
||||
|
||||
/* uArchitecture specifics */
|
||||
|
||||
/* Serial Info */
|
||||
#define CFG_SYS_NS16550_CLK 100000000
|
||||
#define CFG_SYS_NS16550_CLK_DIV 54
|
||||
#define CFG_SYS_NS16550_COM3 0x18023000
|
||||
|
||||
#endif /* __ARCH_CONFIGS_H */
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CONFIGS_H
|
||||
#define __ARCH_CONFIGS_H
|
||||
|
||||
#include <asm/iproc-common/configs.h>
|
||||
|
||||
/* uArchitecture specifics */
|
||||
|
||||
/* Serial Info */
|
||||
#define CFG_SYS_NS16550_CLK 0x03b9aca0
|
||||
#define CFG_SYS_NS16550_COM1 0x18000300
|
||||
|
||||
#endif /* __ARCH_CONFIGS_H */
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
*
|
||||
* -PCIe
|
||||
* -there is a range of stream IDs set aside for PCI in this
|
||||
* file. U-boot will scan the PCI bus and for each device discovered:
|
||||
* file. U-Boot will scan the PCI bus and for each device discovered:
|
||||
* -allocate a streamID
|
||||
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
|
||||
* -set a msi-map entry in the PEXn controller node in the
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
*
|
||||
* -PCIe
|
||||
* -there is a range of stream IDs set aside for PCI in this
|
||||
* file. U-boot will scan the PCI bus and for each device discovered:
|
||||
* file. U-Boot will scan the PCI bus and for each device discovered:
|
||||
* -allocate a streamID
|
||||
* -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
|
||||
* -set a msi-map entry in the PEXn controller node in the
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#ifndef __ARCH_IMX8M_SYS_PROTO_H
|
||||
#define __ARCH_NMX8M_SYS_PROTO_H
|
||||
#define __ARCH_IMX8M_SYS_PROTO_H
|
||||
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#ifndef __ARCH_IMX8ULP_SYS_PROTO_H
|
||||
#define __ARCH_NMX8ULP_SYS_PROTO_H
|
||||
#define __ARCH_IMX8ULP_SYS_PROTO_H
|
||||
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
*/
|
||||
|
||||
#ifndef __ARCH_IMX9_SYS_PROTO_H
|
||||
#define __ARCH_NMX9_SYS_PROTO_H
|
||||
#define __ARCH_IMX9_SYS_PROTO_H
|
||||
|
||||
#include <asm/mach-imx/sys_proto.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2019
|
||||
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_IMXRT_H
|
||||
#define _ASM_ARCH_IMXRT_H
|
||||
|
||||
#endif /* _ASM_ARCH_IMXRT_H */
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* LPC32xx GPIO interface macro for pin mapping.
|
||||
*
|
||||
* (C) Copyright 2015 DENX Software Engineering GmbH
|
||||
* Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
|
||||
*/
|
||||
|
||||
#ifndef _LPC32XX_GPIO_GRP_H
|
||||
#define _LPC32XX_GPIO_GRP_H
|
||||
|
||||
/*
|
||||
* Macro to map the pin for the lpc32xx_gpio driver.
|
||||
* Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
|
||||
* mapping is done per register, as group of 32.
|
||||
* (see drivers/gpio/lpc32xx_gpio.c for details).
|
||||
* - macros can be use with the following pins:
|
||||
* P0.0 - P0.7
|
||||
* P1.0 - P1.23
|
||||
* P2.0 - P2.12
|
||||
* P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
|
||||
* P3 GPO_0 - GPO_23
|
||||
* P3 GPIO_0 - GPIO_5 (output register only)
|
||||
*/
|
||||
#define LPC32XX_GPIO_P0_GRP 0
|
||||
#define LPC32XX_GPIO_P1_GRP 32
|
||||
#define LPC32XX_GPIO_P2_GRP 64
|
||||
#define LPC32XX_GPO_P3_GRP 96
|
||||
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
|
||||
#define LPC32XX_GPI_P3_GRP 128
|
||||
|
||||
/*
|
||||
* A specific GPIO can be selected with this macro
|
||||
* ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
|
||||
* See the LPC32x0 User's guide for GPIO group numbers
|
||||
*/
|
||||
#define LPC32XX_GPIO(x, y) ((x) + (y))
|
||||
|
||||
#endif /* _LPC32XX_GPIO_GRP_H */
|
||||
20
arch/arm/include/asm/arch-meson/a1.h
Normal file
20
arch/arm/include/asm/arch-meson/a1.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2023 SberDevices, Inc.
|
||||
* Author: Igor Prusov <ivprusov@sberdevices.ru>
|
||||
*/
|
||||
|
||||
#ifndef __MESON_A1_H__
|
||||
#define __MESON_A1_H__
|
||||
|
||||
#define A1_SYSCTRL_BASE 0xfe005800
|
||||
|
||||
/* SYSCTRL registers */
|
||||
#define A1_SYSCTRL_ADDR(off) (A1_SYSCTRL_BASE + ((off) << 2))
|
||||
|
||||
#define A1_SYSCTRL_SEC_STATUS_REG4 A1_SYSCTRL_ADDR(0xc4)
|
||||
|
||||
#define A1_SYSCTRL_MEM_SIZE_MASK 0xFFFF0000
|
||||
#define A1_SYSCTRL_MEM_SIZE_SHIFT 16
|
||||
|
||||
#endif /* __MESON_A1_H__ */
|
||||
|
|
@ -58,4 +58,34 @@ enum {
|
|||
*/
|
||||
int meson_sm_get_reboot_reason(void);
|
||||
|
||||
#define PWRDM_OFF 0
|
||||
#define PWRDM_ON 1
|
||||
|
||||
/**
|
||||
* meson_sm_pwrdm_set - do command at specified power domain.
|
||||
*
|
||||
* @index: power domain index.
|
||||
* @cmd: command index.
|
||||
* @return: zero on success or error code on failure.
|
||||
*/
|
||||
int meson_sm_pwrdm_set(size_t index, int cmd);
|
||||
|
||||
/**
|
||||
* meson_sm_pwrdm_off - disable specified power domain.
|
||||
*
|
||||
* @index: power domain index.
|
||||
* @return: zero on success or error code on failure.
|
||||
*/
|
||||
#define meson_sm_pwrdm_off(index) \
|
||||
meson_sm_pwrdm_set(index, PWRDM_OFF)
|
||||
|
||||
/**
|
||||
* meson_sm_pwrdm_on - enable specified power domain.
|
||||
*
|
||||
* @index: power domain index.
|
||||
* @return: zero on success or error code on failure.
|
||||
*/
|
||||
#define meson_sm_pwrdm_on(index) \
|
||||
meson_sm_pwrdm_set(index, PWRDM_ON)
|
||||
|
||||
#endif /* __MESON_SM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,11 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
|
||||
*/
|
||||
|
||||
#ifndef ASM_ARCH_MXCMMC_H
|
||||
#define ASM_ARCH_MXCMMC_H
|
||||
|
||||
int mxc_mmc_init(struct bd_info *bis);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2017 Armadeus Systems
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
|
||||
#define __ARCH_ARM_MX6UL_OPOS6UL_H__
|
||||
|
||||
int opos6ul_board_late_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,219 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Freescale MXS UARTAPP Register Definitions
|
||||
*
|
||||
* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
|
||||
*
|
||||
* Based on code from LTIB:
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM___MXS_UARTAPP_H
|
||||
#define __ARCH_ARM___MXS_UARTAPP_H
|
||||
|
||||
#include <asm/mach-imx/regs-common.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxs_uartapp_regs {
|
||||
mxs_reg_32(hw_uartapp_ctrl0)
|
||||
mxs_reg_32(hw_uartapp_ctrl1)
|
||||
mxs_reg_32(hw_uartapp_ctrl2)
|
||||
mxs_reg_32(hw_uartapp_linectrl)
|
||||
mxs_reg_32(hw_uartapp_linectrl2)
|
||||
mxs_reg_32(hw_uartapp_intr)
|
||||
mxs_reg_32(hw_uartapp_data)
|
||||
mxs_reg_32(hw_uartapp_stat)
|
||||
mxs_reg_32(hw_uartapp_debug)
|
||||
mxs_reg_32(hw_uartapp_version)
|
||||
mxs_reg_32(hw_uartapp_autobaud)
|
||||
};
|
||||
#endif
|
||||
|
||||
#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
|
||||
#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
|
||||
#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
|
||||
#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
|
||||
#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
|
||||
#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
|
||||
#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
|
||||
#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
|
||||
#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
|
||||
|
||||
#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
|
||||
#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
|
||||
#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
|
||||
#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
|
||||
#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
|
||||
#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
|
||||
#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
|
||||
#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
|
||||
#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
|
||||
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
|
||||
#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
|
||||
#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
|
||||
#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
|
||||
#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
|
||||
#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
|
||||
#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
|
||||
#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
|
||||
#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
|
||||
#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
|
||||
#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
|
||||
|
||||
#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
|
||||
#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
|
||||
#define UARTAPP_CTRL2_UARTEN_MASK 0x01
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
|
||||
#define UARTAPP_LINECTRL_BRK_MASK 1
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
|
||||
|
||||
#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
|
||||
#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
|
||||
#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
|
||||
#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
|
||||
#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
|
||||
#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
|
||||
#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
|
||||
#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
|
||||
#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
|
||||
#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
|
||||
#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
|
||||
#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
|
||||
|
||||
#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
|
||||
#define UARTAPP_INTR_OEIS_MASK (1 << 10)
|
||||
#define UARTAPP_INTR_BEIS_MASK (1 << 9)
|
||||
#define UARTAPP_INTR_PEIS_MASK (1 << 8)
|
||||
#define UARTAPP_INTR_FEIS_MASK (1 << 7)
|
||||
#define UARTAPP_INTR_RTIS_MASK (1 << 6)
|
||||
#define UARTAPP_INTR_TXIS_MASK (1 << 5)
|
||||
#define UARTAPP_INTR_RXIS_MASK (1 << 4)
|
||||
#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
|
||||
#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
|
||||
#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
|
||||
#define UARTAPP_INTR_RIMIS_MASK 0x1
|
||||
|
||||
#define UARTAPP_DATA_DATA_OFFSET 0
|
||||
#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
|
||||
#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
|
||||
|
||||
#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
|
||||
|
||||
#define UARTAPP_STAT_BUSY_MASK (1 << 29)
|
||||
#define UARTAPP_STAT_CTS_MASK (1 << 28)
|
||||
#define UARTAPP_STAT_TXFE_MASK (1 << 27)
|
||||
#define UARTAPP_STAT_RXFF_MASK (1 << 26)
|
||||
#define UARTAPP_STAT_TXFF_MASK (1 << 25)
|
||||
#define UARTAPP_STAT_RXFE_MASK (1 << 24)
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
|
||||
|
||||
#define UARTAPP_STAT_OERR_MASK (1 << 19)
|
||||
#define UARTAPP_STAT_BERR_MASK (1 << 18)
|
||||
#define UARTAPP_STAT_PERR_MASK (1 << 17)
|
||||
#define UARTAPP_STAT_FERR_MASK (1 << 16)
|
||||
#define UARTAPP_STAT_RXCOUNT_OFFSET 0
|
||||
#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
|
||||
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
|
||||
|
||||
#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
|
||||
#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
|
||||
#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
|
||||
#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
|
||||
#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
|
||||
#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
|
||||
|
||||
#define UARTAPP_VERSION_MAJOR_OFFSET 24
|
||||
#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_VERSION_MINOR_OFFSET 16
|
||||
#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_VERSION_STEP_OFFSET 0
|
||||
#define UARTAPP_VERSION_STEP_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
|
||||
#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
|
||||
#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
|
||||
#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
|
||||
#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
|
||||
#endif /* __ARCH_ARM___UARTAPP_H */
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
|
||||
*/
|
||||
|
||||
#ifndef _OMAP3_REGS_H
|
||||
#define _OMAP3_REGS_H
|
||||
|
||||
/*
|
||||
* Register definitions for OMAP3 processors.
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPMC_CONFIG1 - GPMC_CONFIG7
|
||||
*/
|
||||
|
||||
/* Values for GPMC_CONFIG1 - signal control parameters */
|
||||
#define WRAPBURST (1 << 31)
|
||||
#define READMULTIPLE (1 << 30)
|
||||
#define READTYPE (1 << 29)
|
||||
#define WRITEMULTIPLE (1 << 28)
|
||||
#define WRITETYPE (1 << 27)
|
||||
#define CLKACTIVATIONTIME(x) (((x) & 3) << 25)
|
||||
#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23)
|
||||
#define WAITREADMONITORING (1 << 22)
|
||||
#define WAITWRITEMONITORING (1 << 21)
|
||||
#define WAITMONITORINGTIME(x) (((x) & 3) << 18)
|
||||
#define WAITPINSELECT(x) (((x) & 3) << 16)
|
||||
#define DEVICESIZE(x) (((x) & 3) << 12)
|
||||
#define DEVICESIZE_8BIT DEVICESIZE(0)
|
||||
#define DEVICESIZE_16BIT DEVICESIZE(1)
|
||||
#define DEVICETYPE(x) (((x) & 3) << 10)
|
||||
#define DEVICETYPE_NOR DEVICETYPE(0)
|
||||
#define DEVICETYPE_NAND DEVICETYPE(2)
|
||||
#define MUXADDDATA (1 << 9)
|
||||
#define TIMEPARAGRANULARITY (1 << 4)
|
||||
#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG2 - CS timing */
|
||||
#define CSWROFFTIME(x) (((x) & 0x1f) << 16)
|
||||
#define CSRDOFFTIME(x) (((x) & 0x1f) << 8)
|
||||
#define CSEXTRADELAY (1 << 7)
|
||||
#define CSONTIME(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG3 - nADV timing */
|
||||
#define ADVWROFFTIME(x) (((x) & 0x1f) << 16)
|
||||
#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8)
|
||||
#define ADVEXTRADELAY (1 << 7)
|
||||
#define ADVONTIME(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG4 - nWE and nOE timing */
|
||||
#define WEOFFTIME(x) (((x) & 0x1f) << 24)
|
||||
#define WEEXTRADELAY (1 << 23)
|
||||
#define WEONTIME(x) (((x) & 0xf) << 16)
|
||||
#define OEOFFTIME(x) (((x) & 0x1f) << 8)
|
||||
#define OEEXTRADELAY (1 << 7)
|
||||
#define OEONTIME(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
|
||||
#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
|
||||
#define RDACCESSTIME(x) (((x) & 0x1f) << 16)
|
||||
#define WRCYCLETIME(x) (((x) & 0x1f) << 8)
|
||||
#define RDCYCLETIME(x) (((x) & 0x1f) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG6 - misc timings */
|
||||
#define WRACCESSTIME(x) (((x) & 0x1f) << 24)
|
||||
#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
|
||||
#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
|
||||
#define CYCLE2CYCLESAMECSEN (1 << 7)
|
||||
#define CYCLE2CYCLEDIFFCSEN (1 << 6)
|
||||
#define BUSTURNAROUND(x) (((x) & 0xf) << 0)
|
||||
|
||||
/* Values for GPMC_CONFIG7 - CS address mapping configuration */
|
||||
#define MASKADDRESS(x) (((x) & 0xf) << 8)
|
||||
#define CSVALID (1 << 6)
|
||||
#define BASEADDRESS(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#endif /* _OMAP3_REGS_H */
|
||||
|
|
@ -1,317 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2004-2009
|
||||
* Texas Instruments Incorporated
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
* Balaji Krishnamoorthy <balajitk@ti.com>
|
||||
*/
|
||||
#ifndef _MUX_OMAP5_H_
|
||||
#define _MUX_OMAP5_H_
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
#ifdef CONFIG_OFF_PADCONF
|
||||
#define OFF_PD (1 << 12)
|
||||
#define OFF_PU (3 << 12)
|
||||
#define OFF_OUT_PTD (0 << 10)
|
||||
#define OFF_OUT_PTU (2 << 10)
|
||||
#define OFF_IN (1 << 10)
|
||||
#define OFF_OUT (0 << 10)
|
||||
#define OFF_EN (1 << 9)
|
||||
#else
|
||||
#define OFF_PD (0 << 12)
|
||||
#define OFF_PU (0 << 12)
|
||||
#define OFF_OUT_PTD (0 << 10)
|
||||
#define OFF_OUT_PTU (0 << 10)
|
||||
#define OFF_IN (0 << 10)
|
||||
#define OFF_OUT (0 << 10)
|
||||
#define OFF_EN (0 << 9)
|
||||
#endif
|
||||
|
||||
#define IEN (1 << 8)
|
||||
#define IDIS (0 << 8)
|
||||
#define PTU (3 << 3)
|
||||
#define PTD (1 << 3)
|
||||
#define EN (1 << 3)
|
||||
#define DIS (0 << 3)
|
||||
|
||||
#define M0 0
|
||||
#define M1 1
|
||||
#define M2 2
|
||||
#define M3 3
|
||||
#define M4 4
|
||||
#define M5 5
|
||||
#define M6 6
|
||||
#define M7 7
|
||||
|
||||
#define SAFE_MODE M7
|
||||
|
||||
#ifdef CONFIG_OFF_PADCONF
|
||||
#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
|
||||
#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
|
||||
#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
|
||||
#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
|
||||
#else
|
||||
#define OFF_IN_PD 0
|
||||
#define OFF_IN_PU 0
|
||||
#define OFF_OUT_PD 0
|
||||
#define OFF_OUT_PU 0
|
||||
#endif
|
||||
|
||||
#define CORE_REVISION 0x0000
|
||||
#define CORE_HWINFO 0x0004
|
||||
#define CORE_SYSCONFIG 0x0010
|
||||
#define EMMC_CLK 0x0040
|
||||
#define EMMC_CMD 0x0042
|
||||
#define EMMC_DATA0 0x0044
|
||||
#define EMMC_DATA1 0x0046
|
||||
#define EMMC_DATA2 0x0048
|
||||
#define EMMC_DATA3 0x004a
|
||||
#define EMMC_DATA4 0x004c
|
||||
#define EMMC_DATA5 0x004e
|
||||
#define EMMC_DATA6 0x0050
|
||||
#define EMMC_DATA7 0x0052
|
||||
#define C2C_CLKOUT0 0x0054
|
||||
#define C2C_CLKOUT1 0x0056
|
||||
#define C2C_CLKIN0 0x0058
|
||||
#define C2C_CLKIN1 0x005a
|
||||
#define C2C_DATAIN0 0x005c
|
||||
#define C2C_DATAIN1 0x005e
|
||||
#define C2C_DATAIN2 0x0060
|
||||
#define C2C_DATAIN3 0x0062
|
||||
#define C2C_DATAIN4 0x0064
|
||||
#define C2C_DATAIN5 0x0066
|
||||
#define C2C_DATAIN6 0x0068
|
||||
#define C2C_DATAIN7 0x006a
|
||||
#define C2C_DATAOUT0 0x006c
|
||||
#define C2C_DATAOUT1 0x006e
|
||||
#define C2C_DATAOUT2 0x0070
|
||||
#define C2C_DATAOUT3 0x0072
|
||||
#define C2C_DATAOUT4 0x0074
|
||||
#define C2C_DATAOUT5 0x0076
|
||||
#define C2C_DATAOUT6 0x0078
|
||||
#define C2C_DATAOUT7 0x007a
|
||||
#define C2C_DATA8 0x007c
|
||||
#define C2C_DATA9 0x007e
|
||||
#define C2C_DATA10 0x0080
|
||||
#define C2C_DATA11 0x0082
|
||||
#define C2C_DATA12 0x0084
|
||||
#define C2C_DATA13 0x0086
|
||||
#define C2C_DATA14 0x0088
|
||||
#define C2C_DATA15 0x008a
|
||||
#define LLIA_WAKEREQOUT 0x008c
|
||||
#define LLIB_WAKEREQOUT 0x008e
|
||||
#define HSI1_ACREADY 0x0090
|
||||
#define HSI1_CAREADY 0x0092
|
||||
#define HSI1_ACWAKE 0x0094
|
||||
#define HSI1_CAWAKE 0x0096
|
||||
#define HSI1_ACFLAG 0x0098
|
||||
#define HSI1_ACDATA 0x009a
|
||||
#define HSI1_CAFLAG 0x009c
|
||||
#define HSI1_CADATA 0x009e
|
||||
#define UART1_TX 0x00a0
|
||||
#define UART1_CTS 0x00a2
|
||||
#define UART1_RX 0x00a4
|
||||
#define UART1_RTS 0x00a6
|
||||
#define HSI2_CAREADY 0x00a8
|
||||
#define HSI2_ACREADY 0x00aa
|
||||
#define HSI2_CAWAKE 0x00ac
|
||||
#define HSI2_ACWAKE 0x00ae
|
||||
#define HSI2_CAFLAG 0x00b0
|
||||
#define HSI2_CADATA 0x00b2
|
||||
#define HSI2_ACFLAG 0x00b4
|
||||
#define HSI2_ACDATA 0x00b6
|
||||
#define UART2_RTS 0x00b8
|
||||
#define UART2_CTS 0x00ba
|
||||
#define UART2_RX 0x00bc
|
||||
#define UART2_TX 0x00be
|
||||
#define USBB1_HSIC_STROBE 0x00c0
|
||||
#define USBB1_HSIC_DATA 0x00c2
|
||||
#define USBB2_HSIC_STROBE 0x00c4
|
||||
#define USBB2_HSIC_DATA 0x00c6
|
||||
#define TIMER10_PWM_EVT 0x00c8
|
||||
#define DSIPORTA_TE0 0x00ca
|
||||
#define DSIPORTA_LANE0X 0x00cc
|
||||
#define DSIPORTA_LANE0Y 0x00ce
|
||||
#define DSIPORTA_LANE1X 0x00d0
|
||||
#define DSIPORTA_LANE1Y 0x00d2
|
||||
#define DSIPORTA_LANE2X 0x00d4
|
||||
#define DSIPORTA_LANE2Y 0x00d6
|
||||
#define DSIPORTA_LANE3X 0x00d8
|
||||
#define DSIPORTA_LANE3Y 0x00da
|
||||
#define DSIPORTA_LANE4X 0x00dc
|
||||
#define DSIPORTA_LANE4Y 0x00de
|
||||
#define DSIPORTC_LANE0X 0x00e0
|
||||
#define DSIPORTC_LANE0Y 0x00e2
|
||||
#define DSIPORTC_LANE1X 0x00e4
|
||||
#define DSIPORTC_LANE1Y 0x00e6
|
||||
#define DSIPORTC_LANE2X 0x00e8
|
||||
#define DSIPORTC_LANE2Y 0x00ea
|
||||
#define DSIPORTC_LANE3X 0x00ec
|
||||
#define DSIPORTC_LANE3Y 0x00ee
|
||||
#define DSIPORTC_LANE4X 0x00f0
|
||||
#define DSIPORTC_LANE4Y 0x00f2
|
||||
#define DSIPORTC_TE0 0x00f4
|
||||
#define TIMER9_PWM_EVT 0x00f6
|
||||
#define I2C4_SCL 0x00f8
|
||||
#define I2C4_SDA 0x00fa
|
||||
#define MCSPI2_CLK 0x00fc
|
||||
#define MCSPI2_SIMO 0x00fe
|
||||
#define MCSPI2_SOMI 0x0100
|
||||
#define MCSPI2_CS0 0x0102
|
||||
#define RFBI_DATA15 0x0104
|
||||
#define RFBI_DATA14 0x0106
|
||||
#define RFBI_DATA13 0x0108
|
||||
#define RFBI_DATA12 0x010a
|
||||
#define RFBI_DATA11 0x010c
|
||||
#define RFBI_DATA10 0x010e
|
||||
#define RFBI_DATA9 0x0110
|
||||
#define RFBI_DATA8 0x0112
|
||||
#define RFBI_DATA7 0x0114
|
||||
#define RFBI_DATA6 0x0116
|
||||
#define RFBI_DATA5 0x0118
|
||||
#define RFBI_DATA4 0x011a
|
||||
#define RFBI_DATA3 0x011c
|
||||
#define RFBI_DATA2 0x011e
|
||||
#define RFBI_DATA1 0x0120
|
||||
#define RFBI_DATA0 0x0122
|
||||
#define RFBI_WE 0x0124
|
||||
#define RFBI_CS0 0x0126
|
||||
#define RFBI_A0 0x0128
|
||||
#define RFBI_RE 0x012a
|
||||
#define RFBI_HSYNC0 0x012c
|
||||
#define RFBI_TE_VSYNC0 0x012e
|
||||
#define GPIO6_182 0x0130
|
||||
#define GPIO6_183 0x0132
|
||||
#define GPIO6_184 0x0134
|
||||
#define GPIO6_185 0x0136
|
||||
#define GPIO6_186 0x0138
|
||||
#define GPIO6_187 0x013a
|
||||
#define HDMI_CEC 0x013c
|
||||
#define HDMI_HPD 0x013e
|
||||
#define HDMI_DDC_SCL 0x0140
|
||||
#define HDMI_DDC_SDA 0x0142
|
||||
#define CSIPORTC_LANE0X 0x0144
|
||||
#define CSIPORTC_LANE0Y 0x0146
|
||||
#define CSIPORTC_LANE1X 0x0148
|
||||
#define CSIPORTC_LANE1Y 0x014a
|
||||
#define CSIPORTB_LANE0X 0x014c
|
||||
#define CSIPORTB_LANE0Y 0x014e
|
||||
#define CSIPORTB_LANE1X 0x0150
|
||||
#define CSIPORTB_LANE1Y 0x0152
|
||||
#define CSIPORTB_LANE2X 0x0154
|
||||
#define CSIPORTB_LANE2Y 0x0156
|
||||
#define CSIPORTA_LANE0X 0x0158
|
||||
#define CSIPORTA_LANE0Y 0x015a
|
||||
#define CSIPORTA_LANE1X 0x015c
|
||||
#define CSIPORTA_LANE1Y 0x015e
|
||||
#define CSIPORTA_LANE2X 0x0160
|
||||
#define CSIPORTA_LANE2Y 0x0162
|
||||
#define CSIPORTA_LANE3X 0x0164
|
||||
#define CSIPORTA_LANE3Y 0x0166
|
||||
#define CSIPORTA_LANE4X 0x0168
|
||||
#define CSIPORTA_LANE4Y 0x016a
|
||||
#define CAM_SHUTTER 0x016c
|
||||
#define CAM_STROBE 0x016e
|
||||
#define CAM_GLOBALRESET 0x0170
|
||||
#define TIMER11_PWM_EVT 0x0172
|
||||
#define TIMER5_PWM_EVT 0x0174
|
||||
#define TIMER6_PWM_EVT 0x0176
|
||||
#define TIMER8_PWM_EVT 0x0178
|
||||
#define I2C3_SCL 0x017a
|
||||
#define I2C3_SDA 0x017c
|
||||
#define GPIO8_233 0x017e
|
||||
#define GPIO8_234 0x0180
|
||||
#define ABE_CLKS 0x0182
|
||||
#define ABEDMIC_DIN1 0x0184
|
||||
#define ABEDMIC_DIN2 0x0186
|
||||
#define ABEDMIC_DIN3 0x0188
|
||||
#define ABEDMIC_CLK1 0x018a
|
||||
#define ABEDMIC_CLK2 0x018c
|
||||
#define ABEDMIC_CLK3 0x018e
|
||||
#define ABESLIMBUS1_CLOCK 0x0190
|
||||
#define ABESLIMBUS1_DATA 0x0192
|
||||
#define ABEMCBSP2_DR 0x0194
|
||||
#define ABEMCBSP2_DX 0x0196
|
||||
#define ABEMCBSP2_FSX 0x0198
|
||||
#define ABEMCBSP2_CLKX 0x019a
|
||||
#define ABEMCPDM_UL_DATA 0x019c
|
||||
#define ABEMCPDM_DL_DATA 0x019e
|
||||
#define ABEMCPDM_FRAME 0x01a0
|
||||
#define ABEMCPDM_LB_CLK 0x01a2
|
||||
#define WLSDIO_CLK 0x01a4
|
||||
#define WLSDIO_CMD 0x01a6
|
||||
#define WLSDIO_DATA0 0x01a8
|
||||
#define WLSDIO_DATA1 0x01aa
|
||||
#define WLSDIO_DATA2 0x01ac
|
||||
#define WLSDIO_DATA3 0x01ae
|
||||
#define UART5_RX 0x01b0
|
||||
#define UART5_TX 0x01b2
|
||||
#define UART5_CTS 0x01b4
|
||||
#define UART5_RTS 0x01b6
|
||||
#define I2C2_SCL 0x01b8
|
||||
#define I2C2_SDA 0x01ba
|
||||
#define MCSPI1_CLK 0x01bc
|
||||
#define MCSPI1_SOMI 0x01be
|
||||
#define MCSPI1_SIMO 0x01c0
|
||||
#define MCSPI1_CS0 0x01c2
|
||||
#define MCSPI1_CS1 0x01c4
|
||||
#define I2C5_SCL 0x01c6
|
||||
#define I2C5_SDA 0x01c8
|
||||
#define PERSLIMBUS2_CLOCK 0x01ca
|
||||
#define PERSLIMBUS2_DATA 0x01cc
|
||||
#define UART6_TX 0x01ce
|
||||
#define UART6_RX 0x01d0
|
||||
#define UART6_CTS 0x01d2
|
||||
#define UART6_RTS 0x01d4
|
||||
#define UART3_CTS_RCTX 0x01d6
|
||||
#define UART3_RTS_IRSD 0x01d8
|
||||
#define UART3_TX_IRTX 0x01da
|
||||
#define UART3_RX_IRRX 0x01dc
|
||||
#define USBB3_HSIC_STROBE 0x01de
|
||||
#define USBB3_HSIC_DATA 0x01e0
|
||||
#define SDCARD_CLK 0x01e2
|
||||
#define SDCARD_CMD 0x01e4
|
||||
#define SDCARD_DATA2 0x01e6
|
||||
#define SDCARD_DATA3 0x01e8
|
||||
#define SDCARD_DATA0 0x01ea
|
||||
#define SDCARD_DATA1 0x01ec
|
||||
#define USBD0_HS_DP 0x01ee
|
||||
#define USBD0_HS_DM 0x01f0
|
||||
#define I2C1_PMIC_SCL 0x01f2
|
||||
#define I2C1_PMIC_SDA 0x01f4
|
||||
#define USBD0_SS_RX 0x01f6
|
||||
|
||||
#define LLIA_WAKEREQIN 0x0040
|
||||
#define LLIB_WAKEREQIN 0x0042
|
||||
#define DRM_EMU0 0x0044
|
||||
#define DRM_EMU1 0x0046
|
||||
#define JTAG_NTRST 0x0048
|
||||
#define JTAG_TCK 0x004a
|
||||
#define JTAG_RTCK 0x004c
|
||||
#define JTAG_TMSC 0x004e
|
||||
#define JTAG_TDI 0x0050
|
||||
#define JTAG_TDO 0x0052
|
||||
#define SYS_32K 0x0054
|
||||
#define FREF_CLK_IOREQ 0x0056
|
||||
#define FREF_CLK0_OUT 0x0058
|
||||
#define FREF_CLK1_OUT 0x005a
|
||||
#define FREF_CLK2_OUT 0x005c
|
||||
#define FREF_CLK2_REQ 0x005e
|
||||
#define FREF_CLK1_REQ 0x0060
|
||||
#define SYS_NRESPWRON 0x0062
|
||||
#define SYS_NRESWARM 0x0064
|
||||
#define SYS_PWR_REQ 0x0066
|
||||
#define SYS_NIRQ1 0x0068
|
||||
#define SYS_NIRQ2 0x006a
|
||||
#define SR_PMIC_SCL 0x006c
|
||||
#define SR_PMIC_SDA 0x006e
|
||||
#define SYS_BOOT0 0x0070
|
||||
#define SYS_BOOT1 0x0072
|
||||
#define SYS_BOOT2 0x0074
|
||||
#define SYS_BOOT3 0x0076
|
||||
#define SYS_BOOT4 0x0078
|
||||
#define SYS_BOOT5 0x007a
|
||||
|
||||
#endif /* _MUX_OMAP5_H_ */
|
||||
|
|
@ -31,8 +31,6 @@
|
|||
.long \sym\()_hi32
|
||||
.endm
|
||||
|
||||
.globl _start
|
||||
_start:
|
||||
/*
|
||||
* DO NOT MODIFY. Image header expected by Linux boot-loaders.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2014 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __IPROC_COMMON_CONFIGS_H
|
||||
#define __IPROC_COMMON_CONFIGS_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/* Memory Info */
|
||||
#define CFG_SYS_SDRAM_BASE 0x61000000
|
||||
|
||||
#endif /* __IPROC_COMMON_CONFIGS_H */
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: <SPDX License Expression> */
|
||||
/*
|
||||
* Copyright 2019 Broadcom
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __IPROC_SDHCI_H
|
||||
#define __IPROC_SDHCI_H
|
||||
|
||||
int iproc_sdhci_init(int dev_index, u32 quirks);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Broadcom Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __KONA_SDHCI_H
|
||||
#define __KONA_SDHCI_H
|
||||
|
||||
int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef __ASM_LINKAGE_H
|
||||
#define __ASM_LINKAGE_H
|
||||
|
||||
#define __ALIGN .align 0
|
||||
#define __ALIGN_STR ".align 0"
|
||||
#define __ALIGN .p2align 2
|
||||
#define __ALIGN_STR ".p2align 2"
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,19 +1,2 @@
|
|||
#ifndef _ASM_ARM_UNALIGNED_H
|
||||
#define _ASM_ARM_UNALIGNED_H
|
||||
|
||||
#include <linux/unaligned/le_byteshift.h>
|
||||
#include <linux/unaligned/be_byteshift.h>
|
||||
#include <linux/unaligned/generic.h>
|
||||
|
||||
/*
|
||||
* Select endianness
|
||||
*/
|
||||
#if __BYTE_ORDER == __LITTLE_ENDIAN
|
||||
#define get_unaligned __get_unaligned_le
|
||||
#define put_unaligned __put_unaligned_le
|
||||
#else
|
||||
#define get_unaligned __get_unaligned_be
|
||||
#define put_unaligned __put_unaligned_be
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARM_UNALIGNED_H */
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#include <asm-generic/unaligned.h>
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010
|
||||
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
|
||||
*
|
||||
* Real-time Timer
|
||||
* Based on AT91SAM9XE datasheet
|
||||
*/
|
||||
|
||||
#ifndef AT91_RTT_H
|
||||
#define AT91_RTT_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef struct at91_rtt {
|
||||
u32 mr; /* Mode Register RW 0x00008000 */
|
||||
u32 ar; /* Alarm Register RW 0xFFFFFFFF */
|
||||
u32 vr; /* Value Register RO 0x00000000 */
|
||||
u32 sr; /* Status Register RO 0x00000000 */
|
||||
} at91_rtt_t;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define AT91_RTT_MR_RTPRES 0x0000ffff
|
||||
#define AT91_RTT_MR_ALMIEN 0x00010000
|
||||
#define AT91_RTT_RTTINCIEN 0x00020000
|
||||
#define AT91_RTT_RTTRST 0x00040000
|
||||
|
||||
#define AT91_RTT_SR_ALMS 0x00000001
|
||||
#define AT91_RTT_SR_RTTINC 0x00000002
|
||||
|
||||
#endif
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*/
|
||||
#ifndef _DV_AINTC_DEFS_H_
|
||||
#define _DV_AINTC_DEFS_H_
|
||||
|
||||
struct dv_aintc_regs {
|
||||
unsigned int fiq0; /* 0x00 */
|
||||
unsigned int fiq1; /* 0x04 */
|
||||
unsigned int irq0; /* 0x08 */
|
||||
unsigned int irq1; /* 0x0c */
|
||||
unsigned int fiqentry; /* 0x10 */
|
||||
unsigned int irqentry; /* 0x14 */
|
||||
unsigned int eint0; /* 0x18 */
|
||||
unsigned int eint1; /* 0x1c */
|
||||
unsigned int intctl; /* 0x20 */
|
||||
unsigned int eabase; /* 0x24 */
|
||||
unsigned char rsvd0[8]; /* 0x28 */
|
||||
unsigned int intpri0; /* 0x30 */
|
||||
unsigned int intpri1; /* 0x34 */
|
||||
unsigned int intpri2; /* 0x38 */
|
||||
unsigned int intpri3; /* 0x3c */
|
||||
unsigned int intpri4; /* 0x40 */
|
||||
unsigned int intpri5; /* 0x44 */
|
||||
unsigned int intpri6; /* 0x48 */
|
||||
unsigned int intpri7; /* 0x4c */
|
||||
};
|
||||
|
||||
#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
|
||||
|
||||
#define DV_AINTC_INTCTL_IDMODE (1 << 2)
|
||||
|
||||
#endif /* _DV_AINTC_DEFS_H_ */
|
||||
|
|
@ -54,7 +54,7 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o
|
|||
ifneq ($(CONFIG_SPL_BUILD),y)
|
||||
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
|
||||
endif
|
||||
obj-$(CONFIG_SATA) += sata.o
|
||||
obj-$(CONFIG_$(SPL_)SATA) += sata.o
|
||||
obj-$(CONFIG_IMX_HAB) += hab.o
|
||||
obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -15,6 +15,15 @@
|
|||
#include <dm/uclass-internal.h>
|
||||
#include <dm/pinctrl.h>
|
||||
|
||||
#define RTC_BASE_ADDRESS 0x2b1f0000
|
||||
#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18)
|
||||
#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70)
|
||||
#define REG_K3RTC_KICK1 (RTC_BASE_ADDRESS + 0x74)
|
||||
|
||||
/* Magic values for lock/unlock */
|
||||
#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13
|
||||
#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0
|
||||
|
||||
/*
|
||||
* This uninitialized global variable would normal end up in the .bss section,
|
||||
* but the .bss is cleared between writing and reading this variable, so move
|
||||
|
|
@ -71,6 +80,42 @@ static __maybe_unused void enable_mcu_esm_reset(void)
|
|||
writel(stat, CTRLMMR_MCU_RST_CTRL);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_V7R)
|
||||
|
||||
/*
|
||||
* RTC Erratum i2327 Workaround for Silicon Revision 1
|
||||
*
|
||||
* Due to a bug in initial synchronization out of cold power on,
|
||||
* IRQ status can get locked infinitely if we do not unlock RTC
|
||||
*
|
||||
* This workaround *must* be applied within 1 second of power on,
|
||||
* So, this is closest point to be able to guarantee the max
|
||||
* timing.
|
||||
*
|
||||
* https://www.ti.com/lit/er/sprz487c/sprz487c.pdf
|
||||
*/
|
||||
void rtc_erratumi2327_init(void)
|
||||
{
|
||||
u32 counter;
|
||||
|
||||
/*
|
||||
* If counter has gone past 1, nothing we can do, leave
|
||||
* system locked! This is the only way we know if RTC
|
||||
* can be used for all practical purposes.
|
||||
*/
|
||||
counter = readl(REG_K3RTC_S_CNT_LSW);
|
||||
if (counter > 1)
|
||||
return;
|
||||
/*
|
||||
* Need to set this up at the very start
|
||||
* MUST BE DONE under 1 second of boot.
|
||||
*/
|
||||
writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0);
|
||||
writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
|
@ -78,6 +123,7 @@ void board_init_f(ulong dummy)
|
|||
|
||||
#if defined(CONFIG_CPU_V7R)
|
||||
setup_k3_mpu_regions();
|
||||
rtc_erratumi2327_init();
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -222,11 +222,59 @@ struct mm_region *mem_map = j721s2_mem_map;
|
|||
|
||||
#endif /* CONFIG_SOC_K3_J721S2 */
|
||||
|
||||
#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \
|
||||
defined(CONFIG_SOC_K3_AM62A7)
|
||||
#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
|
||||
|
||||
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
||||
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
|
||||
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
|
||||
|
||||
/* ToDo: Add 64bit IO */
|
||||
struct mm_region am62_mem_map[NR_MMU_REGIONS] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
.virt = 0x80000000UL,
|
||||
.phys = 0x80000000UL,
|
||||
.size = 0x1E780000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xA0000000UL,
|
||||
.phys = 0xA0000000UL,
|
||||
.size = 0x60000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
|
||||
}, {
|
||||
.virt = 0x880000000UL,
|
||||
.phys = 0x880000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0x500000000UL,
|
||||
.phys = 0x500000000UL,
|
||||
.size = 0x400000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = am62_mem_map;
|
||||
#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
|
||||
|
||||
#ifdef CONFIG_SOC_K3_AM642
|
||||
|
||||
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
|
||||
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4)
|
||||
|
||||
/* ToDo: Add 64bit IO */
|
||||
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
|
||||
|
|
@ -240,7 +288,13 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
|
|||
}, {
|
||||
.virt = 0x80000000UL,
|
||||
.phys = 0x80000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.size = 0x1E800000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xA0000000UL,
|
||||
.phys = 0xA0000000UL,
|
||||
.size = 0x60000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
|
|
@ -263,4 +317,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
|
|||
};
|
||||
|
||||
struct mm_region *mem_map = am64_mem_map;
|
||||
#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
|
||||
#endif /* CONFIG_SOC_K3_AM642 */
|
||||
|
|
|
|||
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Reference in a new issue