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Removes all board specific code from the arch. part for DM644x (DaVinci) boards

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Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
This commit is contained in:
Pieter Voorthuijsen 2008-03-30 11:11:34 +01:00 • committed by Peter Pearse
parent 1704dc2091
commit 1377b5583a
6 changed files with 130 additions and 73 deletions
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79
cpu/arm926ejs/davinci/lowlevel_init.S
View file

@ -3,6 +3,11 @@
* *
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
* *
* Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
* Changed:
* Made board specific defines such as DDR timing and PLL
* dividers. These should be set in the board config file
*
* Partially based on TI sources, original copyrights follow: * Partially based on TI sources, original copyrights follow:
*/ */
@ -156,17 +161,17 @@ WaitPPL2Loop:
/* Program the PLL Multiplier */ /* Program the PLL Multiplier */
ldr r6, PLL2_PLLM ldr r6, PLL2_PLLM
mov r2, $0x17 /* 162 MHz */ mov r2, $CFG_DAVINCI_PLL2_PLLM
str r2, [r6] str r2, [r6]
/* Program the PLL2 Divisor Value */ /* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV2 ldr r6, PLL2_DIV2
mov r3, $0x01 mov r3, $CFG_DAVINCI_PLL2_DIV2
str r3, [r6] str r3, [r6]
/* Program the PLL2 Divisor Value */ /* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV1 ldr r6, PLL2_DIV1
mov r4, $0x0b /* 54 MHz */ mov r4, $CFG_DAVINCI_PLL2_DIV1
str r4, [r6] str r4, [r6]
/* PLL2 DIV2 MMR */ /* PLL2 DIV2 MMR */
@ -273,7 +278,7 @@ checkDDRStatClkStop:
bne checkDDRStatClkStop bne checkDDRStatClkStop
/*------------------------------------------------------* /*------------------------------------------------------*
* Program DDR2 MMRs for 162MHz Setting * * Program DDR2 MMRs *
*------------------------------------------------------*/ *------------------------------------------------------*/
/* Program PHY Control Register */ /* Program PHY Control Register */
@ -288,12 +293,12 @@ checkDDRStatClkStop:
/* Program SDRAM TIM-0 Config Register */ /* Program SDRAM TIM-0 Config Register */
ldr r6, SDTIM0 ldr r6, SDTIM0
ldr r7, SDTIM0_VAL_162MHz ldr r7, SDTIM0_VAL
str r7, [r6] str r7, [r6]
/* Program SDRAM TIM-1 Config Register */ /* Program SDRAM TIM-1 Config Register */
ldr r6, SDTIM1 ldr r6, SDTIM1
ldr r7, SDTIM1_VAL_162MHz ldr r7, SDTIM1_VAL
str r7, [r6] str r7, [r6]
/* Program the SDRAM Bank Config Control Register */ /* Program the SDRAM Bank Config Control Register */
@ -435,7 +440,7 @@ WaitLoop:
/* Program the PLL Multiplier */ /* Program the PLL Multiplier */
ldr r6, PLL1_PLLM ldr r6, PLL1_PLLM
mov r3, $0x15 /* For 594MHz */ mov r3, $CFG_DAVINCI_PLL1_PLLM
str r3, [r6] str r3, [r6]
/* Wait for PLL to Reset Properly */ /* Wait for PLL to Reset Properly */
@ -467,7 +472,7 @@ PLL1Lock:
nop nop
/*------------------------------------------------------* /*------------------------------------------------------*
* AEMIF configuration for NOR Flash (double check) * * AEMIF configuration for NAND/NOR Flash *
*------------------------------------------------------*/ *------------------------------------------------------*/
ldr r0, _PINMUX0 ldr r0, _PINMUX0
ldr r1, _DEV_SETTING ldr r1, _DEV_SETTING
@ -479,6 +484,12 @@ PLL1Lock:
orr r2, r2, r1 orr r2, r2, r1
str r2, [r0] str r2, [r0]
ldr r0, ACFG2
ldr r1, ACFG2_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
ldr r0, ACFG3 ldr r0, ACFG3
ldr r1, ACFG3_VAL ldr r1, ACFG3_VAL
ldr r2, [r0] ldr r2, [r0]
@ -497,6 +508,12 @@ PLL1Lock:
and r1, r2, r1 and r1, r2, r1
str r1, [r0] str r1, [r0]
ldr r0, NANDFCR
ldr r1, NANDFCR_VAL
ldr r2, [r0]
and r1, r2, r1
str r1, [r0]
/*--------------------------------------* /*--------------------------------------*
* VTP manual Calibration * * VTP manual Calibration *
*--------------------------------------*/ *--------------------------------------*/
@ -560,24 +577,36 @@ _PINMUX1:
.word 0x01c40004 /* Device Configuration Registers */ .word 0x01c40004 /* Device Configuration Registers */
_DEV_SETTING: _DEV_SETTING:
.word 0x00000c1f .word CFG_DAVINCI_PINMUX_0
WAITCFG: WAITCFG:
.word 0x01e00004 .word 0x01e00004
WAITCFG_VAL: WAITCFG_VAL:
.word 0 .word CFG_DAVINCI_WAITCFG
ACFG2:
.word 0x01e00010
ACFG2_VAL:
.word CFG_DAVINCI_ACFG2
ACFG3: ACFG3:
.word 0x01e00014 .word 0x01e00014
ACFG3_VAL: ACFG3_VAL:
.word 0x3ffffffd .word CFG_DAVINCI_ACFG3
ACFG4: ACFG4:
.word 0x01e00018 .word 0x01e00018
ACFG4_VAL: ACFG4_VAL:
.word 0x3ffffffd .word CFG_DAVINCI_ACFG4
ACFG5: ACFG5:
.word 0x01e0001c .word 0x01e0001c
ACFG5_VAL: ACFG5_VAL:
.word 0x3ffffffd .word CFG_DAVINCI_ACFG5
NANDFCR:
.word 0x01e00060
NANDFCR_VAL:
#ifdef CFG_DAVINCI_NANDCE
.word (1 << (CFG_DAVINCI_NANDCE - 2))
#else
.word 0x00000000
#endif
MDCTL_DDR2: MDCTL_DDR2:
.word 0x01c41a34 .word 0x01c41a34
@ -599,33 +628,27 @@ PSC_FLAG_CLEAR:
PSC_GEM_FLAG_CLEAR: PSC_GEM_FLAG_CLEAR:
.word 0xfffffeff .word 0xfffffeff
/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */ /* DDR2 MMR & CONFIGURATION VALUES */
DDRCTL: DDRCTL:
.word 0x200000e4 .word 0x200000e4
DDRCTL_VAL: DDRCTL_VAL:
.word 0x50006405 .word CFG_DAVINCI_DDRCTL
SDREF: SDREF:
.word 0x2000000c .word 0x2000000c
SDREF_VAL: SDREF_VAL:
.word 0x000005c3 .word CFG_DAVINCI_SDREF
SDCFG: SDCFG:
.word 0x20000008 .word 0x20000008
SDCFG_VAL: SDCFG_VAL:
#ifdef DDR_4BANKS .word CFG_DAVINCI_SDCFG
.word 0x00178622
#elif defined DDR_8BANKS
.word 0x00178632
#else
#error "Unknown DDR configuration!!!"
#endif
SDTIM0: SDTIM0:
.word 0x20000010 .word 0x20000010
SDTIM0_VAL_162MHz: SDTIM0_VAL:
.word 0x28923211 .word CFG_DAVINCI_SDTIM0
SDTIM1: SDTIM1:
.word 0x20000014 .word 0x20000014
SDTIM1_VAL_162MHz: SDTIM1_VAL:
.word 0x0016c722 .word CFG_DAVINCI_SDTIM1
VTPIOCR: VTPIOCR:
.word 0x200000f0 /* VTP IO Control register */ .word 0x200000f0 /* VTP IO Control register */
DDRVTPR: DDRVTPR:
@ -699,7 +722,7 @@ PLL2_DIV_MASK:
MMARG_BRF0: MMARG_BRF0:
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/ .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
MMARG_BRF0_VAL: MMARG_BRF0_VAL:
.word 0x00444400 .word CFG_DAVINCI_MMARG_BRF0
DDR2_START_ADDR: DDR2_START_ADDR:
.word 0x80000000 .word 0x80000000

41
cpu/arm926ejs/davinci/nand.c
View file

@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
dummy = emif_addr->NANDF3ECC; dummy = emif_addr->NANDF3ECC;
dummy = emif_addr->NANDF4ECC; dummy = emif_addr->NANDF4ECC;
emif_addr->NANDFCR |= (1 << 8); emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
} }
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
region = 1; region = (CFG_DAVINCI_NANDCE - 1);
while (n--) { while (n--) {
tmp = nand_davinci_readecc(mtd, region); tmp = nand_davinci_readecc(mtd, region);
*ecc_code++ = tmp; *ecc_code++ = tmp;
@ -311,40 +311,9 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i
static void nand_flash_init(void) static void nand_flash_init(void)
{ {
u_int32_t acfg1 = 0x3ffffffc; /* All EMIF initialization is done in lowlevel_init.S
u_int32_t acfg2 = 0x3ffffffc; * and config values are in the board config files
u_int32_t acfg3 = 0x3ffffffc; */
u_int32_t acfg4 = 0x3ffffffc;
emifregs emif_regs;
/*------------------------------------------------------------------*
* NAND FLASH CHIP TIMEOUT @ 459 MHz *
* *
* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
* *
*------------------------------------------------------------------*/
acfg1 = 0
| (0 << 31 ) /* selectStrobe */
| (0 << 30 ) /* extWait */
| (1 << 26 ) /* writeSetup 10 ns */
| (3 << 20 ) /* writeStrobe 40 ns */
| (1 << 17 ) /* writeHold 10 ns */
| (1 << 13 ) /* readSetup 10 ns */
| (5 << 7 ) /* readStrobe 60 ns */
| (1 << 4 ) /* readHold 10 ns */
| (3 << 2 ) /* turnAround ?? ns */
| (0 << 0 ) /* asyncSize 8-bit bus */
;
emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
emif_regs->AWCCR |= 0x10000000;
emif_regs->AB1CR = acfg1; /* 0x08244128 */;
emif_regs->AB2CR = acfg2;
emif_regs->AB3CR = acfg3;
emif_regs->AB4CR = acfg4;
emif_regs->NANDFCR = 0x00000101;
} }
int board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)

2
include/asm-arm/arch-davinci/hardware.h
View file

@ -150,6 +150,8 @@ typedef volatile unsigned int * dv_reg_p;
#define VDD3P3V_PWDN (0x01c40048) #define VDD3P3V_PWDN (0x01c40048)
#define UART0_PWREMU_MGMT (0x01c20030) #define UART0_PWREMU_MGMT (0x01c20030)
#define UART1_PWREMU_MGMT (0x01c20430)
#define UART2_PWREMU_MGMT (0x01c20830)
#define PSC_SILVER_BULLET (0x01c41a20) #define PSC_SILVER_BULLET (0x01c41a20)

32
include/configs/davinci_dvevm.h
View file

@ -52,6 +52,9 @@
#define DV_EVM #define DV_EVM
#define CFG_NAND_SMALLPAGE #define CFG_NAND_SMALLPAGE
#define CFG_USE_NOR #define CFG_USE_NOR
#define CFG_USE_INTEL_NOR /* Define this when your DVEVM has Intel
* flash instead of AMD flash
*/
/*===================*/ /*===================*/
/* SoC Configuration */ /* SoC Configuration */
/*===================*/ /*===================*/
@ -60,6 +63,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000 #define CFG_HZ 1000
#define CFG_DAVINCI_PINMUX_0 0x00000c1f
#define CFG_DAVINCI_WAITCFG 0x00000000
#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
#define CFG_DAVINCI_ACFG3 0x3ffffffd
#define CFG_DAVINCI_ACFG4 0x3ffffffd
#define CFG_DAVINCI_ACFG5 0x3ffffffd
#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
#define CFG_DAVINCI_SDREF 0x000005c3
#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
#define CFG_DAVINCI_SDTIM0 0x28923211
#define CFG_DAVINCI_SDTIM1 0x0016c722
#define CFG_DAVINCI_MMARG_BRF0 0x00444400
/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
#define CFG_DAVINCI_PLL1_PLLM 0x15
#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/ /*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
@ -143,13 +164,20 @@
#define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI #define CFG_FLASH_CFI
#define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
#define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) #define CFG_ENV_OFFSET (CFG_ENV_ADDR)
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ #define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ #define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ #define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) #define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */
#ifdef CFG_USE_INTEL_NOR
#define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size INTEL Flash */
#define CFG_FLASH_PROTECTION 1
#else
#define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
#endif
#endif #endif
/*==============================*/ /*==============================*/
/* U-Boot general configuration */ /* U-Boot general configuration */

19
include/configs/davinci_schmoogie.h
View file

@ -35,6 +35,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000 #define CFG_HZ 1000
#define CFG_DAVINCI_PINMUX_0 0x00000c1f
#define CFG_DAVINCI_WAITCFG 0x00000000
#define CFG_DAVINCI_ACFG2 0x0432229c /* CE configs */
#define CFG_DAVINCI_ACFG3 0x3ffffffd
#define CFG_DAVINCI_ACFG4 0x3ffffffd
#define CFG_DAVINCI_ACFG5 0x3ffffffd
#define CFG_DAVINCI_NANDCE 2 /* When using NAND, define 2,3 or 4 */
#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
#define CFG_DAVINCI_SDREF 0x000005c3
#define CFG_DAVINCI_SDCFG 0x00178622 /* 4 banks */
#define CFG_DAVINCI_SDTIM0 0x28923211
#define CFG_DAVINCI_SDTIM1 0x0016c722
#define CFG_DAVINCI_MMARG_BRF0 0x00444400
/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
#define CFG_DAVINCI_PLL1_PLLM 0x15
#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
#define CFG_DAVINCI_PLL2_DIV2 0x01
/*=============*/ /*=============*/
/* Memory Info */ /* Memory Info */
/*=============*/ /*=============*/
@ -46,7 +64,6 @@
#define CONFIG_STACKSIZE (256*1024) /* regular stack */ #define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ #define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/ /*====================*/
/* Serial Driver info */ /* Serial Driver info */
/*====================*/ /*====================*/

18
include/configs/davinci_sonata.h
View file

@ -60,6 +60,24 @@
#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ #define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CFG_HZ 1000 #define CFG_HZ 1000
#define CFG_DAVINCI_PINMUX_0 0x00000c1f
#define CFG_DAVINCI_WAITCFG 0x00000000
#define CFG_DAVINCI_ACFG2 0x3ffffffd /* CE configs */
#define CFG_DAVINCI_ACFG3 0x3ffffffd
#define CFG_DAVINCI_ACFG4 0x3ffffffd
#define CFG_DAVINCI_ACFG5 0x3ffffffd
#undef CFG_DAVINCI_NANDCE /* When using NAND, define 2,3 or 4 */
#define CFG_DAVINCI_DDRCTL 0x50006405 /* DDR timing config */
#define CFG_DAVINCI_SDREF 0x000005c3
#define CFG_DAVINCI_SDCFG 0x00178632 /* 8 banks */
#define CFG_DAVINCI_SDTIM0 0x28923211
#define CFG_DAVINCI_SDTIM1 0x0016c722
#define CFG_DAVINCI_MMARG_BRF0 0x00444400
/* DM6446 = 0x15, DM6441 = 0x12, DM6441_LV = 0x0e */
#define CFG_DAVINCI_PLL1_PLLM 0x15
#define CFG_DAVINCI_PLL2_PLLM 0x17 /* 162 MHz */
#define CFG_DAVINCI_PLL2_DIV1 0x0b /* 54 MHz */
#define CFG_DAVINCI_PLL2_DIV2 0x01
/*====================================================*/ /*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */