mmc: sdhci: use the SDHCI_QUIRK_USE_WIDE8 for samsung SoC

Samsung SoC is supported the WIDE8, even if Controller version is v2.0.
So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
This commit is contained in:
Jaehoon Chung 2013-07-19 17:44:49 +09:00 committed by Pantelis Antoniou
parent 46ef4faed1
commit 113e5dfcd7
3 changed files with 13 additions and 7 deletions

View file

@ -72,7 +72,7 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD; SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
@ -81,6 +81,8 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
host->index = index; host->index = index;
host->host_caps = MMC_MODE_HC; host->host_caps = MMC_MODE_HC;
if (bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
return add_sdhci(host, 52000000, 400000); return add_sdhci(host, 52000000, 400000);
} }

View file

@ -254,7 +254,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
if (clock == 0) if (clock == 0)
return 0; return 0;
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */ /* Version 3.00 divisors must be a multiple of 2. */
if (mmc->f_max <= clock) if (mmc->f_max <= clock)
div = 1; div = 1;
@ -347,10 +347,11 @@ void sdhci_set_ios(struct mmc *mmc)
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) { if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS; ctrl &= ~SDHCI_CTRL_4BITBUS;
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
(host->quirks & SDHCI_QUIRK_USE_WIDE8))
ctrl |= SDHCI_CTRL_8BITBUS; ctrl |= SDHCI_CTRL_8BITBUS;
} else { } else {
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS; ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4) if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS; ctrl |= SDHCI_CTRL_4BITBUS;
@ -437,7 +438,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
if (max_clk) if (max_clk)
mmc->f_max = max_clk; mmc->f_max = max_clk;
else { else {
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT; >> SDHCI_CLOCK_BASE_SHIFT;
else else
@ -452,7 +453,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
if (min_clk) if (min_clk)
mmc->f_min = min_clk; mmc->f_min = min_clk;
else { else {
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300; mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
else else
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200; mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
@ -470,7 +471,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
mmc->voltages |= host->voltages; mmc->voltages |= host->voltages;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
if (caps & SDHCI_CAN_DO_8BIT) if (caps & SDHCI_CAN_DO_8BIT)
mmc->host_caps |= MMC_MODE_8BIT; mmc->host_caps |= MMC_MODE_8BIT;
} }

View file

@ -192,6 +192,8 @@
#define SDHCI_SPEC_200 1 #define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2 #define SDHCI_SPEC_300 2
#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
/* /*
* End of controller registers. * End of controller registers.
*/ */
@ -210,6 +212,7 @@
#define SDHCI_QUIRK_NO_CD (1 << 5) #define SDHCI_QUIRK_NO_CD (1 << 5)
#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7) #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7)
#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
/* to make gcc happy */ /* to make gcc happy */
struct sdhci_host; struct sdhci_host;