mirror of
https://github.com/u-boot/u-boot.git
synced 2025-05-09 03:21:51 +00:00
fix various comments
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
This commit is contained in:
parent
7817cb2083
commit
10c7382bc5
5 changed files with 25 additions and 26 deletions
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@ -57,7 +57,7 @@ _fiq: .word fiq
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* Startup Code (reset vector)
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* Startup Code (reset vector)
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*
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*
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* do important init only if we don't start from RAM!
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* do important init only if we don't start from RAM!
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* - relocate armboot to ram
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* - relocate armboot to RAM
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* - setup stack
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* - setup stack
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* - jump to second stage
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* - jump to second stage
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*/
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*/
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@ -90,7 +90,7 @@ IRQ_STACK_START:
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.globl FIQ_STACK_START
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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FIQ_STACK_START:
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.word 0x0badc0de
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.word 0x0badc0de
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#endif
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#endif /* CONFIG_USE_IRQ */
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/****************************************************************************/
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/****************************************************************************/
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@ -100,18 +100,18 @@ FIQ_STACK_START:
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/****************************************************************************/
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/****************************************************************************/
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reset:
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reset:
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mrs r0,cpsr /* set the cpu to SVC32 mode */
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mrs r0,cpsr /* set the CPU to SVC32 mode */
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bic r0,r0,#0x1f /* (superviser mode, M=10011) */
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bic r0,r0,#0x1f /* (superviser mode, M=10011) */
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orr r0,r0,#0x13
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orr r0,r0,#0x13
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msr cpsr,r0
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msr cpsr,r0
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/*
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/*
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* we do sys-critical inits only at reboot,
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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* not when booting from RAM!
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*/
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit /* we do sys-critical inits */
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bl cpu_init_crit /* we do sys-critical inits */
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#endif
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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relocate: /* relocate U-Boot to RAM */
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relocate: /* relocate U-Boot to RAM */
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@ -130,7 +130,7 @@ copy_loop:
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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ble copy_loop
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#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
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#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
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/* Set up the stack */
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/* Set up the stack */
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stack_setup:
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stack_setup:
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@ -139,7 +139,7 @@ stack_setup:
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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#ifdef CONFIG_USE_IRQ
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#ifdef CONFIG_USE_IRQ
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
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#endif
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#endif /* CONFIG_USE_IRQ */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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clear_bss:
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@ -172,11 +172,11 @@ _start_armboot: .word start_armboot
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#undef OSCR
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#undef OSCR
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#undef OWER
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#undef OWER
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#undef OIER
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#undef OIER
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#endif
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#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
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#ifdef CONFIG_PXA250
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#ifdef CONFIG_PXA250
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#undef RCSR
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#undef RCSR
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#undef CCCR
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#undef CCCR
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#endif
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#endif /* CONFIG_PXA250 */
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/* Interrupt-Controller base address */
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/* Interrupt-Controller base address */
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IC_BASE: .word 0x40d00000
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IC_BASE: .word 0x40d00000
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@ -197,18 +197,18 @@ OSTIMER_BASE: .word 0x40a00000
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#ifdef CONFIG_CPU_MONAHANS
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#ifdef CONFIG_CPU_MONAHANS
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# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
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# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
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# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
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# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
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# endif
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# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */
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# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
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# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
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# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
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# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
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# endif
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# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */
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#else /* ! CONFIG_CPU_MONAHANS */
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#else /* !CONFIG_CPU_MONAHANS */
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#ifdef CFG_CPUSPEED
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#ifdef CFG_CPUSPEED
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CC_BASE: .word 0x41300000
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CC_BASE: .word 0x41300000
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#define CCCR 0x00
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#define CCCR 0x00
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cpuspeed: .word CFG_CPUSPEED
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cpuspeed: .word CFG_CPUSPEED
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#else
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#else /* !CFG_CPUSPEED */
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#error "You have to define CFG_CPUSPEED!!"
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#error "You have to define CFG_CPUSPEED!!"
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#endif
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#endif /* CFG_CPUSPEED */
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#endif /* CONFIG_CPU_MONAHANS */
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#endif /* CONFIG_CPU_MONAHANS */
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/* takes care the CP15 update has taken place */
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/* takes care the CP15 update has taken place */
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@ -225,7 +225,7 @@ cpu_init_crit:
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ldr r0, IC_BASE
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ldr r0, IC_BASE
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mov r1, #0x00
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mov r1, #0x00
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str r1, [r0, #ICMR]
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str r1, [r0, #ICMR]
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#else
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#else /* CONFIG_CPU_MONAHANS */
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/* Step 1 - Enable CP6 permission */
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/* Step 1 - Enable CP6 permission */
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mrc p15, 0, r1, c15, c1, 0 @ read CPAR
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mrc p15, 0, r1, c15, c1, 0 @ read CPAR
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orr r1, r1, #0x40
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orr r1, r1, #0x40
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@ -244,14 +244,14 @@ cpu_init_crit:
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ldr r1, =CKENB
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ldr r1, =CKENB
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ldr r2, =(CKENB_6_IRQ)
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ldr r2, =(CKENB_6_IRQ)
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str r2, [r1]
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str r2, [r1]
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#endif
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#endif /* !CONFIG_CPU_MONAHANS */
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/* set clock speed */
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/* set clock speed */
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#ifdef CONFIG_CPU_MONAHANS
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#ifdef CONFIG_CPU_MONAHANS
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ldr r0, =ACCR
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ldr r0, =ACCR
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ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
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ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
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str r1, [r0]
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str r1, [r0]
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#else /* ! CONFIG_CPU_MONAHANS */
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#else /* !CONFIG_CPU_MONAHANS */
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#ifdef CFG_CPUSPEED
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#ifdef CFG_CPUSPEED
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ldr r0, CC_BASE
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ldr r0, CC_BASE
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ldr r1, cpuspeed
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ldr r1, cpuspeed
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@ -451,7 +451,7 @@ fiq:
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bl do_fiq /* effiction fiq_save_user_regs */
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bl do_fiq /* effiction fiq_save_user_regs */
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irq_restore_user_regs
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irq_restore_user_regs
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#else
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#else /* !CONFIG_USE_IRQ */
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.align 5
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.align 5
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irq:
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irq:
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@ -465,7 +465,7 @@ fiq:
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bad_save_user_regs
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bad_save_user_regs
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bl do_fiq
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bl do_fiq
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#endif
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#endif /* CONFIG_USE_IRQ */
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/****************************************************************************/
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/****************************************************************************/
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/* */
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/* */
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@ -79,7 +79,7 @@ Commands:
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nand write.jffs2 addr ofs|partition size
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nand write.jffs2 addr ofs|partition size
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Like `write', but blocks that are marked bad are skipped and the
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Like `write', but blocks that are marked bad are skipped and the
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is written to the next block instead. This allows writing writing
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data is written to the next block instead. This allows writing
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a JFFS2 image, as long as the image is short enough to fit even
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a JFFS2 image, as long as the image is short enough to fit even
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after skipping the bad blocks. Compact images, such as those
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after skipping the bad blocks. Compact images, such as those
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produced by mkfs.jffs2 should work well, but loading an image copied
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produced by mkfs.jffs2 should work well, but loading an image copied
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@ -839,7 +839,7 @@ void uboot_push_packet_len(int len) {
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}
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}
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dp83902a_recv(&pbuf[0], len);
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dp83902a_recv(&pbuf[0], len);
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/*Just pass it to the upper layer*/
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/* Just pass it to the upper layer */
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NetReceive(&pbuf[0], len);
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NetReceive(&pbuf[0], len);
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}
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}
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@ -902,7 +902,6 @@ int eth_init(bd_t *bd) {
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}
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}
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void eth_halt() {
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void eth_halt() {
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PRINTK("### eth_halt\n");
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PRINTK("### eth_halt\n");
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if(initialized)
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if(initialized)
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dp83902a_stop();
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dp83902a_stop();
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}
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}
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int eth_rx() {
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int eth_rx() {
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dp83902a_poll();
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dp83902a_poll();
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return 1;
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return 1;
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}
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}
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int eth_send(volatile void *packet, int length) {
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int eth_send(volatile void *packet, int length) {
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@ -129,7 +129,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
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#define NAND_ECC_HW3_256 2
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#define NAND_ECC_HW3_256 2
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/* Hardware ECC 3 byte ECC per 512 Byte data */
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/* Hardware ECC 3 byte ECC per 512 Byte data */
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#define NAND_ECC_HW3_512 3
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#define NAND_ECC_HW3_512 3
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/* Hardware ECC 3 byte ECC per 512 Byte data */
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/* Hardware ECC 6 byte ECC per 512 Byte data */
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#define NAND_ECC_HW6_512 4
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#define NAND_ECC_HW6_512 4
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/* Hardware ECC 8 byte ECC per 512 Byte data */
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/* Hardware ECC 8 byte ECC per 512 Byte data */
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#define NAND_ECC_HW8_512 6
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#define NAND_ECC_HW8_512 6
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@ -73,7 +73,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
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nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
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nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
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/*
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/*
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* Read on byte
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* Read one byte
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*/
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*/
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if (this->read_byte(mtd) != 0xff)
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if (this->read_byte(mtd) != 0xff)
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return 1;
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return 1;
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