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ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository

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This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the
commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot").

This patch was created by following steps:

1. Replace all a38x files in U-Boot tree by files from upstream github
   Marvell mv-ddr-marvell repository.

2. Run following command to omit portions not relevant for a38x and ddr3:

    files=drivers/ddr/marvell/a38x/*
    sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files
    unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \
        -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
        -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
        -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files

3. Manually omit SPDX-License-Identifier changes from this patch as
   upstream license in  upstream github repository contains long license
   texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x ddr3 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch is removal of dead code and some fixes with
include files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2021-03-02 11:17:41 +01:00 • committed by Stefan Roese
parent a5fc099081
commit 107c3391b9
10 changed files with 6 additions and 40 deletions
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8
drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
View file

@ -6,8 +6,6 @@
#include "ddr3_init.h"
#include "mv_ddr_regs.h"
#include "ddr_training_ip_db.h"
#include <image.h>
#include <linux/delay.h>
#define PATTERN_1 0x55555555
#define PATTERN_2 0xaaaaaaaa
@ -614,9 +612,9 @@ int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
MASK_ALL_BITS));
}
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODPG_DATA_BUFFER_OFFS_REG,
load_addr, MASK_ALL_BITS));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS));
return MV_OK;
}