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ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository

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This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the
commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot").

This patch was created by following steps:

1. Replace all a38x files in U-Boot tree by files from upstream github
   Marvell mv-ddr-marvell repository.

2. Run following command to omit portions not relevant for a38x and ddr3:

    files=drivers/ddr/marvell/a38x/*
    sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files
    unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \
        -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
        -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
        -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files

3. Manually omit SPDX-License-Identifier changes from this patch as
   upstream license in  upstream github repository contains long license
   texts and U-Boot is using just SPDX-License-Identifier.

After applying this patch, a38x ddr3 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.

The only change in this patch is removal of dead code and some fixes with
include files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár 2021-03-02 11:17:41 +01:00 • committed by Stefan Roese
parent a5fc099081
commit 107c3391b9
10 changed files with 6 additions and 40 deletions
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11
drivers/ddr/marvell/a38x/ddr3_training.c
View file

@ -7,8 +7,6 @@
#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
#include <log.h>
#include <linux/delay.h>
#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
@ -207,7 +205,6 @@ static int ddr3_tip_pad_inv(void)
if (tm->interface_params[0].as_bus_params[sphy].
is_ck_swap == 1 && sphy == 0) {
/* TODO: move this code to per platform one */
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* clock swap for both cs0 and cs1 */
data = (INVERT_PAD << INV_PAD2_OFFS |
INVERT_PAD << INV_PAD6_OFFS |
@ -219,9 +216,6 @@ static int ddr3_tip_pad_inv(void)
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X */
#pragma message "unknown platform to configure ddr clock swap"
#endif
}
}
@ -2014,9 +2008,7 @@ int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2)
static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
{
/* TODO: enable this functionality for other platforms */
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
struct init_cntr_param init_cntr_prm;
#endif
int ret = MV_OK;
int adll_bypass_flag = 0;
u32 if_id;
@ -2050,7 +2042,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
}
/* TODO: enable this functionality for other platforms */
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
if (is_adll_calib_before_init != 0) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("with adll calib before init\n"));
@ -2081,7 +2072,6 @@ static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
return MV_FAIL;
}
}
#endif
ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
if (ret != MV_OK) {
@ -2905,3 +2895,4 @@ unsigned int mv_ddr_misl_phy_odt_n_get(void)
return odt_n;
}