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dt-bindings: exynos: Update bindings doc for DW MMC controller
Update the bindings doc for Exynos DW MMC block to follow the upstream example and reflect the latest changes made in corresponding Linux kernel bindings. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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1 changed files with 27 additions and 19 deletions
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@ -12,7 +12,9 @@ SOC specific and Board specific properties are channel specific.
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Required SoC Specific Properties:
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Required SoC Specific Properties:
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- compatible: should be
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- compatible: should be
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- samsung,exynos-dwmmc: for exynos platforms
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- samsung,exynos4412-dw-mshc: for Exynos4 platforms
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- samsung,exynos-dwmmc: for Exynos5 platforms
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- samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block)
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- reg: physical base address of the controller and length of memory mapped
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- reg: physical base address of the controller and length of memory mapped
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region.
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region.
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@ -23,32 +25,38 @@ Required Board Specific Properties:
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- #address-cells: should be 1.
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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- #size-cells: should be 0.
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- samsung,bus-width: The width of the bus used to interface the devices
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- bus-width: The width of the bus used to interface the devices
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supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
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supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
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. Typically the bus width is 4 or 8.
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. Typically the bus width is 4 or 8.
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- samsung,timing: The timing values to be written into the
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- samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu)
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Drv/sample clock selection register of corresponding channel.
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clock (0..7).
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. It is comprised of 3 values corresponding to the 3 fileds
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- samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode
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'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
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operation.
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. SelClk_sample: Select sample clock among 8 shifted clocks.
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. First value is CIU clock phase shift value for TX mode (0..7).
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. SelClk_drv: Select drv clock among 8 shifted clocks.
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. Second value is CIU clock phase shift value for RX mode (0..7).
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. DIVRATIO: Clock Divide ratio select.
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- samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode
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. The above 3 values are used by the clock phase shifter.
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operation. If missing, values from samsung,dw-mshc-sdr-timing are used.
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. First value is CIU clock phase shift value for TX mode (0..7).
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. Second value is CIU clock phase shift value for RX mode (0..7).
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Example:
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Example:
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mmc@12200000 {
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mmc@12200000 {
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samsung,bus-width = <8>;
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bus-width = <8>;
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samsung,timing = <1 3 3>;
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non-removable;
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samsung,removable = <1>;
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samsung,dw-mshc-ciu-div = <3>;
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}
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samsung,dw-mshc-sdr-timing = <1 3>;
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samsung,dw-mshc-ddr-timing = <0 2>;
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};
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In the above example,
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In the above example,
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. The bus width is 8
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. The bus width is 8
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. Timing is comprised of 3 values as explained below
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. Divider value for CLKSEL register is 3. The CIU clock rate will be
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calculated as SDCLKIN / (3 + 1).
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. SDR and DDR timings are comprised of 2 values as explained below
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1 - SelClk_sample
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1 - SelClk_sample
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3 - SelClk_drv
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3 - SelClk_drv
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3 - DIVRATIO
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. The 'non-removable' flag indicates whether the particular device
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. The 'removable' flag indicates whether the the particilar device
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cannot be removed (always present) or it is a removable device.
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cannot be removed (always present) or it is a removable device.
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1 - Indicates that the device is removable.
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Flag is present - Indicates that the device cannot be removed.
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0 - Indicates that the device cannot be removed.
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Flag is not present - Indicates that the device is removable.
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