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i.MX6SX: crypto/fsl: fix entropy delay value

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RNG Hardware error is reported due to incorrect entropy delay

rng self test are run to determine the correct ent_dly.
test is executed with different voltage and temperature to identify the
worst case value for ent_dly. after adding a margin value(1000),
ent_dly should be at least 12000.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Gaurav Jain 2022-04-15 16:40:49 +05:30 • committed by Stefano Babic
parent 9fd406de52
commit 0c45c77b8a
2 changed files with 15 additions and 2 deletions
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6
include/fsl_sec.h
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@ -48,7 +48,11 @@ struct rng4tst {
u32 rtmctl; /* misc. control register */
u32 rtscmisc; /* statistical check misc. register */
u32 rtpkrrng; /* poker range register */
#define RTSDCTL_ENT_DLY_MIN 3200
#ifdef CONFIG_MX6SX
#define RTSDCTL_ENT_DLY 12000
#else
#define RTSDCTL_ENT_DLY 3200
#endif
#define RTSDCTL_ENT_DLY_MAX 12800
union {
u32 rtpkrmax; /* PRGM=1: poker max. limit register */