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- khadas-vim3{l}: fix userdata size for android config
- drop A1 dtsi and other bindings includes in favor of Upstream ones -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmc05RgACgkQd9zb2sjI SdHGxA/+LNFIfZzvrDlDTUC40vTO194gn+Iw61wcypYA98lbh3CIxan2r0G2SYqf QMXOmKM6Qxlix6h4SZG3V96/zzgwaNkAobSK1/zsgw7ZcWb3n6Fh1hbuc6gSgQwN YpHyJ2KtX9/CvA9qeLupjVgjWzFAnHysgo5dxsjqnWI/7dRu9DUjyvVxzI67xh33 8bNoOQ5m1VjLZ1s+9KPN/o8G7gKdCzFapArgM3yKlbbVw2Lpb6MWBpQEI3WviErk srX+9GJqurwfIWZEEYQFumOJUoG5D7rvbh/mt8dTK2XNoaTUM7jua+xseRCb49gI Yl+fVsN/e28vDdkoWwWt/9bRJ1uZ+9UrUkoXBjpH4r0QGgDetB//nu1xWdyYVREU NdMQweOOW5VfMo31fVbrNi6xPDC7h6al8SCc2fX/ikdOJIWBl+vKh97Ni6Dwr6rq 8Ouwr8SIYgdei0M7dGvsHYHvRCclIWWg6xly7/6xChrQbjyc2qpjvSutRApd8Zmh sOamFYBQ3XUEL1y8CHNlt+xaQbBsSkk7F1g3WQsQWpGSmuFv/896zv9DEjILfBBk 3EJYbRizc6zF4GQdTvj9Z58nssbAkygT0v1yBVTu9JJRmDrWVfujODsqlJO3SXPS AHSD+OQfvB+41BbJvWgiLISWbyBM1GAjNp/4nBFx/L37iv4DZJg= =1dBl -----END PGP SIGNATURE----- Merge tag 'u-boot-amlogic-next-20241113' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - khadas-vim3{l}: fix userdata size for android config - drop A1 dtsi and other bindings includes in favor of Upstream ones
This commit is contained in:
Tom Rini
commit
030ec147af
11 changed files with 4 additions and 1113 deletions
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@ -1,518 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
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#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
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#include <dt-bindings/gpio/meson-a1-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/meson-a1-power.h>
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#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
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/ {
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compatible = "amlogic,a1";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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efuse: efuse {
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compatible = "amlogic,meson-gxbb-efuse";
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clocks = <&clkc_periphs CLKID_OTP>;
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#address-cells = <1>;
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#size-cells = <1>;
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secure-monitor = <&sm>;
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power-domains = <&pwrc PWRC_OTP_ID>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x800000>;
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alignment = <0x0 0x400000>;
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linux,cma-default;
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};
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};
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sm: secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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pwrc: power-controller {
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compatible = "amlogic,meson-a1-pwrc";
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#power-domain-cells = <1>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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spifc: spi@fd000400 {
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compatible = "amlogic,a1-spifc";
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reg = <0x0 0xfd000400 0x0 0x290>;
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clocks = <&clkc_periphs CLKID_SPIFC>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&pwrc PWRC_SPIFC_ID>;
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status = "disabled";
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};
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apb: bus@fe000000 {
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compatible = "simple-bus";
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reg = <0x0 0xfe000000 0x0 0x1000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
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reset: reset-controller@0 {
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compatible = "amlogic,meson-a1-reset";
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reg = <0x0 0x0 0x0 0x8c>;
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#reset-cells = <1>;
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};
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periphs_pinctrl: pinctrl@400 {
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compatible = "amlogic,meson-a1-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@400 {
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reg = <0x0 0x0400 0x0 0x003c>,
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<0x0 0x0480 0x0 0x0118>;
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reg-names = "mux", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&periphs_pinctrl 0 0 62>;
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};
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i2c0_f11_pins: i2c0-f11 {
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mux {
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groups = "i2c0_sck_f11",
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"i2c0_sda_f12";
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function = "i2c0";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c0_f9_pins: i2c0-f9 {
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mux {
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groups = "i2c0_sck_f9",
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"i2c0_sda_f10";
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function = "i2c0";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c1_x_pins: i2c1-x {
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mux {
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groups = "i2c1_sck_x",
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"i2c1_sda_x";
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function = "i2c1";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c1_a_pins: i2c1-a {
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mux {
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groups = "i2c1_sck_a",
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"i2c1_sda_a";
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function = "i2c1";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c2_x0_pins: i2c2-x0 {
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mux {
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groups = "i2c2_sck_x0",
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"i2c2_sda_x1";
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function = "i2c2";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c2_x15_pins: i2c2-x15 {
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mux {
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groups = "i2c2_sck_x15",
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"i2c2_sda_x16";
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function = "i2c2";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c2_a4_pins: i2c2-a4 {
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mux {
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groups = "i2c2_sck_a4",
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"i2c2_sda_a5";
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function = "i2c2";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c2_a8_pins: i2c2-a8 {
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mux {
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groups = "i2c2_sck_a8",
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"i2c2_sda_a9";
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function = "i2c2";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c3_x_pins: i2c3-x {
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mux {
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groups = "i2c3_sck_x",
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"i2c3_sda_x";
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function = "i2c3";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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i2c3_f_pins: i2c3-f {
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mux {
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groups = "i2c3_sck_f",
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"i2c3_sda_f";
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function = "i2c3";
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bias-pull-up;
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drive-strength-microamp = <3000>;
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};
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};
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uart_a_pins: uart-a {
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mux {
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groups = "uart_a_tx",
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"uart_a_rx";
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function = "uart_a";
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};
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};
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uart_a_cts_rts_pins: uart-a-cts-rts {
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mux {
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groups = "uart_a_cts",
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"uart_a_rts";
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function = "uart_a";
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bias-pull-down;
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};
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};
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sdio_pins: sdio {
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mux0 {
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groups = "sdcard_d0_x",
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"sdcard_d1_x",
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"sdcard_d2_x",
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"sdcard_d3_x",
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"sdcard_cmd_x";
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function = "sdcard";
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bias-pull-up;
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};
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mux1 {
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groups = "sdcard_clk_x";
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function = "sdcard";
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bias-disable;
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};
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};
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sdio_clk_gate_pins: sdio-clk-gate {
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mux {
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groups = "sdcard_clk_x";
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function = "sdcard";
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bias-pull-down;
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};
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};
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spifc_pins: spifc {
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mux {
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groups = "spif_mo",
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"spif_mi",
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"spif_clk",
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"spif_cs",
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"spif_hold_n",
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"spif_wp_n";
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function = "spif";
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};
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};
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};
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gpio_intc: interrupt-controller@440 {
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compatible = "amlogic,meson-a1-gpio-intc",
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"amlogic,meson-gpio-intc";
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reg = <0x0 0x0440 0x0 0x14>;
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interrupt-controller;
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#interrupt-cells = <2>;
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amlogic,channel-interrupts =
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<49 50 51 52 53 54 55 56>;
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};
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clkc_periphs: clock-controller@800 {
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compatible = "amlogic,a1-peripherals-clkc";
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reg = <0 0x800 0 0x104>;
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#clock-cells = <1>;
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clocks = <&clkc_pll CLKID_FCLK_DIV2>,
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<&clkc_pll CLKID_FCLK_DIV3>,
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<&clkc_pll CLKID_FCLK_DIV5>,
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<&clkc_pll CLKID_FCLK_DIV7>,
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<&clkc_pll CLKID_HIFI_PLL>,
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<&xtal>;
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clock-names = "fclk_div2", "fclk_div3",
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"fclk_div5", "fclk_div7",
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"hifi_pll", "xtal";
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};
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i2c0: i2c@1400 {
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compatible = "amlogic,meson-axg-i2c";
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status = "disabled";
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reg = <0x0 0x1400 0x0 0x20>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkc_periphs CLKID_I2C_M_A>;
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power-domains = <&pwrc PWRC_I2C_ID>;
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};
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uart_AO: serial@1c00 {
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compatible = "amlogic,meson-a1-uart",
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"amlogic,meson-ao-uart";
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reg = <0x0 0x1c00 0x0 0x18>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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uart_AO_B: serial@2000 {
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compatible = "amlogic,meson-a1-uart",
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"amlogic,meson-ao-uart";
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reg = <0x0 0x2000 0x0 0x18>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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saradc: adc@2c00 {
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compatible = "amlogic,meson-g12a-saradc",
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"amlogic,meson-saradc";
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reg = <0x0 0x2c00 0x0 0x48>;
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#io-channel-cells = <1>;
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power-domains = <&pwrc PWRC_I2C_ID>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>,
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<&clkc_periphs CLKID_SARADC_EN>,
|
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<&clkc_periphs CLKID_SARADC>,
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<&clkc_periphs CLKID_SARADC_SEL>;
|
||||
clock-names = "clkin", "core",
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"adc_clk", "adc_sel";
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status = "disabled";
|
||||
};
|
||||
|
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i2c1: i2c@5c00 {
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compatible = "amlogic,meson-axg-i2c";
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status = "disabled";
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reg = <0x0 0x5c00 0x0 0x20>;
|
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interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
|
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkc_periphs CLKID_I2C_M_B>;
|
||||
power-domains = <&pwrc PWRC_I2C_ID>;
|
||||
};
|
||||
|
||||
i2c2: i2c@6800 {
|
||||
compatible = "amlogic,meson-axg-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x6800 0x0 0x20>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkc_periphs CLKID_I2C_M_C>;
|
||||
power-domains = <&pwrc PWRC_I2C_ID>;
|
||||
};
|
||||
|
||||
i2c3: i2c@6c00 {
|
||||
compatible = "amlogic,meson-axg-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x0 0x6c00 0x0 0x20>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clkc_periphs CLKID_I2C_M_D>;
|
||||
power-domains = <&pwrc PWRC_I2C_ID>;
|
||||
};
|
||||
|
||||
usb2_phy1: phy@4000 {
|
||||
compatible = "amlogic,a1-usb2-phy";
|
||||
clocks = <&clkc_periphs CLKID_USB_PHY_IN>;
|
||||
clock-names = "xtal";
|
||||
reg = <0x0 0x4000 0x0 0x60>;
|
||||
resets = <&reset RESET_USBPHY>;
|
||||
reset-names = "phy";
|
||||
#phy-cells = <0>;
|
||||
power-domains = <&pwrc PWRC_USB_ID>;
|
||||
};
|
||||
|
||||
hwrng: rng@5118 {
|
||||
compatible = "amlogic,meson-rng";
|
||||
reg = <0x0 0x5118 0x0 0x4>;
|
||||
power-domains = <&pwrc PWRC_OTP_ID>;
|
||||
};
|
||||
|
||||
sec_AO: ao-secure@5a20 {
|
||||
compatible = "amlogic,meson-gx-ao-secure", "syscon";
|
||||
reg = <0x0 0x5a20 0x0 0x140>;
|
||||
amlogic,has-chip-id;
|
||||
};
|
||||
|
||||
clkc_pll: pll-clock-controller@7c80 {
|
||||
compatible = "amlogic,a1-pll-clkc";
|
||||
reg = <0 0x7c80 0 0x18c>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
|
||||
<&clkc_periphs CLKID_HIFIPLL_IN>;
|
||||
clock-names = "fixpll_in", "hifipll_in";
|
||||
};
|
||||
|
||||
sd_emmc: sd@10000 {
|
||||
compatible = "amlogic,meson-axg-mmc";
|
||||
reg = <0x0 0x10000 0x0 0x800>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
|
||||
<&clkc_periphs CLKID_SD_EMMC>,
|
||||
<&clkc_pll CLKID_FCLK_DIV2>;
|
||||
clock-names = "core",
|
||||
"clkin0",
|
||||
"clkin1";
|
||||
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
|
||||
assigned-clock-parents = <&xtal>;
|
||||
resets = <&reset RESET_SD_EMMC_A>;
|
||||
power-domains = <&pwrc PWRC_SD_EMMC_ID>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usb: usb@fe004400 {
|
||||
status = "disabled";
|
||||
compatible = "amlogic,meson-a1-usb-ctrl";
|
||||
reg = <0x0 0xfe004400 0x0 0xa0>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clocks = <&clkc_periphs CLKID_USB_CTRL>,
|
||||
<&clkc_periphs CLKID_USB_BUS>,
|
||||
<&clkc_periphs CLKID_USB_CTRL_IN>;
|
||||
clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
|
||||
resets = <&reset RESET_USBCTRL>;
|
||||
reset-name = "usb_ctrl";
|
||||
|
||||
dr_mode = "otg";
|
||||
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy1";
|
||||
|
||||
dwc3: usb@ff400000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xff400000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,parkmode-disable-ss-quirk;
|
||||
};
|
||||
|
||||
dwc2: usb@ff500000 {
|
||||
compatible = "amlogic,meson-a1-usb", "snps,dwc2";
|
||||
reg = <0x0 0xff500000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
clocks = <&clkc_periphs CLKID_USB_PHY>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "peripheral";
|
||||
g-rx-fifo-size = <192>;
|
||||
g-np-tx-fifo-size = <128>;
|
||||
g-tx-fifo-size = <128 128 16 16 16>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ff901000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x0 0xff901000 0x0 0x1000>,
|
||||
<0x0 0xff902000 0x0 0x2000>,
|
||||
<0x0 0xff904000 0x0 0x2000>,
|
||||
<0x0 0xff906000 0x0 0x2000>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
xtal: xtal-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xtal";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
"name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \
|
||||
"name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \
|
||||
"name=super,size=3072M,uuid=${uuid_gpt_super};" \
|
||||
"name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=rootfs,size=-,uuid=" ROOT_UUID
|
||||
#else
|
||||
#define PARTS_DEFAULT \
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
"name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \
|
||||
"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
|
||||
"name=super,size=1792M,uuid=${uuid_gpt_super};" \
|
||||
"name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=rootfs,size=-,uuid=" ROOT_UUID
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
"name=boot_a,size=64M,bootable,uuid=${uuid_gpt_boot_a};" \
|
||||
"name=boot_b,size=64M,bootable,uuid=${uuid_gpt_boot_b};" \
|
||||
"name=super,size=3072M,uuid=${uuid_gpt_super};" \
|
||||
"name=userdata,size=11282M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=userdata,size=11218M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=rootfs,size=-,uuid=" ROOT_UUID
|
||||
#else
|
||||
#define PARTS_DEFAULT \
|
||||
|
|
@ -37,7 +37,7 @@
|
|||
"name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \
|
||||
"name=cache,size=256M,uuid=${uuid_gpt_cache};" \
|
||||
"name=super,size=1792M,uuid=${uuid_gpt_super};" \
|
||||
"name=userdata,size=12786M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=userdata,size=12722M,uuid=${uuid_gpt_userdata};" \
|
||||
"name=rootfs,size=-,uuid=" ROOT_UUID
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,168 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
* Author: Jian Hu <jian.hu@amlogic.com>
|
||||
*
|
||||
* Copyright (c) 2023, SberDevices. All Rights Reserved.
|
||||
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
|
||||
*/
|
||||
|
||||
#ifndef __A1_PERIPHERALS_CLKC_H
|
||||
#define __A1_PERIPHERALS_CLKC_H
|
||||
|
||||
#define CLKID_XTAL_IN 0
|
||||
#define CLKID_FIXPLL_IN 1
|
||||
#define CLKID_USB_PHY_IN 2
|
||||
#define CLKID_USB_CTRL_IN 3
|
||||
#define CLKID_HIFIPLL_IN 4
|
||||
#define CLKID_SYSPLL_IN 5
|
||||
#define CLKID_DDS_IN 6
|
||||
#define CLKID_SYS 7
|
||||
#define CLKID_CLKTREE 8
|
||||
#define CLKID_RESET_CTRL 9
|
||||
#define CLKID_ANALOG_CTRL 10
|
||||
#define CLKID_PWR_CTRL 11
|
||||
#define CLKID_PAD_CTRL 12
|
||||
#define CLKID_SYS_CTRL 13
|
||||
#define CLKID_TEMP_SENSOR 14
|
||||
#define CLKID_AM2AXI_DIV 15
|
||||
#define CLKID_SPICC_B 16
|
||||
#define CLKID_SPICC_A 17
|
||||
#define CLKID_MSR 18
|
||||
#define CLKID_AUDIO 19
|
||||
#define CLKID_JTAG_CTRL 20
|
||||
#define CLKID_SARADC_EN 21
|
||||
#define CLKID_PWM_EF 22
|
||||
#define CLKID_PWM_CD 23
|
||||
#define CLKID_PWM_AB 24
|
||||
#define CLKID_CEC 25
|
||||
#define CLKID_I2C_S 26
|
||||
#define CLKID_IR_CTRL 27
|
||||
#define CLKID_I2C_M_D 28
|
||||
#define CLKID_I2C_M_C 29
|
||||
#define CLKID_I2C_M_B 30
|
||||
#define CLKID_I2C_M_A 31
|
||||
#define CLKID_ACODEC 32
|
||||
#define CLKID_OTP 33
|
||||
#define CLKID_SD_EMMC_A 34
|
||||
#define CLKID_USB_PHY 35
|
||||
#define CLKID_USB_CTRL 36
|
||||
#define CLKID_SYS_DSPB 37
|
||||
#define CLKID_SYS_DSPA 38
|
||||
#define CLKID_DMA 39
|
||||
#define CLKID_IRQ_CTRL 40
|
||||
#define CLKID_NIC 41
|
||||
#define CLKID_GIC 42
|
||||
#define CLKID_UART_C 43
|
||||
#define CLKID_UART_B 44
|
||||
#define CLKID_UART_A 45
|
||||
#define CLKID_SYS_PSRAM 46
|
||||
#define CLKID_RSA 47
|
||||
#define CLKID_CORESIGHT 48
|
||||
#define CLKID_AM2AXI_VAD 49
|
||||
#define CLKID_AUDIO_VAD 50
|
||||
#define CLKID_AXI_DMC 51
|
||||
#define CLKID_AXI_PSRAM 52
|
||||
#define CLKID_RAMB 53
|
||||
#define CLKID_RAMA 54
|
||||
#define CLKID_AXI_SPIFC 55
|
||||
#define CLKID_AXI_NIC 56
|
||||
#define CLKID_AXI_DMA 57
|
||||
#define CLKID_CPU_CTRL 58
|
||||
#define CLKID_ROM 59
|
||||
#define CLKID_PROC_I2C 60
|
||||
#define CLKID_DSPA_SEL 61
|
||||
#define CLKID_DSPB_SEL 62
|
||||
#define CLKID_DSPA_EN 63
|
||||
#define CLKID_DSPA_EN_NIC 64
|
||||
#define CLKID_DSPB_EN 65
|
||||
#define CLKID_DSPB_EN_NIC 66
|
||||
#define CLKID_RTC 67
|
||||
#define CLKID_CECA_32K 68
|
||||
#define CLKID_CECB_32K 69
|
||||
#define CLKID_24M 70
|
||||
#define CLKID_12M 71
|
||||
#define CLKID_FCLK_DIV2_DIVN 72
|
||||
#define CLKID_GEN 73
|
||||
#define CLKID_SARADC_SEL 74
|
||||
#define CLKID_SARADC 75
|
||||
#define CLKID_PWM_A 76
|
||||
#define CLKID_PWM_B 77
|
||||
#define CLKID_PWM_C 78
|
||||
#define CLKID_PWM_D 79
|
||||
#define CLKID_PWM_E 80
|
||||
#define CLKID_PWM_F 81
|
||||
#define CLKID_SPICC 82
|
||||
#define CLKID_TS 83
|
||||
#define CLKID_SPIFC 84
|
||||
#define CLKID_USB_BUS 85
|
||||
#define CLKID_SD_EMMC 86
|
||||
#define CLKID_PSRAM 87
|
||||
#define CLKID_DMC 88
|
||||
#define CLKID_SYS_A_SEL 89
|
||||
#define CLKID_SYS_A_DIV 90
|
||||
#define CLKID_SYS_A 91
|
||||
#define CLKID_SYS_B_SEL 92
|
||||
#define CLKID_SYS_B_DIV 93
|
||||
#define CLKID_SYS_B 94
|
||||
#define CLKID_DSPA_A_SEL 95
|
||||
#define CLKID_DSPA_A_DIV 96
|
||||
#define CLKID_DSPA_A 97
|
||||
#define CLKID_DSPA_B_SEL 98
|
||||
#define CLKID_DSPA_B_DIV 99
|
||||
#define CLKID_DSPA_B 100
|
||||
#define CLKID_DSPB_A_SEL 101
|
||||
#define CLKID_DSPB_A_DIV 102
|
||||
#define CLKID_DSPB_A 103
|
||||
#define CLKID_DSPB_B_SEL 104
|
||||
#define CLKID_DSPB_B_DIV 105
|
||||
#define CLKID_DSPB_B 106
|
||||
#define CLKID_RTC_32K_IN 107
|
||||
#define CLKID_RTC_32K_DIV 108
|
||||
#define CLKID_RTC_32K_XTAL 109
|
||||
#define CLKID_RTC_32K_SEL 110
|
||||
#define CLKID_CECB_32K_IN 111
|
||||
#define CLKID_CECB_32K_DIV 112
|
||||
#define CLKID_CECB_32K_SEL_PRE 113
|
||||
#define CLKID_CECB_32K_SEL 114
|
||||
#define CLKID_CECA_32K_IN 115
|
||||
#define CLKID_CECA_32K_DIV 116
|
||||
#define CLKID_CECA_32K_SEL_PRE 117
|
||||
#define CLKID_CECA_32K_SEL 118
|
||||
#define CLKID_DIV2_PRE 119
|
||||
#define CLKID_24M_DIV2 120
|
||||
#define CLKID_GEN_SEL 121
|
||||
#define CLKID_GEN_DIV 122
|
||||
#define CLKID_SARADC_DIV 123
|
||||
#define CLKID_PWM_A_SEL 124
|
||||
#define CLKID_PWM_A_DIV 125
|
||||
#define CLKID_PWM_B_SEL 126
|
||||
#define CLKID_PWM_B_DIV 127
|
||||
#define CLKID_PWM_C_SEL 128
|
||||
#define CLKID_PWM_C_DIV 129
|
||||
#define CLKID_PWM_D_SEL 130
|
||||
#define CLKID_PWM_D_DIV 131
|
||||
#define CLKID_PWM_E_SEL 132
|
||||
#define CLKID_PWM_E_DIV 133
|
||||
#define CLKID_PWM_F_SEL 134
|
||||
#define CLKID_PWM_F_DIV 135
|
||||
#define CLKID_SPICC_SEL 136
|
||||
#define CLKID_SPICC_DIV 137
|
||||
#define CLKID_SPICC_SEL2 138
|
||||
#define CLKID_TS_DIV 139
|
||||
#define CLKID_SPIFC_SEL 140
|
||||
#define CLKID_SPIFC_DIV 141
|
||||
#define CLKID_SPIFC_SEL2 142
|
||||
#define CLKID_USB_BUS_SEL 143
|
||||
#define CLKID_USB_BUS_DIV 144
|
||||
#define CLKID_SD_EMMC_SEL 145
|
||||
#define CLKID_SD_EMMC_DIV 146
|
||||
#define CLKID_SD_EMMC_SEL2 147
|
||||
#define CLKID_PSRAM_SEL 148
|
||||
#define CLKID_PSRAM_DIV 149
|
||||
#define CLKID_PSRAM_SEL2 150
|
||||
#define CLKID_DMC_SEL 151
|
||||
#define CLKID_DMC_DIV 152
|
||||
#define CLKID_DMC_SEL2 153
|
||||
|
||||
#endif /* __A1_PERIPHERALS_CLKC_H */
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
* Author: Jian Hu <jian.hu@amlogic.com>
|
||||
*
|
||||
* Copyright (c) 2023, SberDevices. All Rights Reserved.
|
||||
* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
|
||||
*/
|
||||
|
||||
#ifndef __A1_PLL_CLKC_H
|
||||
#define __A1_PLL_CLKC_H
|
||||
|
||||
#define CLKID_FIXED_PLL_DCO 0
|
||||
#define CLKID_FIXED_PLL 1
|
||||
#define CLKID_FCLK_DIV2_DIV 2
|
||||
#define CLKID_FCLK_DIV3_DIV 3
|
||||
#define CLKID_FCLK_DIV5_DIV 4
|
||||
#define CLKID_FCLK_DIV7_DIV 5
|
||||
#define CLKID_FCLK_DIV2 6
|
||||
#define CLKID_FCLK_DIV3 7
|
||||
#define CLKID_FCLK_DIV5 8
|
||||
#define CLKID_FCLK_DIV7 9
|
||||
#define CLKID_HIFI_PLL 10
|
||||
|
||||
#endif /* __A1_PLL_CLKC_H */
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2018 Baylibre SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
#define __AXG_AUDIO_CLKC_BINDINGS_H
|
||||
|
||||
#define AUD_CLKID_DDR_ARB 29
|
||||
#define AUD_CLKID_PDM 30
|
||||
#define AUD_CLKID_TDMIN_A 31
|
||||
#define AUD_CLKID_TDMIN_B 32
|
||||
#define AUD_CLKID_TDMIN_C 33
|
||||
#define AUD_CLKID_TDMIN_LB 34
|
||||
#define AUD_CLKID_TDMOUT_A 35
|
||||
#define AUD_CLKID_TDMOUT_B 36
|
||||
#define AUD_CLKID_TDMOUT_C 37
|
||||
#define AUD_CLKID_FRDDR_A 38
|
||||
#define AUD_CLKID_FRDDR_B 39
|
||||
#define AUD_CLKID_FRDDR_C 40
|
||||
#define AUD_CLKID_TODDR_A 41
|
||||
#define AUD_CLKID_TODDR_B 42
|
||||
#define AUD_CLKID_TODDR_C 43
|
||||
#define AUD_CLKID_LOOPBACK 44
|
||||
#define AUD_CLKID_SPDIFIN 45
|
||||
#define AUD_CLKID_SPDIFOUT 46
|
||||
#define AUD_CLKID_RESAMPLE 47
|
||||
#define AUD_CLKID_POWER_DETECT 48
|
||||
#define AUD_CLKID_MST_A_MCLK 49
|
||||
#define AUD_CLKID_MST_B_MCLK 50
|
||||
#define AUD_CLKID_MST_C_MCLK 51
|
||||
#define AUD_CLKID_MST_D_MCLK 52
|
||||
#define AUD_CLKID_MST_E_MCLK 53
|
||||
#define AUD_CLKID_MST_F_MCLK 54
|
||||
#define AUD_CLKID_SPDIFOUT_CLK 55
|
||||
#define AUD_CLKID_SPDIFIN_CLK 56
|
||||
#define AUD_CLKID_PDM_DCLK 57
|
||||
#define AUD_CLKID_PDM_SYSCLK 58
|
||||
#define AUD_CLKID_MST_A_SCLK 79
|
||||
#define AUD_CLKID_MST_B_SCLK 80
|
||||
#define AUD_CLKID_MST_C_SCLK 81
|
||||
#define AUD_CLKID_MST_D_SCLK 82
|
||||
#define AUD_CLKID_MST_E_SCLK 83
|
||||
#define AUD_CLKID_MST_F_SCLK 84
|
||||
#define AUD_CLKID_MST_A_LRCLK 86
|
||||
#define AUD_CLKID_MST_B_LRCLK 87
|
||||
#define AUD_CLKID_MST_C_LRCLK 88
|
||||
#define AUD_CLKID_MST_D_LRCLK 89
|
||||
#define AUD_CLKID_MST_E_LRCLK 90
|
||||
#define AUD_CLKID_MST_F_LRCLK 91
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122
|
||||
#define AUD_CLKID_TDMIN_A_SCLK 123
|
||||
#define AUD_CLKID_TDMIN_B_SCLK 124
|
||||
#define AUD_CLKID_TDMIN_C_SCLK 125
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK 126
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK 127
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK 128
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK 129
|
||||
#define AUD_CLKID_TDMIN_A_LRCLK 130
|
||||
#define AUD_CLKID_TDMIN_B_LRCLK 131
|
||||
#define AUD_CLKID_TDMIN_C_LRCLK 132
|
||||
#define AUD_CLKID_TDMIN_LB_LRCLK 133
|
||||
#define AUD_CLKID_TDMOUT_A_LRCLK 134
|
||||
#define AUD_CLKID_TDMOUT_B_LRCLK 135
|
||||
#define AUD_CLKID_TDMOUT_C_LRCLK 136
|
||||
#define AUD_CLKID_SPDIFOUT_B 151
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK 152
|
||||
#define AUD_CLKID_TDM_MCLK_PAD0 155
|
||||
#define AUD_CLKID_TDM_MCLK_PAD1 156
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD0 157
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD1 158
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD2 159
|
||||
#define AUD_CLKID_TDM_SCLK_PAD0 160
|
||||
#define AUD_CLKID_TDM_SCLK_PAD1 161
|
||||
#define AUD_CLKID_TDM_SCLK_PAD2 162
|
||||
#define AUD_CLKID_TOP 163
|
||||
#define AUD_CLKID_TORAM 164
|
||||
#define AUD_CLKID_EQDRC 165
|
||||
#define AUD_CLKID_RESAMPLE_B 166
|
||||
#define AUD_CLKID_TOVAD 167
|
||||
#define AUD_CLKID_LOCKER 168
|
||||
#define AUD_CLKID_SPDIFIN_LB 169
|
||||
#define AUD_CLKID_FRDDR_D 170
|
||||
#define AUD_CLKID_TODDR_D 171
|
||||
#define AUD_CLKID_LOOPBACK_B 172
|
||||
|
||||
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Meson-AXG clock tree IDs
|
||||
*
|
||||
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __AXG_CLKC_H
|
||||
#define __AXG_CLKC_H
|
||||
|
||||
#define CLKID_SYS_PLL 0
|
||||
#define CLKID_FIXED_PLL 1
|
||||
#define CLKID_FCLK_DIV2 2
|
||||
#define CLKID_FCLK_DIV3 3
|
||||
#define CLKID_FCLK_DIV4 4
|
||||
#define CLKID_FCLK_DIV5 5
|
||||
#define CLKID_FCLK_DIV7 6
|
||||
#define CLKID_GP0_PLL 7
|
||||
#define CLKID_CLK81 10
|
||||
#define CLKID_MPLL0 11
|
||||
#define CLKID_MPLL1 12
|
||||
#define CLKID_MPLL2 13
|
||||
#define CLKID_MPLL3 14
|
||||
#define CLKID_DDR 15
|
||||
#define CLKID_AUDIO_LOCKER 16
|
||||
#define CLKID_MIPI_DSI_HOST 17
|
||||
#define CLKID_ISA 18
|
||||
#define CLKID_PL301 19
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC0 21
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_RNG0 23
|
||||
#define CLKID_UART0 24
|
||||
#define CLKID_MIPI_DSI_PHY 25
|
||||
#define CLKID_SPICC1 26
|
||||
#define CLKID_PCIE_A 27
|
||||
#define CLKID_PCIE_B 28
|
||||
#define CLKID_HIU_IFACE 29
|
||||
#define CLKID_ASSIST_MISC 30
|
||||
#define CLKID_SD_EMMC_B 31
|
||||
#define CLKID_SD_EMMC_C 32
|
||||
#define CLKID_DMA 33
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_AUDIO 35
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_UART1 37
|
||||
#define CLKID_G2D 38
|
||||
#define CLKID_USB0 39
|
||||
#define CLKID_USB1 40
|
||||
#define CLKID_RESET 41
|
||||
#define CLKID_USB 42
|
||||
#define CLKID_AHB_ARB0 43
|
||||
#define CLKID_EFUSE 44
|
||||
#define CLKID_BOOT_ROM 45
|
||||
#define CLKID_AHB_DATA_BUS 46
|
||||
#define CLKID_AHB_CTRL_BUS 47
|
||||
#define CLKID_USB1_DDR_BRIDGE 48
|
||||
#define CLKID_USB0_DDR_BRIDGE 49
|
||||
#define CLKID_MMC_PCLK 50
|
||||
#define CLKID_VPU_INTR 51
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 52
|
||||
#define CLKID_GIC 53
|
||||
#define CLKID_AO_MEDIA_CPU 54
|
||||
#define CLKID_AO_AHB_SRAM 55
|
||||
#define CLKID_AO_AHB_BUS 56
|
||||
#define CLKID_AO_IFACE 57
|
||||
#define CLKID_AO_I2C 58
|
||||
#define CLKID_SD_EMMC_B_CLK0 59
|
||||
#define CLKID_SD_EMMC_C_CLK0 60
|
||||
#define CLKID_HIFI_PLL 69
|
||||
#define CLKID_PCIE_CML_EN0 79
|
||||
#define CLKID_PCIE_CML_EN1 80
|
||||
#define CLKID_GEN_CLK 84
|
||||
#define CLKID_VPU_0_SEL 92
|
||||
#define CLKID_VPU_0 93
|
||||
#define CLKID_VPU_1_SEL 95
|
||||
#define CLKID_VPU_1 96
|
||||
#define CLKID_VPU 97
|
||||
#define CLKID_VAPB_0_SEL 99
|
||||
#define CLKID_VAPB_0 100
|
||||
#define CLKID_VAPB_1_SEL 102
|
||||
#define CLKID_VAPB_1 103
|
||||
#define CLKID_VAPB_SEL 104
|
||||
#define CLKID_VAPB 105
|
||||
#define CLKID_VCLK 106
|
||||
#define CLKID_VCLK2 107
|
||||
#define CLKID_VCLK_DIV1 122
|
||||
#define CLKID_VCLK_DIV2 123
|
||||
#define CLKID_VCLK_DIV4 124
|
||||
#define CLKID_VCLK_DIV6 125
|
||||
#define CLKID_VCLK_DIV12 126
|
||||
#define CLKID_VCLK2_DIV1 127
|
||||
#define CLKID_VCLK2_DIV2 128
|
||||
#define CLKID_VCLK2_DIV4 129
|
||||
#define CLKID_VCLK2_DIV6 130
|
||||
#define CLKID_VCLK2_DIV12 131
|
||||
#define CLKID_CTS_ENCL 133
|
||||
#define CLKID_VDIN_MEAS 136
|
||||
|
||||
#endif /* __AXG_CLKC_H */
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
* Author: Qianggui Song <qianggui.song@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
|
||||
#define _DT_BINDINGS_MESON_A1_GPIO_H
|
||||
|
||||
#define GPIOP_0 0
|
||||
#define GPIOP_1 1
|
||||
#define GPIOP_2 2
|
||||
#define GPIOP_3 3
|
||||
#define GPIOP_4 4
|
||||
#define GPIOP_5 5
|
||||
#define GPIOP_6 6
|
||||
#define GPIOP_7 7
|
||||
#define GPIOP_8 8
|
||||
#define GPIOP_9 9
|
||||
#define GPIOP_10 10
|
||||
#define GPIOP_11 11
|
||||
#define GPIOP_12 12
|
||||
#define GPIOB_0 13
|
||||
#define GPIOB_1 14
|
||||
#define GPIOB_2 15
|
||||
#define GPIOB_3 16
|
||||
#define GPIOB_4 17
|
||||
#define GPIOB_5 18
|
||||
#define GPIOB_6 19
|
||||
#define GPIOX_0 20
|
||||
#define GPIOX_1 21
|
||||
#define GPIOX_2 22
|
||||
#define GPIOX_3 23
|
||||
#define GPIOX_4 24
|
||||
#define GPIOX_5 25
|
||||
#define GPIOX_6 26
|
||||
#define GPIOX_7 27
|
||||
#define GPIOX_8 28
|
||||
#define GPIOX_9 29
|
||||
#define GPIOX_10 30
|
||||
#define GPIOX_11 31
|
||||
#define GPIOX_12 32
|
||||
#define GPIOX_13 33
|
||||
#define GPIOX_14 34
|
||||
#define GPIOX_15 35
|
||||
#define GPIOX_16 36
|
||||
#define GPIOF_0 37
|
||||
#define GPIOF_1 38
|
||||
#define GPIOF_2 39
|
||||
#define GPIOF_3 40
|
||||
#define GPIOF_4 41
|
||||
#define GPIOF_5 42
|
||||
#define GPIOF_6 43
|
||||
#define GPIOF_7 44
|
||||
#define GPIOF_8 45
|
||||
#define GPIOF_9 46
|
||||
#define GPIOF_10 47
|
||||
#define GPIOF_11 48
|
||||
#define GPIOF_12 49
|
||||
#define GPIOA_0 50
|
||||
#define GPIOA_1 51
|
||||
#define GPIOA_2 52
|
||||
#define GPIOA_3 53
|
||||
#define GPIOA_4 54
|
||||
#define GPIOA_5 55
|
||||
#define GPIOA_6 56
|
||||
#define GPIOA_7 57
|
||||
#define GPIOA_8 58
|
||||
#define GPIOA_9 59
|
||||
#define GPIOA_10 60
|
||||
#define GPIOA_11 61
|
||||
|
||||
#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* This header provides constants for the ARM GIC.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
|
||||
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/* interrupt specifier cell 0 */
|
||||
|
||||
#define GIC_SPI 0
|
||||
#define GIC_PPI 1
|
||||
|
||||
/*
|
||||
* Interrupt specifier cell 2.
|
||||
* The flags in irq.h are valid, plus those below.
|
||||
*/
|
||||
#define GIC_CPU_MASK_RAW(x) ((x) << 8)
|
||||
#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (c) 2023 SberDevices, Inc.
|
||||
* Author: Alexey Romanov <avromanov@sberdevices.ru>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_A1_POWER_H
|
||||
#define _DT_BINDINGS_MESON_A1_POWER_H
|
||||
|
||||
#define PWRC_DSPA_ID 8
|
||||
#define PWRC_DSPB_ID 9
|
||||
#define PWRC_UART_ID 10
|
||||
#define PWRC_DMC_ID 11
|
||||
#define PWRC_I2C_ID 12
|
||||
#define PWRC_PSRAM_ID 13
|
||||
#define PWRC_ACODEC_ID 14
|
||||
#define PWRC_AUDIO_ID 15
|
||||
#define PWRC_OTP_ID 16
|
||||
#define PWRC_DMA_ID 17
|
||||
#define PWRC_SD_EMMC_ID 18
|
||||
#define PWRC_RAMA_ID 19
|
||||
#define PWRC_RAMB_ID 20
|
||||
#define PWRC_IR_ID 21
|
||||
#define PWRC_SPICC_ID 22
|
||||
#define PWRC_SPIFC_ID 23
|
||||
#define PWRC_USB_ID 24
|
||||
#define PWRC_NIC_ID 25
|
||||
#define PWRC_PDMIN_ID 26
|
||||
#define PWRC_RSA_ID 27
|
||||
#define PWRC_MAX_ID 28
|
||||
|
||||
#endif
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
|
||||
* Author: Xingyu Chen <xingyu.chen@amlogic.com>
|
||||
*
|
||||
* Copyright (c) 2023, SberDevices, Inc.
|
||||
* Author: Alexey Romanov <avromanov@salutedevices.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
/* 0 */
|
||||
#define RESET_AM2AXI_VAD 1
|
||||
/* 2-3 */
|
||||
#define RESET_PSRAM 4
|
||||
#define RESET_PAD_CTRL 5
|
||||
/* 6 */
|
||||
#define RESET_TEMP_SENSOR 7
|
||||
#define RESET_AM2AXI_DEV 8
|
||||
/* 9 */
|
||||
#define RESET_SPICC_A 10
|
||||
#define RESET_MSR_CLK 11
|
||||
#define RESET_AUDIO 12
|
||||
#define RESET_ANALOG_CTRL 13
|
||||
#define RESET_SAR_ADC 14
|
||||
#define RESET_AUDIO_VAD 15
|
||||
#define RESET_CEC 16
|
||||
#define RESET_PWM_EF 17
|
||||
#define RESET_PWM_CD 18
|
||||
#define RESET_PWM_AB 19
|
||||
/* 20 */
|
||||
#define RESET_IR_CTRL 21
|
||||
#define RESET_I2C_S_A 22
|
||||
/* 23 */
|
||||
#define RESET_I2C_M_D 24
|
||||
#define RESET_I2C_M_C 25
|
||||
#define RESET_I2C_M_B 26
|
||||
#define RESET_I2C_M_A 27
|
||||
#define RESET_I2C_PROD_AHB 28
|
||||
#define RESET_I2C_PROD 29
|
||||
/* 30-31 */
|
||||
|
||||
/* RESET1 */
|
||||
#define RESET_ACODEC 32
|
||||
#define RESET_DMA 33
|
||||
#define RESET_SD_EMMC_A 34
|
||||
/* 35 */
|
||||
#define RESET_USBCTRL 36
|
||||
/* 37 */
|
||||
#define RESET_USBPHY 38
|
||||
/* 39-41 */
|
||||
#define RESET_RSA 42
|
||||
#define RESET_DMC 43
|
||||
/* 44 */
|
||||
#define RESET_IRQ_CTRL 45
|
||||
/* 46 */
|
||||
#define RESET_NIC_VAD 47
|
||||
#define RESET_NIC_AXI 48
|
||||
#define RESET_RAMA 49
|
||||
#define RESET_RAMB 50
|
||||
/* 51-52 */
|
||||
#define RESET_ROM 53
|
||||
#define RESET_SPIFC 54
|
||||
#define RESET_GIC 55
|
||||
#define RESET_UART_C 56
|
||||
#define RESET_UART_B 57
|
||||
#define RESET_UART_A 58
|
||||
#define RESET_OSC_RING 59
|
||||
/* 60-63 */
|
||||
|
||||
/* RESET2 */
|
||||
/* 64-95 */
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue