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dts: rockchip: px30: add gpio-ranges property to gpio nodes

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Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".

Fixes: 537b1a2774 ("rockchip: add px30 devicetrees")

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Chris Morgan 2023-02-13 16:27:35 -06:00 • committed by Kever Yang
parent 904b8700f8
commit 02cbda2b72
1 changed files with 4 additions and 0 deletions
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4
arch/arm/dts/px30.dtsi
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@ -1366,6 +1366,7 @@
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0_PMU>; clocks = <&pmucru PCLK_GPIO0_PMU>;
gpio-controller; gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
@ -1378,6 +1379,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>; clocks = <&cru PCLK_GPIO1>;
gpio-controller; gpio-controller;
gpio-ranges = <&pinctrl 0 32 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
@ -1390,6 +1392,7 @@
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>; clocks = <&cru PCLK_GPIO2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pinctrl 0 64 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
@ -1402,6 +1405,7 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>; clocks = <&cru PCLK_GPIO3>;
gpio-controller; gpio-controller;
gpio-ranges = <&pinctrl 0 96 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;